[][Update Ethernet procfs-based debug register dump]
[Description]
Change Ethernet procfs-based debug register dump.
- Usage:
- cat /proc/mtketh/dbg_regs
- What's new:
- FE_INT_STA: Frame Engine Interrupt Status
- PSE_IQ_STA5: PSE Input Queue Status part5
- PSE_OQ_STA5: PSE Output Queue Status part5
- PDMA_CRX_IDX: PDMA CPU pointer
- PDMA_DRX_IDX: PDMA DMA pointer
- QDMA_CTX_IDX: QDMA CPU pointer
- QDMA_DTX_IDX: QDMA DMA pointer
- MAC_P1_FSM: GMAC1 finite state machine
- MAC_P2_FSM: GMAC2 finite state machine
- FE_CDM3_FSM: CDM finite state machine for WDMA0
- FE_CDM4_FSM: CDM finite state machine for WDMA1
- SGMII_EFUSE: SGMII E-Fuse value, which can be used
to check whether DUT is calibrated
- SGMII_RX_CNT: SGMII false carrier count, which can
be used to check whether SGMII detects
frame starts
- WED_RTQM_GLO: WED Rx route QM global configuration,
which can be used to check whether
WED stays in Q_FULL state
[Release-log]
N/A
Change-Id: I9f95e9140d1e99415d14b7cc6bc2ebbe504b40a2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5081805
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
index 979bc9b..e2bf16f 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
@@ -725,11 +725,30 @@
.release = single_release
};
+static inline u32 mtk_dbg_r32(u32 reg)
+{
+ void __iomem *virt_reg;
+ u32 val;
+
+ virt_reg = ioremap(reg, 32);
+ val = __raw_readl(virt_reg);
+ iounmap(virt_reg);
+
+ return val;
+}
+
int dbg_regs_read(struct seq_file *seq, void *v)
{
struct mtk_eth *eth = g_eth;
- seq_puts(seq, " <<PSE DEBUG REG DUMP>>\n");
+ seq_puts(seq, " <<DEBUG REG DUMP>>\n");
+
+ seq_printf(seq, "| FE_INT_STA : %08x |\n",
+ mtk_r32(eth, MTK_INT_STATUS));
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ seq_printf(seq, "| FE_INT_STA2 : %08x |\n",
+ mtk_r32(eth, MTK_INT_STATUS2));
+
seq_printf(seq, "| PSE_FQFC_CFG : %08x |\n",
mtk_r32(eth, MTK_PSE_FQFC_CFG));
seq_printf(seq, "| PSE_IQ_STA1 : %08x |\n",
@@ -742,6 +761,8 @@
mtk_r32(eth, MTK_PSE_IQ_STA(2)));
seq_printf(seq, "| PSE_IQ_STA4 : %08x |\n",
mtk_r32(eth, MTK_PSE_IQ_STA(3)));
+ seq_printf(seq, "| PSE_IQ_STA5 : %08x |\n",
+ mtk_r32(eth, MTK_PSE_IQ_STA(4)));
}
seq_printf(seq, "| PSE_OQ_STA1 : %08x |\n",
@@ -754,8 +775,18 @@
mtk_r32(eth, MTK_PSE_OQ_STA(2)));
seq_printf(seq, "| PSE_OQ_STA4 : %08x |\n",
mtk_r32(eth, MTK_PSE_OQ_STA(3)));
+ seq_printf(seq, "| PSE_OQ_STA5 : %08x |\n",
+ mtk_r32(eth, MTK_PSE_OQ_STA(4)));
}
+ seq_printf(seq, "| PDMA_CRX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_PRX_CRX_IDX0));
+ seq_printf(seq, "| PDMA_DRX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_PRX_DRX_IDX0));
+ seq_printf(seq, "| QDMA_CTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_QTX_CTX_PTR));
+ seq_printf(seq, "| QDMA_DTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_QTX_DTX_PTR));
seq_printf(seq, "| QDMA_FQ_CNT : %08x |\n",
mtk_r32(eth, MTK_QDMA_FQ_CNT));
seq_printf(seq, "| FE_PSE_FREE : %08x |\n",
@@ -774,18 +805,38 @@
mtk_r32(eth, MTK_MAC_MCR(0)));
seq_printf(seq, "| MAC_P2_MCR : %08x |\n",
mtk_r32(eth, MTK_MAC_MCR(1)));
+ seq_printf(seq, "| MAC_P1_FSM : %08x |\n",
+ mtk_r32(eth, MTK_MAC_FSM(0)));
+ seq_printf(seq, "| MAC_P2_FSM : %08x |\n",
+ mtk_r32(eth, MTK_MAC_FSM(1)));
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
seq_printf(seq, "| FE_CDM1_FSM : %08x |\n",
mtk_r32(eth, MTK_FE_CDM1_FSM));
seq_printf(seq, "| FE_CDM2_FSM : %08x |\n",
mtk_r32(eth, MTK_FE_CDM2_FSM));
+ seq_printf(seq, "| FE_CDM3_FSM : %08x |\n",
+ mtk_r32(eth, MTK_FE_CDM3_FSM));
+ seq_printf(seq, "| FE_CDM4_FSM : %08x |\n",
+ mtk_r32(eth, MTK_FE_CDM4_FSM));
seq_printf(seq, "| FE_GDM1_FSM : %08x |\n",
mtk_r32(eth, MTK_FE_GDM1_FSM));
seq_printf(seq, "| FE_GDM2_FSM : %08x |\n",
mtk_r32(eth, MTK_FE_GDM2_FSM));
+ seq_printf(seq, "| SGMII_EFUSE : %08x |\n",
+ mtk_dbg_r32(MTK_SGMII_EFUSE));
+ seq_printf(seq, "| SGMII0_RX_CNT : %08x |\n",
+ mtk_dbg_r32(MTK_SGMII_FALSE_CARRIER_CNT(0)));
+ seq_printf(seq, "| SGMII1_RX_CNT : %08x |\n",
+ mtk_dbg_r32(MTK_SGMII_FALSE_CARRIER_CNT(1)));
+ seq_printf(seq, "| WED_RTQM_GLO : %08x |\n",
+ mtk_dbg_r32(MTK_WED_RTQM_GLO_CFG));
}
+ mtk_w32(eth, 0xffffffff, MTK_INT_STATUS);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ mtk_w32(eth, 0xffffffff, MTK_INT_STATUS2);
+
return 0;
}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.h
index b44f93e..ea147b7 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.h
@@ -22,12 +22,18 @@
#define MTK_PSE_FQFC_CFG 0x100
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
+#define MTK_FE_CDM3_FSM 0x238
+#define MTK_FE_CDM4_FSM 0x298
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
#define MTK_FE_PSE_FREE 0x240
#define MTK_FE_DROP_FQ 0x244
#define MTK_FE_DROP_FC 0x248
#define MTK_FE_DROP_PPE 0x24C
+#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
+#define MTK_SGMII_FALSE_CARRIER_CNT(x) (0x10060028 + ((x) * 0x10000))
+#define MTK_SGMII_EFUSE 0x11D008C8
+#define MTK_WED_RTQM_GLO_CFG 0x15010B00
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#define MTK_PSE_IQ_STA(x) (0x180 + (x) * 0x4)
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 6b55c3d..4396762 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1644,12 +1644,12 @@
static void mtk_handle_status_irq(struct mtk_eth *eth)
{
- u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
+ u32 status2 = mtk_r32(eth, MTK_INT_STATUS);
if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
mtk_stats_update(eth);
mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
- MTK_INT_STATUS2);
+ MTK_INT_STATUS);
}
}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a6995df..b8c0728 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -61,7 +61,8 @@
#define RST_GL_PSE BIT(0)
/* Frame Engine Interrupt Status Register */
-#define MTK_INT_STATUS2 0x08
+#define MTK_INT_STATUS 0x08
+#define MTK_INT_STATUS2 0x28
#define MTK_GDM1_AF BIT(28)
#define MTK_GDM2_AF BIT(29)
@@ -148,6 +149,10 @@
#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08)
#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
+/* PDMA RX DMA Pointer Register */
+#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c)
+#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10))
+
/* PDMA HW LRO Control Registers */
#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
#if defined(CONFIG_MEDIATEK_NETSYS_V2)