[][MAC80211][hnat][Fix 64B short packets test cannot reach line rate for the mt7988]
[Description]
Fix 64B short packets test cannot reach line rate for the mt7988.
This patch enables the SRH_CACHE_FIRST_EN and CS0_PIPE_EN features
to improve PPE forwarding performance.
Without this patch, the 64B short packets test cannot reach line
rate for the mt7988.
[Release-log]
N/A
Change-Id: Ia17d11a21cc7398268d03ba4a7d4c0589e2739fb
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/8280735
diff --git a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3015-ethernet-update-ppe-from-netsys2-to-netsys3.patch b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3015-ethernet-update-ppe-from-netsys2-to-netsys3.patch
index 12a3ba8..bedf09e 100644
--- a/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3015-ethernet-update-ppe-from-netsys2-to-netsys3.patch
+++ b/autobuild_mac80211_release/target/linux/mediatek/patches-5.4/999-3015-ethernet-update-ppe-from-netsys2-to-netsys3.patch
@@ -1,22 +1,22 @@
-From 1e2da129898cd45b4196c0aaf2de9d0e9ed46d77 Mon Sep 17 00:00:00 2001
+From 5481f7ecbd3cfffd8234bc8e952a6e07f42de76c Mon Sep 17 00:00:00 2001
From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
-Date: Wed, 25 Oct 2023 11:39:09 +0800
+Date: Tue, 21 Nov 2023 16:42:01 +0800
Subject: [PATCH 16/22] ethernet-update-ppe-from-netsys2-to-netsys3
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++---
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 9 +++--
- drivers/net/ethernet/mediatek/mtk_ppe.c | 31 ++++++++++++---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 ++--
+ drivers/net/ethernet/mediatek/mtk_ppe.c | 35 ++++++++++++++---
drivers/net/ethernet/mediatek/mtk_ppe.h | 38 ++++++++++++++++---
.../net/ethernet/mediatek/mtk_ppe_offload.c | 6 ++-
- drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 5 +++
- 6 files changed, 81 insertions(+), 22 deletions(-)
+ drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 7 ++++
+ 6 files changed, 85 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-index 31c60a0..37355d9 100644
+index 850bc4f..8910d40 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2244,17 +2244,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
+@@ -2248,17 +2248,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, netdev);
@@ -38,7 +38,7 @@
reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5);
if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) {
for (i = 0; i < eth->ppe_num; i++) {
-@@ -5262,7 +5262,8 @@ static int mtk_probe(struct platform_device *pdev)
+@@ -5290,7 +5290,8 @@ static int mtk_probe(struct platform_device *pdev)
for (i = 0; i < eth->ppe_num; i++) {
eth->ppe[i] = mtk_ppe_init(eth,
@@ -48,7 +48,7 @@
2, eth->soc->hash_way, i,
eth->soc->has_accounting);
if (!eth->ppe[i]) {
-@@ -5529,6 +5530,9 @@ static const struct mtk_soc_data mt7988_data = {
+@@ -5557,6 +5558,9 @@ static const struct mtk_soc_data mt7988_data = {
.required_clks = MT7988_CLKS_BITMAP,
.required_pctl = false,
.has_sram = true,
@@ -59,10 +59,10 @@
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2),
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-index 0282d25..48ecdc8 100644
+index 9c77f14..c7d36c5 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -130,9 +130,10 @@
+@@ -134,9 +134,10 @@
#define MTK_GDMA_UCS_EN BIT(20)
#define MTK_GDMA_STRP_CRC BIT(16)
#define MTK_GDMA_TO_PDMA 0x0
@@ -74,7 +74,7 @@
#else
#define MTK_GDMA_TO_PPE0 0x4444
#endif
-@@ -1972,13 +1973,13 @@ extern u32 dbg_show_level;
+@@ -1978,14 +1979,14 @@ extern u32 dbg_show_level;
static inline void mtk_set_ib1_sp(struct mtk_eth *eth, struct mtk_foe_entry *foe, u32 val)
{
@@ -91,9 +91,8 @@
return FIELD_GET(MTK_FOE_IB1_UNBIND_SRC_PORT, foe->ib1);
#else
return 0;
- #endif
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
-index 1ed1b60..5a1036f 100755
+index 8388f65..184e29d 100755
--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
@@ -91,7 +91,7 @@ static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe)
@@ -183,7 +182,16 @@
MTK_PPE_TB_CFG_INFO_SEL |
#endif
FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
-@@ -993,7 +1012,7 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+@@ -988,12 +1007,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe)
+ MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
+ MTK_PPE_GLO_CFG_IP4_CS_DROP |
+ MTK_PPE_GLO_CFG_MCAST_TB_EN |
++#if defined(CONFIG_MEDIATEK_NETSYS_V3)
++ MTK_PPE_GLO_CFG_CS0_PIPE_EN |
++ MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN |
++#endif
+ MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
+ ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
@@ -308,10 +316,19 @@
ctx.dev = idev;
idev->netdev_ops->ndo_fill_receive_path(&ctx, &path);
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
-index 8d3ebe1..f8425df 100644
+index 8d3ebe1..55b9b0c 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
-@@ -155,9 +155,14 @@ enum {
+@@ -18,6 +18,8 @@
+ #define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
+ #define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
+ #define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
++#define MTK_PPE_GLO_CFG_CS0_PIPE_EN BIT(29)
++#define MTK_PPE_GLO_CFG_SRH_CACHE_FIRST_EN BIT(30)
+ #define MTK_PPE_GLO_CFG_BUSY BIT(31)
+
+ #define MTK_PPE_FLOW_CFG 0x204
+@@ -155,9 +157,14 @@ enum {
#define MTK_PPE_MIB_SER_R1 0x344
#define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16)
#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)