| commit | 6aa00169a7ab2e5bd7a3db1b0bedc21ea2efe77d | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Mon Mar 20 11:56:51 2023 +0800 |
| committer | developer <developer@mediatek.com> | Wed Mar 22 15:45:14 2023 +0800 |
| tree | c63a82ea370aa47fbfd55a7c1bd673555221e5a9 | |
| parent | 7f1906350481ed86c46e45b8d93a33f180708613 [diff] [blame] |
[][kernel][mt7988][eth][Refactor USXGMII reset sequence] [Description] Refactor USXGMII reset sequence. If without this patch, SGMII might be reset as well when resetting USXGMII. [Release-log] N/A Change-Id: I7bef3a542b06c2beb339f117fc27a40cacac3bf0 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7267722
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 5b860d6..32b7f6b 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -923,6 +923,8 @@ #define SWSYSRST_XFI_PLL_GRST BIT(16) #define SWSYSRST_XFI_PEXPT1_GRST BIT(15) #define SWSYSRST_XFI_PEXPT0_GRST BIT(14) +#define SWSYSRST_XFI1_GRST BIT(13) +#define SWSYSRST_XFI0_GRST BIT(12) #define SWSYSRST_SGMII1_GRST BIT(2) #define SWSYSRST_SGMII0_GRST BIT(1) #define TOPRGU_SWSYSRST_EN 0xFC