commit 637f555f1fe794d435e467673c5ff6a40d38e2e8
author developer <developer@mediatek.com> Thu May 27 17:45:27 2021 +0800
committer developer <developer@mediatek.com> Tue Jun 01 11:56:44 2021 +0800
tree ae8dbb69ce38e0a953aac7dddfaa4d1666708dde
parent 19d22f6fc62062d735e11e64733b43a009318062

[][OpenWrt Dev][Add mmc0 node to IAP board]

[Description]
Add mmc0 node to IAP board

[Release-log]
N/A

Change-Id: Ia49859a08d05ee8f01d819ac887b52c7ef3b47e0
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4586296

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
index bddab9e..8914201 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
@@ -267,6 +267,20 @@
 	status = "okay";
 };
 
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	bus-width = <8>;
+	max-frequency = <50000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	status = "okay";
+};
+
 &pio {
 	spi_flash_pins: spi0-pins {
 		mux {
@@ -288,4 +302,18 @@
 			groups = "spi1_2";
 		};
 	};
+
+	mmc0_pins_default: mmc0-pins-default {
+		mux {
+			function = "flash";
+			groups = "emmc_51";
+		};
+	};
+
+	mmc0_pins_uhs: mmc0-pins-uhs {
+		mux {
+			function = "flash";
+			groups = "emmc_51";
+		};
+	};
 };

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index dfefc76..13ac994 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -429,6 +429,18 @@
 		status = "disabled";
 	};
 
+	mmc0: mmc@11230000 {
+		compatible = "mediatek,mt7986-mmc";
+		reg = <0 0x11230000 0 0x1000>,
+			<0 0x11c20000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&uart_clk>,
+			<&uart_clk>,
+			<&uart_clk>;
+		clock-names = "source", "hclk", "source_cg";
+		status = "disabled";
+	};
+
 	auxadc: adc@1100d000 {
 		compatible = "mediatek,mt7986-auxadc",
 			     "mediatek,mt7622-auxadc";