[][openwrt][update the patches in accordance with the new naming rules]
[Description]
Change all mtk patches in accordance with the new naming rules
"999-20xx-" : Basic Part
"999-21xx-" : Slow Speed I/O
"999-22xx-" : Slow Speed I/O
"999-23xx-" : SPI & Storage
"999-24xx-" : SPI & Storage
"999-25xx-" : Advanced features
"999-26xx-" : High Speed I/O
"999-27xx-" : Networking
"999-28xx-" : MISC
"999-29xx-" : Uncategorized
[Release-log]
N/A
Change-Id: I245da3b0e5b7299b42473c20cc6f0899cffc1ad2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7530987
diff --git a/target/linux/mediatek/patches-5.4/999-2610-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-5.4/999-2610-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch
new file mode 100644
index 0000000..bf3a3c7
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/999-2610-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch
@@ -0,0 +1,156 @@
+From 3ef64d448a36853279de5324f9bf00041b9f3ce5 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 2 Jun 2023 13:06:25 +0800
+Subject: [PATCH]
+ [high-speed-io][999-2610-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch]
+
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 83 ++++++++++++++++++++++++++++-
+ 1 file changed, 81 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
+index d1ecf0880..c6e073401 100644
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -10,6 +10,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/iopoll.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+@@ -268,6 +269,14 @@
+ #define HIF_SYSCFG1 0x14
+ #define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
+
++/* PHY switch between pcie/usb3/sgmii/sata */
++#define USB_PHY_SWITCH_CTRL 0x0
++#define RG_PHY_SW_TYPE GENMASK(3, 0)
++#define RG_PHY_SW_PCIE 0x0
++#define RG_PHY_SW_USB3 0x1
++#define RG_PHY_SW_SGMII 0x2
++#define RG_PHY_SW_SATA 0x3
++
+ enum mtk_phy_version {
+ MTK_PHY_V1 = 1,
+ MTK_PHY_V2,
+@@ -301,7 +310,10 @@ struct mtk_phy_instance {
+ };
+ struct clk *ref_clk; /* reference clock of anolog phy */
+ u32 index;
+- u8 type;
++ u32 type;
++ struct regmap *type_sw;
++ u32 type_sw_reg;
++ u32 type_sw_index;
+ int eye_src;
+ int eye_vrt;
+ int eye_term;
+@@ -900,6 +912,64 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
+ }
+ }
+
++/* type switch for usb3/pcie/sgmii/sata */
++static int phy_type_syscon_get(struct mtk_phy_instance *instance,
++ struct device_node *dn)
++{
++ struct of_phandle_args args;
++ int ret;
++
++ /* type switch function is optional */
++ if (!of_property_read_bool(dn, "mediatek,syscon-type"))
++ return 0;
++
++ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
++ 2, 0, &args);
++ if (ret)
++ return ret;
++
++ instance->type_sw_reg = args.args[0];
++ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
++ instance->type_sw = syscon_node_to_regmap(args.np);
++ of_node_put(args.np);
++ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
++ instance->type_sw_reg, instance->type_sw_index);
++
++ return PTR_ERR_OR_ZERO(instance->type_sw);
++}
++
++static int phy_type_set(struct mtk_phy_instance *instance)
++{
++ int type;
++ u32 mask;
++
++ if (!instance->type_sw)
++ return 0;
++
++ switch (instance->type) {
++ case PHY_TYPE_USB3:
++ type = RG_PHY_SW_USB3;
++ break;
++ case PHY_TYPE_PCIE:
++ type = RG_PHY_SW_PCIE;
++ break;
++ case PHY_TYPE_SGMII:
++ type = RG_PHY_SW_SGMII;
++ break;
++ case PHY_TYPE_SATA:
++ type = RG_PHY_SW_SATA;
++ break;
++ case PHY_TYPE_USB2:
++ default:
++ return 0;
++ }
++
++ mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);
++ regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);
++
++ return 0;
++}
++
+ static int mtk_phy_init(struct phy *phy)
+ {
+ struct mtk_phy_instance *instance = phy_get_drvdata(phy);
+@@ -932,6 +1002,9 @@ static int mtk_phy_init(struct phy *phy)
+ case PHY_TYPE_SATA:
+ sata_phy_instance_init(tphy, instance);
+ break;
++ case PHY_TYPE_SGMII:
++ /* nothing to do, only used to set type */
++ break;
+ default:
+ dev_err(tphy->dev, "incompatible PHY type\n");
+ return -EINVAL;
+@@ -1020,7 +1093,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+ if (!(instance->type == PHY_TYPE_USB2 ||
+ instance->type == PHY_TYPE_USB3 ||
+ instance->type == PHY_TYPE_PCIE ||
+- instance->type == PHY_TYPE_SATA)) {
++ instance->type == PHY_TYPE_SATA ||
++ instance->type == PHY_TYPE_SGMII)) {
+ dev_err(dev, "unsupported device type: %d\n", instance->type);
+ return ERR_PTR(-EINVAL);
+ }
+@@ -1035,6 +1109,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
+ }
+
+ phy_parse_property(tphy, instance);
++ phy_type_set(instance);
+
+ return instance->phy;
+ }
+@@ -1183,6 +1258,10 @@ static int mtk_tphy_probe(struct platform_device *pdev)
+ retval = PTR_ERR(instance->ref_clk);
+ goto put_child;
+ }
++
++ retval = phy_type_syscon_get(instance, child_np);
++ if (retval)
++ goto put_child;
+ }
+
+ provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
+--
+2.34.1
+