[][openwrt][update the patches in accordance with the new naming rules]
[Description]
Change all mtk patches in accordance with the new naming rules
"999-20xx-" : Basic Part
"999-21xx-" : Slow Speed I/O
"999-22xx-" : Slow Speed I/O
"999-23xx-" : SPI & Storage
"999-24xx-" : SPI & Storage
"999-25xx-" : Advanced features
"999-26xx-" : High Speed I/O
"999-27xx-" : Networking
"999-28xx-" : MISC
"999-29xx-" : Uncategorized
[Release-log]
N/A
Change-Id: I245da3b0e5b7299b42473c20cc6f0899cffc1ad2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7530987
diff --git a/target/linux/mediatek/patches-5.4/999-2131-pwm-add-mt7981-support.patch b/target/linux/mediatek/patches-5.4/999-2131-pwm-add-mt7981-support.patch
new file mode 100644
index 0000000..e137dc4
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/999-2131-pwm-add-mt7981-support.patch
@@ -0,0 +1,145 @@
+From c6dc9128df3673041cade417331ad2579e669520 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 2 Jun 2023 13:06:07 +0800
+Subject: [PATCH] [slow-speed-io][999-2131-pwm-add-mt7981-support.patch]
+
+---
+ drivers/pwm/pwm-mediatek.c | 51 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 48 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
+index 35a0db2ff..f4393bd46 100644
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -32,10 +32,13 @@
+ #define PWM45THRES_FIXUP 0x34
+
+ #define PWM_CLK_DIV_MAX 7
++#define REG_V1 1
++#define REG_V2 2
+
+ struct pwm_mediatek_of_data {
+ unsigned int num_pwms;
+ bool pwm45_fixup;
++ int reg_ver;
+ };
+
+ /**
+@@ -56,10 +59,14 @@ struct pwm_mediatek_chip {
+ const struct pwm_mediatek_of_data *soc;
+ };
+
+-static const unsigned int pwm_mediatek_reg_offset[] = {
++static const unsigned int mtk_pwm_reg_offset_v1[] = {
+ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
+ };
+
++static const unsigned int mtk_pwm_reg_offset_v2[] = {
++ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
++};
++
+ static inline struct pwm_mediatek_chip *
+ to_pwm_mediatek_chip(struct pwm_chip *chip)
+ {
+@@ -107,14 +114,38 @@ static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
+ static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
+ unsigned int num, unsigned int offset)
+ {
+- return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
++ u32 pwm_offset;
++
++ switch (chip->soc->reg_ver) {
++ case REG_V2:
++ pwm_offset = mtk_pwm_reg_offset_v2[num];
++ break;
++
++ case REG_V1:
++ default:
++ pwm_offset = mtk_pwm_reg_offset_v1[num];
++ }
++
++ return readl(chip->regs + pwm_offset + offset);
+ }
+
+ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
+ unsigned int num, unsigned int offset,
+ u32 value)
+ {
+- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
++ u32 pwm_offset;
++
++ switch (chip->soc->reg_ver) {
++ case REG_V2:
++ pwm_offset = mtk_pwm_reg_offset_v2[num];
++ break;
++
++ case REG_V1:
++ default:
++ pwm_offset = mtk_pwm_reg_offset_v1[num];
++ }
++
++ writel(value, chip->regs + pwm_offset + offset);
+ }
+
+ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
+@@ -280,36 +311,49 @@ static int pwm_mediatek_remove(struct platform_device *pdev)
+ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
+ .num_pwms = 8,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
+ .num_pwms = 6,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = true,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = true,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
+ .num_pwms = 1,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
++};
++
++static const struct pwm_mediatek_of_data mt7981_pwm_data = {
++ .num_pwms = 3,
++ .pwm45_fixup = false,
++ .reg_ver = REG_V2,
+ };
+
+ static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+ .num_pwms = 2,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct of_device_id pwm_mediatek_of_match[] = {
+@@ -318,6 +362,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
+ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
+ { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
++ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+ { },
+--
+2.34.1
+