commit 555419758a611245fff41f2eb264e9c2217f3236
author developer <developer@mediatek.com> Fri Aug 16 18:01:52 2024 +0800
committer developer <developer@mediatek.com> Tue Aug 20 21:45:43 2024 +0800
tree 8632eee789f57cc45b24c2529fcbde4fa2f9dc90
parent dff3219ffd3240cfd4a88bdfc5f23d65063efcd2

[][High][kernel][mt7981/mt7988][eth][net: phy: mediatek: Introduce mtk-phy-lib and add 2.5Gphy support]

[Description]
Add mtk-phy-lib and add 2.5Gphy support:
This patch series integrate MediaTek's built-in Ethernet PHY helper functions
into mtk-phy-lib and add more functions into it. Also, add support for 2.5Gphy
on MT7988 SoC:

1. Re-organize MediaTek ethernet phy driver files and get ready to integrate
some common functions and add new 2.5G phy driver.
mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy
mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988
mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988
2. Fix spelling errors which comes from mediatek-ge-soc.c and
rearrange variables with reverse Xmas tree order.
3. Create mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's
LED helper functions so that we can use those helper functions in other
MTK's ethernet phy driver. However, we won't use this in kernel-5.4
because this needs newer LED framework.
4. Integrate read/write page helper functions as MTK phy lib.
5. Add MT7530 & MT7531's PHY ID macros in mtk-ge.c so that
it follows the same rule of mtk-ge-soc.c.
6. Shrink mtk-ge-soc.c line wrapping to 80 characters.
7. Adds TR(token ring) manipulations and adds correct
macro names for those magic numbers. TR is a way to access
proprietary registers on page 52b5. Use these helper functions
so we can see which fields we're going to modify/set/clear.
8. We observe that some 10G devices' (mostly Marvell's chips inside) 1G
training time violates specification, which may last 2230ms and affect
later TX/RX link pulse time. This will invalidate MediaTek series
gigabit Ethernet PHYs' hardware auto downshift mechanism.
Without this patch, if someone is trying to use "4-wire" cable to
connect above devices, MediaTek' gigabit Ethernet PHYs may fail
to downshift to 100Mbps. (If partner 10G devices' downshift mechanism
stops at 1G)
This patch extends our 1G TX/RX link pulse time so that we can still
link up with those 10G devices.

Tested device:
- Netgear GS110EMX's 10G port (Marvell 88X3340P)
- QNAP QSW-M408-4C

[Release-log]
N/A

Change-Id: Ife6f87f0248bd42c87dd7e2d6cf753ca1751a7bf
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9510450