[][kernel][common][eth][Refactor PSE port link down function]
[Description]
Refactor PSE port link down function.
[Release-log]
N/A
Change-Id: I49ff9906f8f121f805ed224a865ba6d0fff2f19e
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9364824
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
index de93b25..fb5ed7f 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
@@ -829,13 +829,16 @@
}
}
-void mtk_pse_port_linkdown(struct mtk_eth *eth, int port)
+void mtk_pse_set_port_link(struct mtk_eth *eth, u32 port, bool enable)
{
- u32 fe_glo_cfg;
+ u32 val;
- fe_glo_cfg = mtk_r32(eth, MTK_FE_GLO_CFG(port));
- fe_glo_cfg |= MTK_FE_LINK_DOWN_PORT(port);
- mtk_w32(eth, fe_glo_cfg, MTK_FE_GLO_CFG(port));
+ val = mtk_r32(eth, MTK_FE_GLO_CFG(port));
+ if (enable)
+ val &= ~MTK_FE_LINK_DOWN_P(port);
+ else
+ val |= MTK_FE_LINK_DOWN_P(port);
+ mtk_w32(eth, val, MTK_FE_GLO_CFG(port));
}
void mtk_prepare_reset_fe(struct mtk_eth *eth)
@@ -861,14 +864,14 @@
/* Force mac link down */
mtk_mac_linkdown(eth);
- /* Force pse port link down */
- mtk_pse_port_linkdown(eth, 0);
- mtk_pse_port_linkdown(eth, 1);
- mtk_pse_port_linkdown(eth, 2);
- mtk_pse_port_linkdown(eth, 8);
- mtk_pse_port_linkdown(eth, 9);
+ /* Force PSE port link down */
+ mtk_pse_set_port_link(eth, 0, false);
+ mtk_pse_set_port_link(eth, 1, false);
+ mtk_pse_set_port_link(eth, 2, false);
+ mtk_pse_set_port_link(eth, 8, false);
+ mtk_pse_set_port_link(eth, 9, false);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
- mtk_pse_port_linkdown(eth, 15);
+ mtk_pse_set_port_link(eth, 15, false);
/* Enable GDM drop */
for (i = 0; i < MTK_MAC_COUNT; i++)
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.h
index dd8206a..facb645 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.h
@@ -92,4 +92,5 @@
void mtk_prepare_reset_fe(struct mtk_eth *eth);
void mtk_prepare_reset_ppe(struct mtk_eth *eth, u32 ppe_id);
+void mtk_pse_set_port_link(struct mtk_eth *eth, u32 port, bool enable);
#endif /* MTK_ETH_RESET_H */
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 48aab68..e73eaf5 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -970,10 +970,10 @@
__func__, gdm_fsm, mac_fsm);
}
-static void mtk_pse_port_link_set(struct mtk_mac *mac, bool up,
- phy_interface_t interface)
+static void mtk_pse_set_mac_port_link(struct mtk_mac *mac, bool up,
+ phy_interface_t interface)
{
- u32 fe_glo_cfg, val = 0, port = 0;
+ u32 port = 0;
if (!up && interface == PHY_INTERFACE_MODE_XGMII) {
void __iomem *base;
@@ -995,26 +995,18 @@
switch (mac->id) {
case MTK_GMAC1_ID:
port = PSE_GDM1_PORT;
- val = MTK_FE_LINK_DOWN_PORT(port);
break;
case MTK_GMAC2_ID:
port = PSE_GDM2_PORT;
- val = MTK_FE_LINK_DOWN_PORT(port);
break;
case MTK_GMAC3_ID:
port = PSE_GDM3_PORT;
- val = MTK_FE_LINK_DOWN_PORT(port);
break;
+ default:
+ return;
}
- fe_glo_cfg = mtk_r32(mac->hw, MTK_FE_GLO_CFG(port));
-
- if (!up)
- fe_glo_cfg |= val;
- else
- fe_glo_cfg &= ~val;
-
- mtk_w32(mac->hw, fe_glo_cfg, MTK_FE_GLO_CFG(port));
+ mtk_pse_set_port_link(mac->hw, port, up);
mtk_gdm_fsm_poll(mac);
}
@@ -1027,7 +1019,7 @@
unsigned int id;
u32 mcr, sts;
- mtk_pse_port_link_set(mac, false, interface);
+ mtk_pse_set_mac_port_link(mac, false, interface);
if (mac->type == MTK_GDM_TYPE) {
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
@@ -1209,7 +1201,7 @@
mcr &= ~(XMAC_MCR_TRX_DISABLE);
mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
}
- mtk_pse_port_link_set(mac, true, interface);
+ mtk_pse_set_mac_port_link(mac, true, interface);
}
static void mtk_validate(struct phylink_config *config,
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 198cd0e..305ede6 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -71,8 +71,10 @@
#define MTK_RSS_MAX_INDIRECTION_TABLE 128
/* Frame Engine Global Configuration */
-#define MTK_FE_GLO_CFG(port) ((port < 8) ? 0x0 : 0x24)
-#define MTK_FE_LINK_DOWN_PORT(x) ((x < 8) ? (1 << (8 + x)) : (1 << (x - 8)))
+#define MTK_FE_GLO_CFG(x) ((x < 8) ? 0x0 : 0x24)
+#define MTK_FE_LINK_DOWN_P(x) ((x < 8) ? FIELD_PREP(GENMASK(15, 8), BIT(x)) : \
+ FIELD_PREP(GENMASK(7, 0), BIT(x - 8)))
+
/* Frame Engine Global Reset Register */
#define MTK_RST_GL 0x04
#define RST_GL_PSE BIT(0)
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c
index 29477cb..bee4131 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat.c
@@ -36,9 +36,9 @@
void (*ra_sw_nat_clear_bind_entries)(void) = NULL;
EXPORT_SYMBOL(ra_sw_nat_clear_bind_entries);
-int (*hnat_get_wdma_tx_port)(int wdma_idx) = NULL;
+int (*hnat_get_wdma_tx_port)(u32 wdma_idx) = NULL;
EXPORT_SYMBOL(hnat_get_wdma_tx_port);
-int (*hnat_get_wdma_rx_port)(int wdma_idx) = NULL;
+int (*hnat_get_wdma_rx_port)(u32 wdma_idx) = NULL;
EXPORT_SYMBOL(hnat_get_wdma_rx_port);
int (*ppe_del_entry_by_mac)(unsigned char *mac) = NULL;
@@ -49,7 +49,7 @@
void (*ppe_dev_unregister_hook)(struct net_device *dev) = NULL;
EXPORT_SYMBOL(ppe_dev_unregister_hook);
-int (*hnat_set_wdma_pse_port_state)(int wdma_idx, int up) = NULL;
+int (*hnat_set_wdma_pse_port_state)(u32 wdma_idx, bool up) = NULL;
EXPORT_SYMBOL(hnat_set_wdma_pse_port_state);
static void hnat_sma_build_entry(struct timer_list *t)
@@ -144,7 +144,7 @@
}
}
-static int mtk_get_wdma_tx_port(int wdma_idx)
+static int mtk_get_wdma_tx_port(u32 wdma_idx)
{
if (wdma_idx == 0 || wdma_idx == 1 || wdma_idx == 2)
return NR_PPE0_PORT;
@@ -152,7 +152,7 @@
return -EINVAL;
}
-static int mtk_get_wdma_rx_port(int wdma_idx)
+static int mtk_get_wdma_rx_port(u32 wdma_idx)
{
if (wdma_idx == 2)
return NR_WDMA2_PORT;
@@ -164,7 +164,7 @@
return -EINVAL;
}
-static int mtk_set_wdma_pse_port_state(int wdma_idx, int up)
+static int mtk_set_wdma_pse_port_state(u32 wdma_idx, bool up)
{
int port;
@@ -173,7 +173,7 @@
return -EINVAL;
cr_set_field(hnat_priv->fe_base + MTK_FE_GLO_CFG(port),
- BIT((u32)port - NR_WDMA0_PORT), !up);
+ MTK_FE_LINK_DOWN_P((u32)port), !up);
return 0;
}
diff --git a/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch b/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
index 1511384..d46ef2d 100644
--- a/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
+++ b/21.02/files/target/linux/mediatek/patches-5.4/999-4102-mtk-crypto-offload-support.patch
@@ -317,7 +317,7 @@
+bool (*mtk_crypto_offloadable)(struct sk_buff *skb) = NULL;
+EXPORT_SYMBOL(mtk_crypto_offloadable);
- int (*hnat_set_wdma_pse_port_state)(int wdma_idx, int up) = NULL;
+ int (*hnat_set_wdma_pse_port_state)(u32 wdma_idx, bool up) = NULL;
EXPORT_SYMBOL(hnat_set_wdma_pse_port_state);
--- a/drivers/net/ethernet/mediatek/mtk_hnat/hnat.h
+++ b/drivers/net/ethernet/mediatek/mtk_hnat/hnat.h