[][Add read back value when using cl write command]
[Description]
Add read back value when using cl write command
[Release-log]
N/A
Change-Id: I4738098a8daf611b9d38ab268915b87a679d3d46
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6366532
diff --git a/feed/switch/src/switch_753x.c b/feed/switch/src/switch_753x.c
index 2637ed5..9c7c921 100644
--- a/feed/switch/src/switch_753x.c
+++ b/feed/switch/src/switch_753x.c
@@ -273,9 +273,9 @@
{
unsigned int port_num;
unsigned int dev_num;
- unsigned int value;
+ unsigned int value, cl_value;
unsigned int reg;
- int ret = 0;
+ int ret = 0, cl_ret = 0;
char op;
if (strncmp(argv[2], "cl22", 4) && strncmp(argv[2], "cl45", 4))
@@ -310,11 +310,21 @@
if (argc == 7) {
port_num = strtoul(argv[argc-3], NULL, 0);
ret = mii_mgr_write(port_num, reg, value);
+ cl_ret = mii_mgr_read(port_num, reg, &cl_value);
+ if (cl_ret < 0)
+ printf(" Phy read reg fail\n");
+ else
+ printf(" Phy read reg=0x%x, value=0x%x\n", reg, cl_value);
}
else if (argc == 8) {
dev_num = strtoul(argv[argc-3], NULL, 0);
port_num = strtoul(argv[argc-4], NULL, 0);
ret = mii_mgr_c45_write(port_num, dev_num, reg, value);
+ cl_ret = mii_mgr_c45_read(port_num, dev_num, reg, &cl_value);
+ if (cl_ret < 0)
+ printf(" Phy read reg fail\n");
+ else
+ printf(" Phy read reg=0x%x, value=0x%x\n", reg, cl_value);
}
else
usage(argv[0]);