[][MAC80211][mt76][refactor internal patches]
[Description]
Fix mt7986-mac80211 patch fail.
[Release-log]
N/A
Change-Id: I4c43e8e63ec4fce831590dd6edde33d26c2adc50
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6774656
diff --git a/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch b/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
index b0689cd..113b411 100644
--- a/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
+++ b/autobuild_mac80211_release/package/kernel/mt76/patches/0001-mt76-mt7915-rework-testmode-init-registers.patch
@@ -1,4 +1,4 @@
-From 567a6f7be24a7f87d550f1cf3e1f1796e1770b2a Mon Sep 17 00:00:00 2001
+From 09ef6b695a93055d885869222614a936ed309dc2 Mon Sep 17 00:00:00 2001
From: Shayne Chen <shayne.chen@mediatek.com>
Date: Mon, 6 Jun 2022 19:46:26 +0800
Subject: [PATCH 1/3] mt76: mt7915: rework testmode init registers
@@ -11,10 +11,10 @@
4 files changed, 55 insertions(+), 18 deletions(-)
diff --git a/mt7915/mmio.c b/mt7915/mmio.c
-index be1b8ea7..9c2c5086 100644
+index 3c840853..813d6f40 100644
--- a/mt7915/mmio.c
+++ b/mt7915/mmio.c
-@@ -68,6 +68,7 @@ static const u32 mt7986_reg[] = {
+@@ -113,6 +113,7 @@ static const u32 mt7986_reg[] = {
};
static const u32 mt7915_offs[] = {
@@ -22,7 +22,7 @@
[TMAC_CDTR] = 0x090,
[TMAC_ODTR] = 0x094,
[TMAC_ATCR] = 0x098,
-@@ -142,6 +143,7 @@ static const u32 mt7915_offs[] = {
+@@ -187,6 +188,7 @@ static const u32 mt7915_offs[] = {
};
static const u32 mt7916_offs[] = {
@@ -31,10 +31,10 @@
[TMAC_ODTR] = 0x0cc,
[TMAC_ATCR] = 0x00c,
diff --git a/mt7915/regs.h b/mt7915/regs.h
-index 5180dd93..2e445373 100644
+index 0c61f125..947f02f2 100644
--- a/mt7915/regs.h
+++ b/mt7915/regs.h
-@@ -32,6 +32,7 @@ enum reg_rev {
+@@ -47,6 +47,7 @@ enum reg_rev {
};
enum offs_rev {
@@ -42,7 +42,7 @@
TMAC_CDTR,
TMAC_ODTR,
TMAC_ATCR,
-@@ -182,6 +183,12 @@ enum offs_rev {
+@@ -197,6 +198,12 @@ enum offs_rev {
#define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
#define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
@@ -55,7 +55,7 @@
/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
-@@ -190,6 +197,9 @@ enum offs_rev {
+@@ -205,6 +212,9 @@ enum offs_rev {
#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
@@ -65,7 +65,7 @@
#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
-@@ -461,8 +471,10 @@ enum offs_rev {
+@@ -484,8 +494,10 @@ enum offs_rev {
#define MT_AGG_PCR0_VHT_PROT BIT(13)
#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
@@ -190,5 +190,5 @@
mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE],
&td->tx_duty_cycle, 0, 99) ||
--
-2.25.1
+2.18.0