diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
index 083a723..9b40b37 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
@@ -29,13 +29,13 @@
 			<&infracfg CK_INFRA_ISPI0>,
 			<&infracfg CK_INFRA_I2C>,
 			<&infracfg CK_INFRA_ISPI1>,
-			<&infracfg CK_INFRA_PWM>,
+			<&clk40m>,
 			<&infracfg CK_INFRA_66M_MCK>,
 			<&infracfg CK_INFRA_CK_F32K>,
 			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
-			<&infracfg CK_INFRA_PWM_BCK>,
-			<&infracfg CK_INFRA_PWM_CK1>,
-			<&infracfg CK_INFRA_PWM_CK2>,
+			<&clk40m>,
 			<&infracfg CK_INFRA_133M_HCK>,
 			<&infracfg CK_INFRA_66M_PHCK>,
 			<&infracfg CK_INFRA_FAUD_L_CK	>,
@@ -64,15 +64,15 @@
 			<&infracfg_ao CK_INFRA_UART2_SEL>,
 			<&infracfg_ao CK_INFRA_SPI0_SEL>,
 			<&infracfg_ao CK_INFRA_SPI1_SEL>,
-			<&infracfg_ao CK_INFRA_PWM1_SEL>,
-			<&infracfg_ao CK_INFRA_PWM2_SEL>,
-			<&infracfg_ao CK_INFRA_PWM_BSEL>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
 			<&clk40m>,
 			<&infracfg_ao CK_INFRA_GPT_STA>,
-			<&infracfg_ao CK_INFRA_PWM_HCK>,
-			<&infracfg_ao CK_INFRA_PWM_STA>,
-			<&infracfg_ao CK_INFRA_PWM1_CK>,
-			<&infracfg_ao CK_INFRA_PWM2_CK>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
 			<&infracfg_ao CK_INFRA_CQ_DMA_CK>,
 			<&clk40m>,
 			<&clk40m>,
@@ -165,7 +165,7 @@
 			<&clk40m>,
 			<&clk40m>,
 			<&topckgen CK_TOP_UART_SEL>,
-			<&topckgen CK_TOP_PWM_SEL>,
+			<&clk40m>,
 			<&topckgen CK_TOP_I2C_SEL>,
 			<&clk40m>,
 			<&topckgen CK_TOP_EMMC_208M_SEL	>,
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index 1c1fccd..f5bd0ca 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -40,6 +40,18 @@
 		};
 	};
 
+	pwm: pwm@10048000 {
+		compatible = "mediatek,mt7981-pwm";
+		reg = <0 0x10048000 0 0x1000>;
+		#pwm-cells = <2>;
+		clocks = <&infracfg_ao CK_INFRA_PWM_STA>,
+			 <&infracfg_ao CK_INFRA_PWM_HCK>,
+			 <&infracfg_ao CK_INFRA_PWM1_CK>,
+			 <&infracfg_ao CK_INFRA_PWM2_CK>,
+			 <&infracfg_ao CK_INFRA_PWM3_CK>;
+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+	};
+
 	auxadc: adc@1100d000 {
 		compatible = "mediatek,mt7981-auxadc",
 			     "mediatek,mt7622-auxadc";