[][pwm add mt7981 support]
[Description]
Add PWM dts node, remove PWM clock from clkitg, modify PWM drivers for REG-V2.
[Release-log]
N/A
Change-Id: If007b311f77d9a2fa4be26199b63ff384d0218c0
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5381846
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
index 083a723..9b40b37 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clkitg.dtsi
@@ -29,13 +29,13 @@
<&infracfg CK_INFRA_ISPI0>,
<&infracfg CK_INFRA_I2C>,
<&infracfg CK_INFRA_ISPI1>,
- <&infracfg CK_INFRA_PWM>,
+ <&clk40m>,
<&infracfg CK_INFRA_66M_MCK>,
<&infracfg CK_INFRA_CK_F32K>,
<&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
- <&infracfg CK_INFRA_PWM_BCK>,
- <&infracfg CK_INFRA_PWM_CK1>,
- <&infracfg CK_INFRA_PWM_CK2>,
+ <&clk40m>,
<&infracfg CK_INFRA_133M_HCK>,
<&infracfg CK_INFRA_66M_PHCK>,
<&infracfg CK_INFRA_FAUD_L_CK >,
@@ -64,15 +64,15 @@
<&infracfg_ao CK_INFRA_UART2_SEL>,
<&infracfg_ao CK_INFRA_SPI0_SEL>,
<&infracfg_ao CK_INFRA_SPI1_SEL>,
- <&infracfg_ao CK_INFRA_PWM1_SEL>,
- <&infracfg_ao CK_INFRA_PWM2_SEL>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
<&clk40m>,
<&infracfg_ao CK_INFRA_GPT_STA>,
- <&infracfg_ao CK_INFRA_PWM_HCK>,
- <&infracfg_ao CK_INFRA_PWM_STA>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
<&infracfg_ao CK_INFRA_CQ_DMA_CK>,
<&clk40m>,
<&clk40m>,
@@ -165,7 +165,7 @@
<&clk40m>,
<&clk40m>,
<&topckgen CK_TOP_UART_SEL>,
- <&topckgen CK_TOP_PWM_SEL>,
+ <&clk40m>,
<&topckgen CK_TOP_I2C_SEL>,
<&clk40m>,
<&topckgen CK_TOP_EMMC_208M_SEL >,
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index 1c1fccd..f5bd0ca 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -40,6 +40,18 @@
};
};
+ pwm: pwm@10048000 {
+ compatible = "mediatek,mt7981-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&infracfg_ao CK_INFRA_PWM_STA>,
+ <&infracfg_ao CK_INFRA_PWM_HCK>,
+ <&infracfg_ao CK_INFRA_PWM1_CK>,
+ <&infracfg_ao CK_INFRA_PWM2_CK>,
+ <&infracfg_ao CK_INFRA_PWM3_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
auxadc: adc@1100d000 {
compatible = "mediatek,mt7981-auxadc",
"mediatek,mt7622-auxadc";
diff --git a/target/linux/mediatek/patches-5.4/0931-pwm-add-mt7981-support.patch b/target/linux/mediatek/patches-5.4/0931-pwm-add-mt7981-support.patch
new file mode 100644
index 0000000..d8b8434
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0931-pwm-add-mt7981-support.patch
@@ -0,0 +1,141 @@
+diff --git a/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c b/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c
+index 7c56ee2..3a5a456 100644
+--- a/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c
++++ b/build_dir/target-aarch64_cortex-a53_musl/linux-mediatek_mt7981/linux-5.4.163/drivers/pwm/pwm-mediatek.c
+@@ -20,7 +20,6 @@
+ #include <linux/slab.h>
+ #include <linux/types.h>
+
+-
+ /* PWM registers and bits definitions */
+ #define PWMCON 0x00
+ #define PWMHDUR 0x04
+@@ -33,10 +32,13 @@
+ #define PWM45THRES_FIXUP 0x34
+
+ #define PWM_CLK_DIV_MAX 7
++#define REG_V1 1
++#define REG_V2 2
+
+ struct pwm_mediatek_of_data {
+ unsigned int num_pwms;
+ bool pwm45_fixup;
++ int reg_ver;
+ };
+
+ /**
+@@ -57,10 +59,14 @@ struct pwm_mediatek_chip {
+ const struct pwm_mediatek_of_data *soc;
+ };
+
+-static const unsigned int pwm_mediatek_reg_offset[] = {
++static const unsigned int mtk_pwm_reg_offset_v1[] = {
+ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
+ };
+
++static const unsigned int mtk_pwm_reg_offset_v2[] = {
++ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240
++};
++
+ static inline struct pwm_mediatek_chip *
+ to_pwm_mediatek_chip(struct pwm_chip *chip)
+ {
+@@ -108,14 +114,38 @@ static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
+ static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
+ unsigned int num, unsigned int offset)
+ {
+- return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
++ u32 pwm_offset;
++
++ switch (chip->soc->reg_ver) {
++ case REG_V2:
++ pwm_offset = mtk_pwm_reg_offset_v2[num];
++ break;
++
++ case REG_V1:
++ default:
++ pwm_offset = mtk_pwm_reg_offset_v1[num];
++ }
++
++ return readl(chip->regs + pwm_offset + offset);
+ }
+
+ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
+ unsigned int num, unsigned int offset,
+ u32 value)
+ {
+- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
++ u32 pwm_offset;
++
++ switch (chip->soc->reg_ver) {
++ case REG_V2:
++ pwm_offset = mtk_pwm_reg_offset_v2[num];
++ break;
++
++ case REG_V1:
++ default:
++ pwm_offset = mtk_pwm_reg_offset_v1[num];
++ }
++
++ writel(value, chip->regs + pwm_offset + offset);
+ }
+
+ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
+@@ -281,36 +311,49 @@ static int pwm_mediatek_remove(struct platform_device *pdev)
+ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
+ .num_pwms = 8,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
+ .num_pwms = 6,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = true,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = true,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
+ .num_pwms = 1,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
++};
++
++static const struct pwm_mediatek_of_data mt7981_pwm_data = {
++ .num_pwms = 3,
++ .pwm45_fixup = false,
++ .reg_ver = REG_V2,
+ };
+
+ static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+ .num_pwms = 2,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V2,
+ };
+
+ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = false,
++ .reg_ver = REG_V1,
+ };
+
+ static const struct of_device_id pwm_mediatek_of_match[] = {
+@@ -319,6 +362,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
+ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
+ { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
++ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+ { },