[][openwrt][mt7988][integration][Add basic Filogic 880 SoC support]
[Description]
Add basic filogic 880 SoC support to openwrt 21.02
[Release-log]
Change-Id: I57791df2e9f9f4729cb2d32f734090de52c370f2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6592143
Build: srv_hbgsm110
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/Makefile b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/Makefile
old mode 100755
new mode 100644
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7530.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7530.c
old mode 100755
new mode 100644
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
index 7253042..854a586 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
@@ -7,6 +7,10 @@
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/hrtimer.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
#include "mt753x.h"
#include "mt753x_regs.h"
@@ -682,6 +686,24 @@
return -ENODEV;
}
+static int mt7988_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)
+{
+ const char *model;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "mediatek,mt7988-switch");
+ if (!np)
+ return -ENODEV;
+
+ of_node_put(np);
+
+ crev->rev = 0;
+ crev->name = "MT7988";
+ gsw->direct_access = true;
+
+ return 0;
+}
+
static void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode)
{
u32 val;
@@ -810,7 +832,8 @@
u32 val;
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- mt7531_phy_100m_eye_diag_setting(gsw, i);
+ if (!gsw->direct_access)
+ mt7531_phy_100m_eye_diag_setting(gsw, i);
/* Enable HW auto downshift */
gsw->mii_write(gsw, i, 0x1f, 0x1);
@@ -834,10 +857,14 @@
val |= PHY_LINKDOWN_POWER_SAVING_EN;
gsw->mii_write(gsw, i, PHY_EXT_REG_17, val);
- val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6);
- val &= ~PHY_POWER_SAVING_M;
- val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
- gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, val);
+ if (!gsw->direct_access) {
+ val = gsw->mmd_read(gsw, i, PHY_DEV1E,
+ PHY_DEV1E_REG_0C6);
+ val &= ~PHY_POWER_SAVING_M;
+ val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
+ gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6,
+ val);
+ }
/* Timing Recovery for GbE slave mode */
mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_01, 0x6fb90a);
@@ -952,7 +979,8 @@
gsw->mmd_read = mt753x_mmd_read;
gsw->mmd_write = mt753x_mmd_write;
- gsw->hw_phy_cal = of_property_read_bool(gsw->dev->of_node, "mediatek,hw_phy_cal");
+ gsw->hw_phy_cal = of_property_read_bool(gsw->dev->of_node,
+ "mediatek,hw_phy_cal");
for (i = 0; i < MT753X_NUM_PHYS; i++) {
val = gsw->mii_read(gsw, i, MII_BMCR);
@@ -966,7 +994,7 @@
/* Switch soft reset */
mt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST);
- usleep_range(10, 20);
+ udelay(20);
/* Enable MDC input Schmitt Trigger */
val = mt753x_reg_read(gsw, SMT0_IOLB);
@@ -976,6 +1004,7 @@
mt7531_set_gpio_pinmux(gsw);
mt7531_core_pll_setup(gsw);
+
mt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg);
mt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg);
@@ -999,6 +1028,89 @@
return 0;
}
+static int mt7988_sw_init(struct gsw_mt753x *gsw)
+{
+ struct device_node *switch_node = NULL;
+ struct platform_device *pdev;
+ int i;
+ u32 val;
+ u32 pmcr;
+ u32 speed;
+
+ switch_node = of_find_node_by_name(NULL, "switch0");
+ if (switch_node == NULL) {
+ dev_err(&pdev->dev, "switch node invaild\n");
+ return -ENOENT;
+ }
+
+ gsw->base = of_iomap(switch_node, 0);
+ if (IS_ERR(gsw->base)) {
+ dev_err(&pdev->dev, "switch ioremap failed\n");
+ return -EIO;
+ }
+
+ pdev = container_of(gsw->dev, struct platform_device, dev);
+ gsw->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,sysctrl");
+ if (IS_ERR(gsw->sysctrl_base)) {
+ dev_err(&pdev->dev, "no sysctl regmap found\n");
+ return -ENODEV;
+ }
+
+ /* reset control */
+ regmap_write(gsw->sysctrl_base, ETH_RESET, 0x200);
+ udelay(20);
+ regmap_write(gsw->sysctrl_base, ETH_RESET, 0);
+ udelay(20);
+
+ gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK;
+
+ gsw->mii_read = mt753x_mii_read;
+ gsw->mii_write = mt753x_mii_write;
+ gsw->mmd_read = mt753x_mmd_read;
+ gsw->mmd_write = mt753x_mmd_write;
+
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ val = gsw->mii_read(gsw, i, MII_BMCR);
+ val |= BMCR_ISOLATE;
+ gsw->mii_write(gsw, i, MII_BMCR, val);
+ }
+
+ speed = MAC_SPD_1000;
+ pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
+ MAC_MODE | MAC_TX_EN | MAC_RX_EN | BKOFF_EN |
+ BACKPR_EN | FORCE_MODE_LNK | FORCE_LINK | FORCE_MODE_SPD |
+ FORCE_MODE_DPX | FORCE_MODE_RX_FC | FORCE_MODE_TX_FC |
+ FORCE_RX_FC | FORCE_TX_FC | (speed << FORCE_SPD_S) | FORCE_DPX;
+
+ mt753x_reg_write(gsw, PMCR(6), pmcr);
+
+ /* Global mac control settings */
+ mt753x_reg_write(gsw, GMACCR,
+ (15 << MTCC_LMT_S) | (15 << MAX_RX_JUMBO_S) |
+ RX_PKT_LEN_MAX_JUMBO);
+
+ /* Enable Collision Poll */
+ val = mt753x_reg_read(gsw, CPGC_CTRL);
+ val |= COL_CLK_EN;
+ mt753x_reg_write(gsw, CPGC_CTRL, val);
+ val |= COL_RST_N;
+ mt753x_reg_write(gsw, CPGC_CTRL, val);
+ val |= COL_EN;
+ mt753x_reg_write(gsw, CPGC_CTRL, val);
+
+ /* Disable AFIFO reset for extra short IPG */
+ mt7531_afifo_reset(gsw, 0);
+
+ /* PHY force slave 1G*/
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ gsw->mii_write(gsw, i, MII_CTRL1000, 0x1200);
+ gsw->mii_write(gsw, i, MII_BMCR, 0x140);
+ }
+
+ return 0;
+}
+
static int mt7531_sw_post_init(struct gsw_mt753x *gsw)
{
int i;
@@ -1016,7 +1128,8 @@
val |= POWER_ON_OFF;
gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
- mt7531_phy_pll_setup(gsw);
+ if (!gsw->direct_access)
+ mt7531_phy_pll_setup(gsw);
/* Enable Internal PHYs before phy setting */
val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
@@ -1041,7 +1154,14 @@
for (i = 0; i < MT753X_NUM_PHYS; i++)
gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x0);
- mt7531_internal_phy_calibration(gsw);
+ if (!gsw->direct_access)
+ mt7531_internal_phy_calibration(gsw);
+
+ /* PHY force slave disable, restart AN*/
+ for (i = 0; i < MT753X_NUM_PHYS; i++) {
+ gsw->mii_write(gsw, i, MII_CTRL1000, 0x200);
+ gsw->mii_write(gsw, i, MII_BMCR, 0x1240);
+ }
return 0;
}
@@ -1053,6 +1173,13 @@
.post_init = mt7531_sw_post_init
};
+struct mt753x_sw_id mt7988_id = {
+ .model = MT7988,
+ .detect = mt7988_sw_detect,
+ .init = mt7988_sw_init,
+ .post_init = mt7531_sw_post_init
+};
+
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Zhanguo Ju <zhanguo.ju@mediatek.com>");
MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch");
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.h b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.h
new file mode 100644
index 0000000..2167722
--- /dev/null
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ */
+#ifndef _MT7531_H_
+#define _MT7531_H_
+#include "mt753x.h"
+extern struct mt753x_sw_id mt7531_id;
+extern struct mt753x_sw_id mt7988_id;
+#endif /* _MT7531_H_ */
+
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x.h b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x.h
old mode 100755
new mode 100644
index 732bda1..344d2b0
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x.h
@@ -13,6 +13,7 @@
#include <linux/of_mdio.h>
#include <linux/workqueue.h>
#include <linux/gpio/consumer.h>
+#include <linux/phy.h>
#ifdef CONFIG_SWCONFIG
#include <linux/switch.h>
@@ -30,12 +31,13 @@
enum mt753x_model {
MT7530 = 0x7530,
- MT7531 = 0x7531
+ MT7531 = 0x7531,
+ MT7988 = 0x7988,
};
struct mt753x_port_cfg {
struct device_node *np;
- int phy_mode;
+ phy_interface_t phy_mode;
u32 enabled: 1;
u32 force_link: 1;
u32 speed: 2;
@@ -60,6 +62,10 @@
u32 smi_addr;
u32 phy_base;
int direct_phy_access;
+ bool direct_access;
+
+ void __iomem *base;
+ struct regmap *sysctrl_base;
enum mt753x_model model;
const char *name;
@@ -70,7 +76,7 @@
bool hw_phy_cal;
bool phy_status_poll;
struct mt753x_phy phys[MT753X_NUM_PHYS];
-// int phy_irqs[PHY_MAX_ADDR]; //FIXME
+// int phy_irqs[PHY_MAX_ADDR]; //FIXME
int phy_link_sts;
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_mdio.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
old mode 100755
new mode 100644
index 3639df1..c57a5a2
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
@@ -33,19 +33,24 @@
static struct mt753x_sw_id *mt753x_sw_ids[] = {
&mt7530_id,
&mt7531_id,
+ &mt7988_id,
};
u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg)
{
u32 high, low;
- mutex_lock(&gsw->host_bus->mdio_lock);
+ if (gsw->direct_access)
+ return __raw_readl(gsw->base + reg);
+ mutex_lock(&gsw->host_bus->mdio_lock);
gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
- (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
+ (reg & MT753X_REG_PAGE_ADDR_M) >>
+ MT753X_REG_PAGE_ADDR_S);
low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr,
- (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S);
+ (reg & MT753X_REG_ADDR_M) >>
+ MT753X_REG_ADDR_S);
high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10);
@@ -56,17 +61,24 @@
void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
{
- mutex_lock(&gsw->host_bus->mdio_lock);
-
- gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
- (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);
+ if (gsw->direct_access) {
+ __raw_writel(val, gsw->base + reg);
+ } else {
+ mutex_lock(&gsw->host_bus->mdio_lock);
+ gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,
+ (reg & MT753X_REG_PAGE_ADDR_M) >>
+ MT753X_REG_PAGE_ADDR_S);
- gsw->host_bus->write(gsw->host_bus, gsw->smi_addr,
- (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff);
+ gsw->host_bus->write(gsw->host_bus, gsw->smi_addr,
+ (reg & MT753X_REG_ADDR_M) >>
+ MT753X_REG_ADDR_S,
+ val & 0xffff);
- gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16);
+ gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10,
+ val >> 16);
- mutex_unlock(&gsw->host_bus->mdio_lock);
+ mutex_unlock(&gsw->host_bus->mdio_lock);
+ }
}
/* Indirect MDIO clause 22/45 access */
@@ -89,8 +101,7 @@
return -ETIMEDOUT;
}
- val = (st << MDIO_ST_S) |
- ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
+ val = (st << MDIO_ST_S) | ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
@@ -182,19 +193,19 @@
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_ADDR << MMD_CMD_S) |
- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
- mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
- MDIO_CMD_WRITE, MDIO_ST_C22);
+ mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, MDIO_CMD_WRITE,
+ MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_DATA << MMD_CMD_S) |
- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
- val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0,
- MDIO_CMD_READ, MDIO_ST_C22);
+ val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0, MDIO_CMD_READ,
+ MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
@@ -211,19 +222,19 @@
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_ADDR << MMD_CMD_S) |
- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
- mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,
- MDIO_CMD_WRITE, MDIO_ST_C22);
+ mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, MDIO_CMD_WRITE,
+ MDIO_ST_C22);
mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,
(MMD_DATA << MMD_CMD_S) |
- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),
MDIO_CMD_WRITE, MDIO_ST_C22);
- mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val,
- MDIO_CMD_WRITE, MDIO_ST_C22);
+ mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val, MDIO_CMD_WRITE,
+ MDIO_ST_C22);
mutex_unlock(&gsw->mii_lock);
}
@@ -239,6 +250,7 @@
struct device_node *fixed_link_node;
struct mt753x_port_cfg *port_cfg;
u32 port;
+ int ret;
for_each_child_of_node(gsw->dev->of_node, port_np) {
if (!of_device_is_compatible(port_np, "mediatek,mt753x-port"))
@@ -269,8 +281,8 @@
port_cfg->np = port_np;
- port_cfg->phy_mode = of_get_phy_mode(port_np);
- if (port_cfg->phy_mode < 0) {
+ ret = of_get_phy_mode(port_cfg->np);
+ if (ret < 0) {
dev_info(gsw->dev, "incorrect phy-mode %d\n", port);
continue;
}
@@ -303,6 +315,7 @@
case 2500:
port_cfg->speed = MAC_SPD_2500;
break;
+
default:
dev_info(gsw->dev, "incorrect speed %d\n",
speed);
@@ -310,10 +323,10 @@
}
}
- port_cfg->ssc_on = of_property_read_bool(port_cfg->np,
- "mediatek,ssc-on");
- port_cfg->stag_on = of_property_read_bool(port_cfg->np,
- "mediatek,stag-on");
+ port_cfg->ssc_on =
+ of_property_read_bool(port_cfg->np, "mediatek,ssc-on");
+ port_cfg->stag_on =
+ of_property_read_bool(port_cfg->np, "mediatek,stag-on");
port_cfg->enabled = 1;
}
}
@@ -438,7 +451,6 @@
mutex_unlock(&mt753x_devs_lock);
}
-
struct gsw_mt753x *mt753x_get_gsw(u32 id)
{
struct gsw_mt753x *dev;
@@ -505,8 +517,8 @@
gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0);
if (gsw->reset_pin < 0) {
- dev_err(gsw->dev, "Missing reset pin of switch\n");
- return ret;
+ dev_info(gsw->dev, "No reset pin of switch\n");
+ return 0;
}
ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset");
@@ -523,7 +535,7 @@
return 0;
}
-#if 1 //XDXDXDXD
+
static int mt753x_mdio_read(struct mii_bus *bus, int addr, int reg)
{
struct gsw_mt753x *gsw = bus->priv;
@@ -540,8 +552,7 @@
return 0;
}
-static const struct net_device_ops mt753x_dummy_netdev_ops = {
-};
+static const struct net_device_ops mt753x_dummy_netdev_ops = {};
static void mt753x_phy_link_handler(struct net_device *dev)
{
@@ -552,8 +563,8 @@
if (phydev->link) {
dev_info(gsw->dev,
- "Port %d Link is Up - %s/%s - flow control %s\n",
- port, phy_speed_to_str(phydev->speed),
+ "Port %d Link is Up - %s/%s - flow control %s\n", port,
+ phy_speed_to_str(phydev->speed),
(phydev->duplex == DUPLEX_FULL) ? "Full" : "Half",
phydev->pause ? "rx/tx" : "off");
} else {
@@ -566,7 +577,8 @@
{
struct device_node *phy_np;
struct mt753x_phy *phy;
- int phy_mode;
+ phy_interface_t iface;
+ int ret;
u32 phyad;
if (!mii_np)
@@ -579,10 +591,10 @@
if (phyad >= MT753X_NUM_PHYS)
continue;
- phy_mode = of_get_phy_mode(phy_np);
- if (phy_mode < 0) {
+ ret = of_get_phy_mode(phy_np);
+ if (ret < 0) {
dev_info(gsw->dev, "incorrect phy-mode %d for PHY %d\n",
- phy_mode, phyad);
+ iface, phyad);
continue;
}
@@ -593,7 +605,7 @@
phy->netdev.netdev_ops = &mt753x_dummy_netdev_ops;
phy->phydev = of_phy_connect(&phy->netdev, phy_np,
- mt753x_phy_link_handler, 0, phy_mode);
+ mt753x_phy_link_handler, 0, iface);
if (!phy->phydev) {
dev_info(gsw->dev, "could not connect to PHY %d\n",
phyad);
@@ -640,7 +652,7 @@
gsw->gphy_bus->priv = gsw;
gsw->gphy_bus->parent = gsw->dev;
gsw->gphy_bus->phy_mask = BIT(MT753X_NUM_PHYS) - 1;
-// gsw->gphy_bus->irq = gsw->phy_irqs;
+ // gsw->gphy_bus->irq = gsw->phy_irqs;
for (i = 0; i < PHY_MAX_ADDR; i++)
gsw->gphy_bus->irq[i] = PHY_POLL;
@@ -655,7 +667,6 @@
ret = of_mdiobus_register(gsw->gphy_bus, mii_np);
if (ret) {
- devm_mdiobus_free(gsw->dev, gsw->gphy_bus);
gsw->gphy_bus = NULL;
} else {
if (gsw->phy_status_poll)
@@ -668,7 +679,6 @@
return ret;
}
-#endif
static irqreturn_t mt753x_irq_handler(int irq, void *dev)
{
@@ -710,8 +720,10 @@
mutex_init(&gsw->mii_lock);
/* Switch hard reset */
- if (mt753x_hw_reset(gsw))
+ if (mt753x_hw_reset(gsw)) {
+ dev_info(&pdev->dev, "reset switch fail.\n");
goto fail;
+ }
/* Fetch the SMI address dirst */
if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr))
@@ -768,8 +780,8 @@
platform_set_drvdata(pdev, gsw);
- gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node,
- "mediatek,phy-poll");
+ gsw->phy_status_poll =
+ of_property_read_bool(gsw->dev->of_node, "mediatek,phy-poll");
mt753x_add_gsw(gsw);
#if 1 //XDXD
@@ -825,7 +837,7 @@
static const struct of_device_id mt753x_ids[] = {
{ .compatible = "mediatek,mt753x" },
- { },
+ {},
};
MODULE_DEVICE_TABLE(of, mt753x_ids);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.c
old mode 100755
new mode 100644
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.h b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.h
old mode 100755
new mode 100644
index 7a2a992..e36b6f3
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_nl.h
@@ -38,7 +38,6 @@
#ifdef __KERNEL__
int mt753x_nl_init(void);
void mt753x_nl_exit(void);
-
#endif /* __KERNEL__ */
#endif /* _MT753X_NL_H_ */
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_regs.h b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_regs.h
old mode 100755
new mode 100644
index 1784873..733da63
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_regs.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_regs.h
@@ -9,6 +9,9 @@
#include <linux/bitops.h>
+/* ethernet wrap register */
+#define ETH_RESET 0x8
+
/* Values of Egress TAG Control */
#define ETAG_CTRL_UNTAG 0
#define ETAG_CTRL_TAG 2
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c
old mode 100755
new mode 100644