blob: a592af938b91647be4c22a65e82ed1e913a591b0 [file] [log] [blame]
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt7986a-rfb";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x0>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
device_type = "cpu";
enable-method = "psci";
compatible = "arm,cortex-a53";
reg = <0x3>;
#cooling-cells = <2>;
};
};
wed: wed@15010000 {
compatible = "mediatek,wed";
wed_num = <2>;
/* add this property for wed get the pci slot number. */
pci_slot_map = <0>, <1>;
reg = <0 0x15010000 0 0x1000>,
<0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
};
wed2: wed2@15011000 {
compatible = "mediatek,wed2";
wed_num = <2>;
reg = <0 0x15010000 0 0x1000>,
<0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
};
wdma: wdma@15104800 {
compatible = "mediatek,wed-wdma";
reg = <0 0x15104800 0 0x400>,
<0 0x15104c00 0 0x400>;
};
ap2woccif: ap2woccif@151A5000 {
compatible = "mediatek,ap2woccif";
reg = <0 0x151A5000 0 0x1000>,
<0 0x151AD000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
wocpu0_ilm: wocpu0_ilm@151E0000 {
compatible = "mediatek,wocpu0_ilm";
reg = <0 0x151E0000 0 0x8000>;
};
wocpu1_ilm: wocpu1_ilm@151F0000 {
compatible = "mediatek,wocpu1_ilm";
reg = <0 0x151F0000 0 0x8000>;
};
wocpu_dlm: wocpu_dlm@151E8000 {
compatible = "mediatek,wocpu_dlm";
reg = <0 0x151E8000 0 0x2000>,
<0 0x151F8000 0 0x2000>;
resets = <&ethsysrst 0>;
reset-names = "wocpu_rst";
};
cpu_boot: wocpu_boot@15194000 {
compatible = "mediatek,wocpu_boot";
reg = <0 0x15194000 0 0x1000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
wmcpu_emi: wmcpu-reserved@4FC00000 {
compatible = "mediatek,wmcpu-reserved";
no-map;
reg = <0 0x4FC00000 0 0x00100000>;
};
wocpu0_emi: wocpu0_emi@4FD00000 {
compatible = "mediatek,wocpu0_emi";
no-map;
reg = <0 0x4FD00000 0 0x40000>;
shared = <0>;
};
wocpu1_emi: wocpu1_emi@4FD80000 {
compatible = "mediatek,wocpu1_emi";
no-map;
reg = <0 0x4FD40000 0 0x40000>;
shared = <0>;
};
wocpu_data: wocpu_data@4FE00000 {
compatible = "mediatek,wocpu_data";
no-map;
reg = <0 0x4FD80000 0 0x200000>;
shared = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clk40m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "clkxtal";
};
system_clk: dummy_system_clk {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
clock-frequency = <13000000>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,mt7986-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x68>;
#clock-cells = <1>;
};
infracfg: infracfg@10001040 {
compatible = "mediatek,mt7986-infracfg", "syscon";
reg = <0 0x1000106c 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@1001B000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys: apmixedsys@1001E000 {
compatible = "mediatek,mt7986-apmixedsys", "syscon";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7622-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c080000 0 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pwm: pwm@10048000 {
compatible = "mediatek,mt7986-pwm";
reg = <0 0x10048000 0 0x1000>;
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CK_INFRA_PWM>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
<&infracfg_ao CK_INFRA_PWM1_CK>,
<&infracfg_ao CK_INFRA_PWM2_CK>;
assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
<&infracfg_ao CK_INFRA_PWM1_SEL>,
<&infracfg_ao CK_INFRA_PWM2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
<&infracfg CK_INFRA_PWM>,
<&infracfg CK_INFRA_PWM>,
<&infracfg CK_INFRA_PWM>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
};
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&infracfg CK_INFRA_UART>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>;
assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>;
assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
status = "disabled";
};
i2c0: i2c@11008000 {
compatible = "mediatek,mt7986-i2c";
reg = <0 0x11008000 0 0x90>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <16>;
clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
<&infracfg_ao CK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_passive: cpu-passive {
temperature = <47000>;
hysteresis = <2000>;
type = "passive";
};
cpu_active: cpu-active {
temperature = <67000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu-hot {
temperature = <87000>;
hysteresis = <2000>;
type = "hot";
};
cpu-crit {
temperature = <107000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_active>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_hot>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
thermal: thermal@1100c800 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x1000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_THERM_CK>,
<&infracfg_ao CK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
};
pcie0: pcie@11280000 {
compatible = "mediatek,mt7986-pcie";
reg = <0 0x11280000 0 0x5000>;
reg-names = "pcie-mac";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000
0x0 0x20000000 0 0x10000000>;
status = "disabled";
clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>,
<&infracfg_ao CK_INFRA_IPCIE_CK>,
<&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>,
<&infracfg_ao CK_INFRA_IPCIER_CK>,
<&infracfg_ao CK_INFRA_IPCIEB_CK>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
crypto: crypto@10320000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&infracfg_ao CK_INFRA_EIP97_CK>;
clock-names = "infra_eip97_ck";
assigned-clocks = <&topckgen CK_TOP_EIP_B_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>;
};
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7986-pinctrl";
reg = <0 0x1001f000 0 0x1000>,
<0 0x11c30000 0 0x1000>,
<0 0x11c40000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e30000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
"iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
"iocfg_tl_base", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 100>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7986-ethsys_ck",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
ethsysrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
};
};
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth";
reg = <0 0x15100000 0 0x80000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ethsys CK_ETH_FE_EN>,
<&ethsys CK_ETH_GP2_EN>,
<&ethsys CK_ETH_GP1_EN>,
<&ethsys CK_ETH_WOCPU1_EN>,
<&ethsys CK_ETH_WOCPU0_EN>,
<&sgmiisys0 CK_SGM0_TX_EN>,
<&sgmiisys0 CK_SGM0_RX_EN>,
<&sgmiisys0 CK_SGM0_CK0_EN>,
<&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
<&sgmiisys1 CK_SGM1_TX_EN>,
<&sgmiisys1 CK_SGM1_RX_EN>,
<&sgmiisys1 CK_SGM1_CK1_EN>,
<&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb";
assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
<&topckgen CK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
<&topckgen CK_TOP_CB_SGM_325M>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hnat: hnat@15000000 {
compatible = "mediatek,mtk-hnat_v4";
reg = <0 0x15100000 0 0x80000>;
resets = <&ethsys 0>;
reset-names = "mtketh";
status = "disabled";
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys",
"mediatek,mt7986-sgmiisys_0",
"syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7986-sgmiisys",
"mediatek,mt7986-sgmiisys_1",
"syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
snand: snfi@11005000 {
compatible = "mediatek,mt7986-snand";
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
<&infracfg_ao CK_INFRA_NFI1_CK>,
<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_MM_D8_D2>,
<&topckgen CK_TOP_CB_MM_D8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wbsys: wbsys@18000000 {
compatible = "mediatek,wbsys";
reg = <0 0x18000000 0 0x1000000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
chip_id = <0x7986>;
};
wed_pcie: wed_pcie@10003000 {
compatible = "mediatek,wed_pcie";
reg = <0 0x10003000 0 0x10>;
};
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi-quad";
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_CB_M_D2>,
<&topckgen CK_TOP_SPI_SEL>,
<&infracfg_ao CK_INFRA_SPI0_CK>,
<&infracfg_ao CK_INFRA_SPI0_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
status = "disabled";
};
spi1: spi@1100b000 {
compatible = "mediatek,ipm-spi-single";
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_CB_M_D2>,
<&topckgen CK_TOP_SPIM_MST_SEL>,
<&infracfg_ao CK_INFRA_SPI1_CK>,
<&infracfg_ao CK_INFRA_SPI1_HCK_CK>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
status = "disabled";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_EMMC_416M>,
<&topckgen CK_TOP_EMMC_250M>,
<&infracfg_ao CK_INFRA_MSDC_CK>;
clock-names = "source", "hclk", "source_cg";
assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
<&topckgen CK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&topckgen CK_TOP_CB_CKSQ_40M>;
status = "disabled";
};
auxadc: adc@1100d000 {
compatible = "mediatek,mt7986-auxadc",
"mediatek,mt7622-auxadc";
reg = <0 0x1100d000 0 0x1000>;
clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
consys: consys@10000000 {
compatible = "mediatek,mt7986-consys";
reg = <0 0x10000000 0 0x8600000>;
memory-region = <&wmcpu_emi>;
};
xhci: xhci@11200000 {
compatible = "mediatek,mt7986-xhci",
"mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
clocks = <&system_clk>,
<&system_clk>,
<&system_clk>,
<&system_clk>,
<&system_clk>;
clock-names = "sys_ck",
"xhci_ck",
"ref_ck",
"mcu_ck",
"dma_ck";
#address-cells = <2>;
#size-cells = <2>;
status = "okay";
};
usbtphy: usb-phy@11e10000 {
compatible = "mediatek,mt7986",
"mediatek,generic-tphy-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port0: usb-phy@11e10000 {
reg = <0 0x11e10000 0 0x700>;
clocks = <&system_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy@11e10700 {
reg = <0 0x11e10700 0 0x900>;
clocks = <&system_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u2port1: usb-phy@11e11000 {
reg = <0 0x11e11000 0 0x700>;
clocks = <&system_clk>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
clkitg: clkitg {
compatible = "simple-bus";
};
afe: audio-controller@11210000 {
compatible = "mediatek,mt7986-audio";
reg = <0 0x11210000 0 0x9000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
<&infracfg_ao CK_INFRA_AUD_26M_CK>,
<&infracfg_ao CK_INFRA_AUD_L_CK>,
<&infracfg_ao CK_INFRA_AUD_AUD_CK>,
<&infracfg_ao CK_INFRA_AUD_EG2_CK>;
clock-names = "aud_bus_ck",
"aud_26m_ck",
"aud_l_ck",
"aud_aud_ck",
"aud_eg2_ck";
assigned-clocks = <&topckgen CK_TOP_A1SYS_SEL>,
<&topckgen CK_TOP_AUD_L_SEL>,
<&topckgen CK_TOP_A_TUNER_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_APLL2_D4>,
<&topckgen CK_TOP_CB_APLL2_196M>,
<&topckgen CK_TOP_APLL2_D4>;
};
trng: trng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg_ao CK_INFRA_TRNG_CK>;
clock-names = "rng";
};
ice: ice_debug {
compatible = "mediatek,mt7986-ice_debug",
"mediatek,mt2701-ice_debug";
clocks = <&infracfg_ao CK_INFRA_DBG_CK>;
clock-names = "ice_dbg";
};
efuse: efuse@11d00000 {
compatible = "mediatek,mt7986-efuse",
"mediatek,efuse";
reg = <0 0x11d00000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
thermal_calibration: calib@274 {
reg = <0x274 0xc>;
};
};
};
#include "mt7986-clkitg.dtsi"