tree 1af9209f85bdbc2238aa7f75b2c63a6b7282aa5e
parent 2b101966085d8aa72734643c4045a77ee1b9d1ae
author developer <developer@mediatek.com> 1680248841 +0800
committer developer <developer@mediatek.com> 1680263028 +0800

[][mt7988][clk][Fix usb3 phy reference clock]

[Description]
Fix USB3 P0 and P1 device recognition problem.
USB3 P0/P1 need CK_TOP_SSPXTP_SEL and CK_TOP_USB_PHY_SEL clocks to work,
this patch adds the clock above to the clock tree hierarchy to ensure
both clocks are enabled by default.

[Release-log]
N/A

Change-Id: Ia0d08f021c95d3e1c7dcb4fbe80683bde0ae2cdc
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7329466