[][mt7988][clk][Fix usb3 phy reference clock]
[Description]
Fix USB3 P0 and P1 device recognition problem.
USB3 P0/P1 need CK_TOP_SSPXTP_SEL and CK_TOP_USB_PHY_SEL clocks to work,
this patch adds the clock above to the clock tree hierarchy to ensure
both clocks are enabled by default.
[Release-log]
N/A
Change-Id: Ia0d08f021c95d3e1c7dcb4fbe80683bde0ae2cdc
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7329466
diff --git a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
index 93585ce..9520ab8 100644
--- a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
+++ b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
@@ -138,8 +138,9 @@
FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", "usb_xhci", 1, 1),
FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", "usb_xhci_p1", 1,
1),
- FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "clkxtal", 1, 1),
- FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "clkxtal", 1, 1),
+ FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "sspxtp_sel", 1, 1),
+ FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "usb_phy_sel", 1,
+ 1),
FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", "clkxtal", 1, 1),
FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", "clkxtal", 1, 1),
FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",