[][Remove old legacy driver]
[Description]
Remove old legacy driver
[Release-log]
N/A
Change-Id: I5eecdc2e57de4de7f34a5cc64308960ab75bb124
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4525353
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Kconfig b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Kconfig
deleted file mode 100644
index f5be18e..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-config RAETH
- tristate "Mediatek Ethernet GMAC"
- ---help---
- This driver supports Mediatek gigabit ethernet family of
- adapters.
-
- Note that the answer to this question doesn't directly affect the
- kernel: saying N will just cause the configurator to skip all
- the questions about Mediatek Ethernet devices. If you say Y,
- you will be asked for your specific card in the following questions.
-
-if RAETH
-
-config GE1_SGMII_FORCE_2500
- bool "SGMII_FORCE_2500 (GigaSW)"
- depends on RAETH
- ---help---
- If you want to use sgmii force 2500.
- Please enable GE1_SGMII_FORCE_2500.
- Switch must support SGMII interface.
- This config will impact switch app makefile.
-
-config ETH_SKB_ALLOC_SELECT
- bool "SKB Allocation API Select"
-
-choice
- prompt "SKB Allocation API Selection"
- depends on ETH_SKB_ALLOC_SELECT
- default ETH_PAGE_ALLOC_SKB
-
-config ETH_SLAB_ALLOC_SKB
- bool "SLAB skb allocation"
-
-config ETH_PAGE_ALLOC_SKB
- bool "Page skb allocation"
-
-endchoice
-
-endif # RAETH
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Makefile b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Makefile
deleted file mode 100644
index e72dd58..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-obj-$(CONFIG_RAETH) += raeth.o
-raeth-objs := raether.o raether_pdma.o ra_mac.o mii_mgr.o ra_switch.o ra_dbg_proc.o
-raeth-objs += raether_qdma.o
-raeth-objs += raether_rss.o
-
-ifeq ($(CONFIG_RAETH_ETHTOOL),y)
-raeth-objs += ra_ethtool.o
-endif
-
-raeth-objs += raether_hwlro.o
-raeth-objs += ra_dbg_hwlro.o
-#raeth-objs += ra_dbg_hwioc.o
-
-ccflags-y += -Idrivers/net/ethernet/raeth
-ccflags-y += -Iinclude/linux/
-
-ifeq ($(CONFIG_RAETH_PDMA_DVT),y)
-raeth-objs += dvt/raether_pdma_dvt.o
-obj-m += dvt/pkt_gen.o
-obj-m += dvt/pkt_gen_udp_frag.o
-obj-m += dvt/pkt_gen_tcp_frag.o
-endif
-
-#ccflags-y += -Werror
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.c
deleted file mode 100644
index 7da2517..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "mii_mgr.h"
-
-void set_an_polling(u32 an_status)
-{
- if (an_status == 1)
- *(unsigned long *)(ESW_PHY_POLLING) |= (1 << 31);
- else
- *(unsigned long *)(ESW_PHY_POLLING) &= ~(1 << 31);
-}
-
-u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
-{
- u32 status = 0;
- u32 rc = 0;
- unsigned long t_start = jiffies;
- u32 data = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned long flags;
-
- spin_lock_irqsave(&ei_local->mdio_lock, flags);
- /* We enable mdio gpio purpose register, and disable it when exit. */
- enable_mdio(1);
-
- /* make sure previous read operation is complete */
- while (1) {
- /* 0 : Read/write operation complete */
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- break;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Read operation is ongoing !!\n");
- goto out;
- }
- }
-
- data =
- (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register <<
- 25);
- sys_reg_write(MDIO_PHY_CONTROL_0, data);
- sys_reg_write(MDIO_PHY_CONTROL_0, (data | (1 << 31)));
-
- /* make sure read operation is complete */
- t_start = jiffies;
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- status = sys_reg_read(MDIO_PHY_CONTROL_0);
- *read_data = (u32)(status & 0x0000FFFF);
-
- enable_mdio(0);
- rc = 1;
- goto out;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err
- ("\n MDIO Read operation Time Out!!\n");
- goto out;
- }
- }
-out:
- spin_unlock_irqrestore(&ei_local->mdio_lock, flags);
- return rc;
-}
-
-u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
-{
- unsigned long t_start = jiffies;
- u32 data;
- u32 rc = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned long flags;
-
- spin_lock_irqsave(&ei_local->mdio_lock, flags);
- enable_mdio(1);
-
- /* make sure previous write operation is complete */
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- break;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Write operation ongoing\n");
- goto out;
- }
- }
-
- data =
- (0x01 << 16) | (1 << 18) | (phy_addr << 20) | (phy_register << 25) |
- write_data;
- sys_reg_write(MDIO_PHY_CONTROL_0, data);
- sys_reg_write(MDIO_PHY_CONTROL_0, (data | (1 << 31))); /*start*/
- /* pr_err("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); */
-
- t_start = jiffies;
-
- /* make sure write operation is complete */
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- enable_mdio(0);
- rc = 1;
- goto out;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Write operation Time Out\n");
- goto out;
- }
- }
-out:
- spin_unlock_irqrestore(&ei_local->mdio_lock, flags);
- return rc;
-}
-
-u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u32 low_word;
- u32 high_word;
- u32 an_status = 0;
-
- if ((ei_local->architecture &
- (GE1_RGMII_FORCE_1000 | GE1_TRGMII_FORCE_2000 |
- GE1_TRGMII_FORCE_2600)) && (phy_addr == 31)) {
- an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1 << 31));
- if (an_status)
- set_an_polling(0);
- if (__mii_mgr_write
- (phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
- if (__mii_mgr_read
- (phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
- if (__mii_mgr_read
- (phy_addr, (0x1 << 4), &high_word)) {
- *read_data =
- (high_word << 16) | (low_word &
- 0xFFFF);
- if (an_status)
- set_an_polling(1);
- return 1;
- }
- }
- }
- if (an_status)
- set_an_polling(1);
- } else {
- if (__mii_mgr_read(phy_addr, phy_register, read_data))
- return 1;
- }
- return 0;
-}
-EXPORT_SYMBOL(mii_mgr_read);
-
-u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u32 an_status = 0;
-
- if ((ei_local->architecture &
- (GE1_RGMII_FORCE_1000 | GE1_TRGMII_FORCE_2000 |
- GE1_TRGMII_FORCE_2600)) && (phy_addr == 31)) {
- an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1 << 31));
- if (an_status)
- set_an_polling(0);
- if (__mii_mgr_write
- (phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
- if (__mii_mgr_write
- (phy_addr, ((phy_register >> 2) & 0xF),
- write_data & 0xFFFF)) {
- if (__mii_mgr_write
- (phy_addr, (0x1 << 4), write_data >> 16)) {
- if (an_status)
- set_an_polling(1);
- return 1;
- }
- }
- }
- if (an_status)
- set_an_polling(1);
- } else {
- if (__mii_mgr_write(phy_addr, phy_register, write_data))
- return 1;
- }
-
- return 0;
-}
-EXPORT_SYMBOL(mii_mgr_write);
-
-u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr)
-{
- u32 rc = 0;
- unsigned long t_start = jiffies;
- u32 data = 0;
-
- enable_mdio(1);
-
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- break;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- pr_err("\n MDIO Read operation is ongoing !!\n");
- return rc;
- }
- }
- data =
- (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) |
- reg_addr;
- sys_reg_write(MDIO_PHY_CONTROL_0, data);
- sys_reg_write(MDIO_PHY_CONTROL_0, (data | (1 << 31)));
-
- t_start = jiffies;
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- enable_mdio(0);
- return 1;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- pr_err("\n MDIO Write operation Time Out\n");
- return 0;
- }
- }
-}
-
-u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data)
-{
- u32 status = 0;
- u32 rc = 0;
- unsigned long t_start = jiffies;
- u32 data = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned long flags;
-
- spin_lock_irqsave(&ei_local->mdio_lock, flags);
- /* set address first */
- mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
- /* udelay(10); */
-
- enable_mdio(1);
-
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- break;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Read operation is ongoing !!\n");
- goto out;
- }
- }
- data =
- (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) |
- reg_addr;
- sys_reg_write(MDIO_PHY_CONTROL_0, data);
- sys_reg_write(MDIO_PHY_CONTROL_0, (data | (1 << 31)));
- t_start = jiffies;
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- *read_data =
- (sys_reg_read(MDIO_PHY_CONTROL_0) & 0x0000FFFF);
- enable_mdio(0);
- rc = 1;
- goto out;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err
- ("\n MDIO Read operation Time Out!!\n");
- goto out;
- }
- status = sys_reg_read(MDIO_PHY_CONTROL_0);
- }
-out:
- spin_unlock_irqrestore(&ei_local->mdio_lock, flags);
- return rc;
-}
-
-u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
-{
- u32 rc = 0;
- unsigned long t_start = jiffies;
- u32 data = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned long flags;
-
- spin_lock_irqsave(&ei_local->mdio_lock, flags);
- /* set address first */
- mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
- /* udelay(10); */
-
- enable_mdio(1);
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- break;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Read operation is ongoing !!\n");
- goto out;
- }
- }
-
- data =
- (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) |
- write_data;
- sys_reg_write(MDIO_PHY_CONTROL_0, data);
- sys_reg_write(MDIO_PHY_CONTROL_0, (data | (1 << 31)));
-
- t_start = jiffies;
-
- while (1) {
- if (!(sys_reg_read(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
- enable_mdio(0);
- rc = 1;
- goto out;
- } else if (time_after(jiffies, t_start + 5 * HZ)) {
- enable_mdio(0);
- rc = 0;
- pr_err("\n MDIO Write operation Time Out\n");
- goto out;
- }
- }
-out:
- spin_unlock_irqrestore(&ei_local->mdio_lock, flags);
- return rc;
-}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.h
deleted file mode 100644
index f8e0517..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/mii_mgr.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/netdevice.h>
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include "raether.h"
-
-extern struct net_device *dev_raether;
-
-#define PHY_CONTROL_0 0x0004
-#define MDIO_PHY_CONTROL_0 (RALINK_ETH_MAC_BASE + PHY_CONTROL_0)
-#define enable_mdio(x)
-
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwioc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwioc.c
deleted file mode 100644
index 1132903..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwioc.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "ra_dbg_proc.h"
-
-#define MCSI_A_PMU_CTL 0x10390100 /* PMU CTRL */
-#define MCSI_A_PMU_CYC_CNT 0x10399004 /* Cycle counter */
-#define MCSI_A_PMU_CYC_CTL 0x10399008 /* Cycle counter CTRL */
-
-#define MCSI_A_PMU_EVN_SEL0 0x1039A000 /* EVENT SELECT 0 */
-#define MCSI_A_PMU_EVN_CNT0 0x1039A004 /* Event Count 0 */
-#define MCSI_A_PMU_EVN_CTL0 0x1039A008 /* Event Count control 0 */
-
-#define MCSI_A_PMU_EVN_SEL1 0x1039B000 /* EVENT SELECT 1 */
-#define MCSI_A_PMU_EVN_CNT1 0x1039B004 /* Event Count 1 */
-#define MCSI_A_PMU_EVN_CTL1 0x1039B008 /* Event Count control 1 */
-
-#define MCSI_A_PMU_EVN_SEL2 0x1039C000 /* EVENT SELECT 2 */
-#define MCSI_A_PMU_EVN_CNT2 0x1039C004 /* Event Count 2 */
-#define MCSI_A_PMU_EVN_CTL2 0x1039C008 /* Event Count control 2 */
-
-#define MCSI_A_PMU_EVN_SEL3 0x1039D000 /* EVENT SELECT 3 */
-#define MCSI_A_PMU_EVN_CNT3 0x1039D004 /* Event Count 3 */
-#define MCSI_A_PMU_EVN_CTL3 0x1039D008 /* Event Count control 3 */
-
-#define PMU_EVN_SEL_S0 (0x0 << 5)
-#define PMU_EVN_SEL_S1 (0x1 << 5)
-#define PMU_EVN_SEL_S2 (0x2 << 5)
-#define PMU_EVN_SEL_S3 (0x3 << 5)
-#define PMU_EVN_SEL_S4 (0x4 << 5)
-#define PMU_EVN_SEL_S5 (0x5 << 5)
-#define PMU_EVN_SEL_M0 (0x6 << 5)
-#define PMU_EVN_SEL_M1 (0x7 << 5)
-#define PMU_EVN_SEL_M2 (0x8 << 5)
-
-#define PMU_EVN_READ_ANY 0x0
-#define PMU_EVN_READ_SNOOP 0x3
-#define PMU_EVN_READ_HIT 0xA
-#define PMU_EVN_WRITE_ANY 0xC
-#define PMU_EVN_WU_SNOOP 0x10
-#define PMU_EVN_WLU_SNOOP 0x11
-
-#define PMU_0_SEL (PMU_EVN_SEL_S2 | PMU_EVN_READ_SNOOP)
-#define PMU_1_SEL (PMU_EVN_SEL_S2 | PMU_EVN_READ_HIT)
-#define PMU_2_SEL (PMU_EVN_SEL_S4 | PMU_EVN_READ_SNOOP)
-#define PMU_3_SEL (PMU_EVN_SEL_S4 | PMU_EVN_READ_HIT)
-
-#define MCSI_A_PMU_CTL_BASE MCSI_A_PMU_CTL
-#define MCSI_A_PMU_CNT0_BASE MCSI_A_PMU_EVN_SEL0
-#define MCSI_A_PMU_CNT1_BASE MCSI_A_PMU_EVN_SEL1
-#define MCSI_A_PMU_CNT2_BASE MCSI_A_PMU_EVN_SEL2
-#define MCSI_A_PMU_CNT3_BASE MCSI_A_PMU_EVN_SEL3
-
-typedef int (*IOC_SET_FUNC) (int par1, int par2, int par3);
-static struct proc_dir_entry *proc_hw_io_coherent;
-
-unsigned int reg_pmu_evn_phys[] = {
- MCSI_A_PMU_CNT0_BASE,
- MCSI_A_PMU_CNT1_BASE,
- MCSI_A_PMU_CNT2_BASE,
- MCSI_A_PMU_CNT3_BASE,
-};
-
-int ioc_pmu_cnt_config(int pmu_no, int interface, int event)
-{
- void *reg_pmu_cnt;
- unsigned int pmu_sel;
-
- reg_pmu_cnt = ioremap(reg_pmu_evn_phys[pmu_no], 0x10);
-
- /* Event Select Register
- * bit[31:8] -> Reserved
- * bit[7:5] -> Event code to define which interface to monitor
- * bit[4:0] -> Event code to define which event to monitor
- */
- pmu_sel = (interface << 5) | event;
- sys_reg_write(reg_pmu_cnt, pmu_sel);
-
- /*Counter Control Registers
- * bit[31:1] -> Reserved
- * bit[0:0] -> Counter enable
- */
- sys_reg_write(reg_pmu_cnt + 0x8, 0x1);
-
- iounmap(reg_pmu_cnt);
-
- return 0;
-}
-
-int ioc_pmu_ctl_config(int enable, int ignore1, int ignore2)
-{
- void *reg_pmu_ctl;
-
- reg_pmu_ctl = ioremap(MCSI_A_PMU_CTL_BASE, 0x10);
-
- /*Performance Monitor Control Register
- * bit[31:16] -> Reserved
- * bit[15:12] -> Specifies the number of counters implemented
- * bit[11:6] -> Reserved
- * bit[5:5] -> DP: Disables cycle counter
- * bit[4:4] -> EX: Enable export of the events to the event bus
- * bit[3:3] -> CCD: Cycle count divider
- * bit[2:2] -> CCR: Cycle counter reset
- * bit[1:1] -> RST: Performance counter reset
- * bit[0:0] -> CEN: Enable bit
- */
- if (enable) {
- sys_reg_write(reg_pmu_ctl, BIT(1));
- sys_reg_write(reg_pmu_ctl, BIT(0));
- } else {
- sys_reg_write(reg_pmu_ctl, 0x0);
- }
-
- iounmap(reg_pmu_ctl);
-
- return 0;
-}
-
-int ioc_set_usage(int ignore1, int ignore2, int ignore3)
-{
- pr_info("<Usage> echo \"[OP Mode] [Arg1] [Arg2 | Arg3]\" > /proc/%s\n\r",
- PROCREG_HW_IO_COHERENT);
- pr_info("\tControl PMU counter: echo \"1 [Enable]\" > /proc/%s\n\r",
- PROCREG_HW_IO_COHERENT);
- pr_info("\t\t[Enable]:\n\r\t\t\t1: enable\n\r\t\t\t0: disable\n\r");
- pr_info("\tConfigure PMU counter: echo \"2 [CNT No.] [IF] [EVN]\" > /proc/%s\n\r",
- PROCREG_HW_IO_COHERENT);
- pr_info("\t\t[CNT No.]: 0/1/2/3 PMU Counter\n\r");
- pr_info("\t\t[IF]:\n\r");
- pr_info("\t\t\t0: PMU_EVN_SEL_S0\n\r");
- pr_info("\t\t\t1: PMU_EVN_SEL_S1\n\r");
- pr_info("\t\t\t2: PMU_EVN_SEL_S2\n\r");
- pr_info("\t\t\t3: PMU_EVN_SEL_S3\n\r");
- pr_info("\t\t\t4: PMU_EVN_SEL_S4\n\r");
- pr_info("\t\t\t5: PMU_EVN_SEL_S5\n\r");
- pr_info("\t\t\t6: PMU_EVN_SEL_M0\n\r");
- pr_info("\t\t\t7: PMU_EVN_SEL_M1\n\r");
- pr_info("\t\t\t8: PMU_EVN_SEL_M2\n\r");
- pr_info("\t\t[EVN]:\n\r");
- pr_info("\t\t\t0: PMU_EVN_READ_ANY\n\r");
- pr_info("\t\t\t3: PMU_EVN_READ_SNOOP\n\r");
- pr_info("\t\t\tA: PMU_EVN_READ_HIT\n\r");
- pr_info("\t\t\tC: PMU_EVN_WRITE_ANY\n\r");
- pr_info("\t\t\t10: PMU_EVN_WU_SNOOP\n\r");
- pr_info("\t\t\t11: PMU_EVN_WLU_SNOOP\n\r");
-
- return 0;
-}
-
-static const IOC_SET_FUNC iocoherent_set_func[] = {
- [0] = ioc_set_usage,
- [1] = ioc_pmu_ctl_config,
- [2] = ioc_pmu_cnt_config,
-};
-
-ssize_t ioc_pmu_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- char buf[32];
- char *p_buf;
- int len = count;
- long arg0 = 0, arg1 = 0, arg2 = 0, arg3 = 0;
- char *p_token = NULL;
- char *p_delimiter = " \t";
- int ret;
-
- if (len >= sizeof(buf)) {
- pr_err("input handling fail!\n");
- len = sizeof(buf) - 1;
- return -1;
- }
-
- if (copy_from_user(buf, buffer, len))
- return -EFAULT;
-
- buf[len] = '\0';
- pr_info("write parameter data = %s\n\r", buf);
-
- p_buf = buf;
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- arg0 = 0;
- else
- ret = kstrtol(p_token, 16, &arg0);
-
- switch (arg0) {
- case 1:
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- arg1 = 0;
- else
- ret = kstrtol(p_token, 16, &arg1);
- break;
- case 2:
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- arg1 = 0;
- else
- ret = kstrtol(p_token, 16, &arg1);
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- arg2 = 0;
- else
- ret = kstrtol(p_token, 16, &arg2);
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- arg3 = 0;
- else
- ret = kstrtol(p_token, 16, &arg3);
- break;
- }
-
- if (iocoherent_set_func[arg0] &&
- (ARRAY_SIZE(iocoherent_set_func) > arg0)) {
- (*iocoherent_set_func[arg0]) (arg1, arg2, arg3);
- } else {
- pr_info("no handler defined for command id(0x%08lx)\n\r", arg0);
- (*iocoherent_set_func[0]) (0, 0, 0);
- }
-
- return len;
-}
-
-int ioc_pmu_read(struct seq_file *seq, void *v)
-{
- void __iomem *reg_virt_0, *reg_virt_1, *reg_virt_2, *reg_virt_3;
-
- reg_virt_0 = ioremap(MCSI_A_PMU_EVN_SEL0, 0x10);
- reg_virt_1 = ioremap(MCSI_A_PMU_EVN_SEL1, 0x10);
- reg_virt_2 = ioremap(MCSI_A_PMU_EVN_SEL2, 0x10);
- reg_virt_3 = ioremap(MCSI_A_PMU_EVN_SEL3, 0x10);
-
- seq_printf(seq, "MCSI_A_PMU_EVN_SEL0 = 0x%x\n",
- sys_reg_read(reg_virt_0));
- seq_printf(seq, "MCSI_A_PMU_EVN_CNT0 = 0x%x\n",
- sys_reg_read(reg_virt_0 + 0x4));
- seq_printf(seq, "MCSI_A_PMU_EVN_CTL0 = 0x%x\n",
- sys_reg_read(reg_virt_0 + 0x8));
- seq_printf(seq, "MCSI_A_PMU_EVN_SEL1 = 0x%x\n",
- sys_reg_read(reg_virt_1));
- seq_printf(seq, "MCSI_A_PMU_EVN_CNT1 = 0x%x\n",
- sys_reg_read(reg_virt_1 + 0x4));
- seq_printf(seq, "MCSI_A_PMU_EVN_CTL1 = 0x%x\n",
- sys_reg_read(reg_virt_1 + 0x8));
-
- seq_printf(seq, "MCSI_A_PMU_EVN_SEL2 = 0x%x\n",
- sys_reg_read(reg_virt_2));
- seq_printf(seq, "MCSI_A_PMU_EVN_CNT2 = 0x%x\n",
- sys_reg_read(reg_virt_2 + 0x4));
- seq_printf(seq, "MCSI_A_PMU_EVN_CTL2 = 0x%x\n",
- sys_reg_read(reg_virt_2 + 0x8));
-
- seq_printf(seq, "MCSI_A_PMU_EVN_SEL3 = 0x%x\n",
- sys_reg_read(reg_virt_3));
- seq_printf(seq, "MCSI_A_PMU_EVN_CNT3 = 0x%x\n",
- sys_reg_read(reg_virt_3 + 0x4));
- seq_printf(seq, "MCSI_A_PMU_EVN_CTL3 = 0x%x\n",
- sys_reg_read(reg_virt_3 + 0x8));
-
- iounmap(reg_virt_0);
- iounmap(reg_virt_1);
- iounmap(reg_virt_2);
- iounmap(reg_virt_3);
- return 0;
-}
-
-static int ioc_pmu_open(struct inode *inode, struct file *file)
-{
- return single_open(file, ioc_pmu_read, NULL);
-}
-
-static const struct file_operations ioc_pmu_fops = {
- .owner = THIS_MODULE,
- .open = ioc_pmu_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = ioc_pmu_write,
- .release = single_release
-};
-
-void hwioc_debug_proc_init(struct proc_dir_entry *proc_reg_dir)
-{
- proc_hw_io_coherent =
- proc_create(PROCREG_HW_IO_COHERENT, 0, proc_reg_dir,
- &ioc_pmu_fops);
- if (!proc_hw_io_coherent)
- pr_err("FAIL to create %s PROC!\n", PROCREG_HW_IO_COHERENT);
-}
-EXPORT_SYMBOL(hwioc_debug_proc_init);
-
-void hwioc_debug_proc_exit(struct proc_dir_entry *proc_reg_dir)
-{
- if (proc_hw_io_coherent)
- remove_proc_entry(PROCREG_HW_IO_COHERENT, proc_reg_dir);
-}
-EXPORT_SYMBOL(hwioc_debug_proc_exit);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwlro.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwlro.c
deleted file mode 100644
index 1ecad66..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_hwlro.c
+++ /dev/null
@@ -1,629 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "raether_hwlro.h"
-#include "ra_dbg_proc.h"
-
-/* HW LRO proc */
-#define HW_LRO_RING_NUM 3
-#define MAX_HW_LRO_AGGR 64
-
-typedef int (*HWLRO_DBG_FUNC) (int par1, int par2);
-unsigned int hw_lro_agg_num_cnt[HW_LRO_RING_NUM][MAX_HW_LRO_AGGR + 1];
-unsigned int hw_lro_agg_size_cnt[HW_LRO_RING_NUM][16];
-unsigned int hw_lro_tot_agg_cnt[HW_LRO_RING_NUM];
-unsigned int hw_lro_tot_flush_cnt[HW_LRO_RING_NUM];
-
-/* HW LRO flush reason proc */
-#define HW_LRO_AGG_FLUSH (1)
-#define HW_LRO_AGE_FLUSH (2)
-#define HW_LRO_NOT_IN_SEQ_FLUSH (3)
-#define HW_LRO_TIMESTAMP_FLUSH (4)
-#define HW_LRO_NON_RULE_FLUSH (5)
-
-unsigned int hw_lro_agg_flush_cnt[HW_LRO_RING_NUM];
-unsigned int hw_lro_age_flush_cnt[HW_LRO_RING_NUM];
-unsigned int hw_lro_seq_flush_cnt[HW_LRO_RING_NUM];
-unsigned int hw_lro_timestamp_flush_cnt[HW_LRO_RING_NUM];
-unsigned int hw_lro_norule_flush_cnt[HW_LRO_RING_NUM];
-
-static struct proc_dir_entry *proc_rx_ring1, *proc_rx_ring2, *proc_rx_ring3;
-static struct proc_dir_entry *proc_hw_lro_stats, *proc_hw_lro_auto_tlb;
-
-int rx_lro_ring_read(struct seq_file *seq, void *v,
- struct PDMA_rxdesc *rx_ring_p)
-{
- struct PDMA_rxdesc *rx_ring;
- int i = 0;
-
- rx_ring =
- kmalloc(sizeof(struct PDMA_rxdesc) * NUM_LRO_RX_DESC, GFP_KERNEL);
- if (!rx_ring) {
- seq_puts(seq, " allocate temp rx_ring fail.\n");
- return 0;
- }
-
- for (i = 0; i < NUM_LRO_RX_DESC; i++)
- memcpy(&rx_ring[i], &rx_ring_p[i], sizeof(struct PDMA_rxdesc));
-
- for (i = 0; i < NUM_LRO_RX_DESC; i++) {
- seq_printf(seq, "%d: %08x %08x %08x %08x\n", i,
- *(int *)&rx_ring[i].rxd_info1,
- *(int *)&rx_ring[i].rxd_info2,
- *(int *)&rx_ring[i].rxd_info3,
- *(int *)&rx_ring[i].rxd_info4);
- }
-
- kfree(rx_ring);
- return 0;
-}
-
-int rx_ring1_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_lro_ring_read(seq, v, ei_local->rx_ring[1]);
-
- return 0;
-}
-
-int rx_ring2_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_lro_ring_read(seq, v, ei_local->rx_ring[2]);
-
- return 0;
-}
-
-int rx_ring3_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_lro_ring_read(seq, v, ei_local->rx_ring[3]);
-
- return 0;
-}
-
-static int rx_ring1_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rx_ring1_read, NULL);
-}
-
-static int rx_ring2_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rx_ring2_read, NULL);
-}
-
-static int rx_ring3_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rx_ring3_read, NULL);
-}
-
-static const struct file_operations rx_ring1_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring1_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static const struct file_operations rx_ring2_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring2_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static const struct file_operations rx_ring3_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring3_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static int hw_lro_len_update(unsigned int agg_size)
-{
- int len_idx;
-
- if (agg_size > 65000)
- len_idx = 13;
- else if (agg_size > 60000)
- len_idx = 12;
- else if (agg_size > 55000)
- len_idx = 11;
- else if (agg_size > 50000)
- len_idx = 10;
- else if (agg_size > 45000)
- len_idx = 9;
- else if (agg_size > 40000)
- len_idx = 8;
- else if (agg_size > 35000)
- len_idx = 7;
- else if (agg_size > 30000)
- len_idx = 6;
- else if (agg_size > 25000)
- len_idx = 5;
- else if (agg_size > 20000)
- len_idx = 4;
- else if (agg_size > 15000)
- len_idx = 3;
- else if (agg_size > 10000)
- len_idx = 2;
- else if (agg_size > 5000)
- len_idx = 1;
- else
- len_idx = 0;
-
- return len_idx;
-}
-
-void hw_lro_stats_update(unsigned int ring_num, struct PDMA_rxdesc *rx_ring)
-{
- unsigned int agg_cnt = rx_ring->rxd_info2.LRO_AGG_CNT;
- unsigned int agg_size = (rx_ring->rxd_info2.PLEN1 << 14) |
- rx_ring->rxd_info2.PLEN0;
-
- if ((ring_num > 0) && (ring_num < 4)) {
- hw_lro_agg_size_cnt[ring_num - 1]
- [hw_lro_len_update(agg_size)]++;
- hw_lro_agg_num_cnt[ring_num - 1][agg_cnt]++;
- hw_lro_tot_flush_cnt[ring_num - 1]++;
- hw_lro_tot_agg_cnt[ring_num - 1] += agg_cnt;
- }
-}
-
-void hw_lro_flush_stats_update(unsigned int ring_num,
- struct PDMA_rxdesc *rx_ring)
-{
- unsigned int flush_reason = rx_ring->rxd_info2.REV;
-
- if ((ring_num > 0) && (ring_num < 4)) {
- if ((flush_reason & 0x7) == HW_LRO_AGG_FLUSH)
- hw_lro_agg_flush_cnt[ring_num - 1]++;
- else if ((flush_reason & 0x7) == HW_LRO_AGE_FLUSH)
- hw_lro_age_flush_cnt[ring_num - 1]++;
- else if ((flush_reason & 0x7) == HW_LRO_NOT_IN_SEQ_FLUSH)
- hw_lro_seq_flush_cnt[ring_num - 1]++;
- else if ((flush_reason & 0x7) == HW_LRO_TIMESTAMP_FLUSH)
- hw_lro_timestamp_flush_cnt[ring_num - 1]++;
- else if ((flush_reason & 0x7) == HW_LRO_NON_RULE_FLUSH)
- hw_lro_norule_flush_cnt[ring_num - 1]++;
- }
-}
-EXPORT_SYMBOL(hw_lro_flush_stats_update);
-
-ssize_t hw_lro_stats_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- memset(hw_lro_agg_num_cnt, 0, sizeof(hw_lro_agg_num_cnt));
- memset(hw_lro_agg_size_cnt, 0, sizeof(hw_lro_agg_size_cnt));
- memset(hw_lro_tot_agg_cnt, 0, sizeof(hw_lro_tot_agg_cnt));
- memset(hw_lro_tot_flush_cnt, 0, sizeof(hw_lro_tot_flush_cnt));
- memset(hw_lro_agg_flush_cnt, 0, sizeof(hw_lro_agg_flush_cnt));
- memset(hw_lro_age_flush_cnt, 0, sizeof(hw_lro_age_flush_cnt));
- memset(hw_lro_seq_flush_cnt, 0, sizeof(hw_lro_seq_flush_cnt));
- memset(hw_lro_timestamp_flush_cnt, 0,
- sizeof(hw_lro_timestamp_flush_cnt));
- memset(hw_lro_norule_flush_cnt, 0, sizeof(hw_lro_norule_flush_cnt));
-
- pr_info("clear hw lro cnt table\n");
-
- return count;
-}
-
-int hw_lro_stats_read(struct seq_file *seq, void *v)
-{
- int i;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- seq_puts(seq, "HW LRO statistic dump:\n");
-
- /* Agg number count */
- seq_puts(seq, "Cnt: RING1 | RING2 | RING3 | Total\n");
- for (i = 0; i <= MAX_HW_LRO_AGGR; i++) {
- seq_printf(seq, " %d : %d %d %d %d\n",
- i, hw_lro_agg_num_cnt[0][i],
- hw_lro_agg_num_cnt[1][i], hw_lro_agg_num_cnt[2][i],
- hw_lro_agg_num_cnt[0][i] + hw_lro_agg_num_cnt[1][i] +
- hw_lro_agg_num_cnt[2][i]);
- }
-
- /* Total agg count */
- seq_puts(seq, "Total agg: RING1 | RING2 | RING3 | Total\n");
- seq_printf(seq, " %d %d %d %d\n",
- hw_lro_tot_agg_cnt[0], hw_lro_tot_agg_cnt[1],
- hw_lro_tot_agg_cnt[2],
- hw_lro_tot_agg_cnt[0] + hw_lro_tot_agg_cnt[1] +
- hw_lro_tot_agg_cnt[2]);
-
- /* Total flush count */
- seq_puts(seq, "Total flush: RING1 | RING2 | RING3 | Total\n");
- seq_printf(seq, " %d %d %d %d\n",
- hw_lro_tot_flush_cnt[0], hw_lro_tot_flush_cnt[1],
- hw_lro_tot_flush_cnt[2],
- hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
- hw_lro_tot_flush_cnt[2]);
-
- /* Avg agg count */
- seq_puts(seq, "Avg agg: RING1 | RING2 | RING3 | Total\n");
- seq_printf(seq, " %d %d %d %d\n",
- (hw_lro_tot_flush_cnt[0]) ? hw_lro_tot_agg_cnt[0] /
- hw_lro_tot_flush_cnt[0] : 0,
- (hw_lro_tot_flush_cnt[1]) ? hw_lro_tot_agg_cnt[1] /
- hw_lro_tot_flush_cnt[1] : 0,
- (hw_lro_tot_flush_cnt[2]) ? hw_lro_tot_agg_cnt[2] /
- hw_lro_tot_flush_cnt[2] : 0,
- (hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
- hw_lro_tot_flush_cnt[2]) ? ((hw_lro_tot_agg_cnt[0] +
- hw_lro_tot_agg_cnt[1] +
- hw_lro_tot_agg_cnt[2]) /
- (hw_lro_tot_flush_cnt[0] +
- hw_lro_tot_flush_cnt[1] +
- hw_lro_tot_flush_cnt[2])) : 0);
-
- /* Statistics of aggregation size counts */
- seq_puts(seq, "HW LRO flush pkt len:\n");
- seq_puts(seq, " Length | RING1 | RING2 | RING3 | Total\n");
- for (i = 0; i < 15; i++) {
- seq_printf(seq, "%d~%d: %d %d %d %d\n", i * 5000,
- (i + 1) * 5000, hw_lro_agg_size_cnt[0][i],
- hw_lro_agg_size_cnt[1][i], hw_lro_agg_size_cnt[2][i],
- hw_lro_agg_size_cnt[0][i] +
- hw_lro_agg_size_cnt[1][i] +
- hw_lro_agg_size_cnt[2][i]);
- }
-
- /* CONFIG_RAETH_HW_LRO_REASON_DBG */
- if (ei_local->features & FE_HW_LRO_DBG) {
- seq_puts(seq, "Flush reason: RING1 | RING2 | RING3 | Total\n");
- seq_printf(seq, "AGG timeout: %d %d %d %d\n",
- hw_lro_agg_flush_cnt[0], hw_lro_agg_flush_cnt[1],
- hw_lro_agg_flush_cnt[2],
- (hw_lro_agg_flush_cnt[0] + hw_lro_agg_flush_cnt[1] +
- hw_lro_agg_flush_cnt[2])
- );
- seq_printf(seq, "AGE timeout: %d %d %d %d\n",
- hw_lro_age_flush_cnt[0], hw_lro_age_flush_cnt[1],
- hw_lro_age_flush_cnt[2],
- (hw_lro_age_flush_cnt[0] + hw_lro_age_flush_cnt[1] +
- hw_lro_age_flush_cnt[2])
- );
- seq_printf(seq, "Not in-sequence: %d %d %d %d\n",
- hw_lro_seq_flush_cnt[0], hw_lro_seq_flush_cnt[1],
- hw_lro_seq_flush_cnt[2],
- (hw_lro_seq_flush_cnt[0] + hw_lro_seq_flush_cnt[1] +
- hw_lro_seq_flush_cnt[2])
- );
- seq_printf(seq, "Timestamp: %d %d %d %d\n",
- hw_lro_timestamp_flush_cnt[0],
- hw_lro_timestamp_flush_cnt[1],
- hw_lro_timestamp_flush_cnt[2],
- (hw_lro_timestamp_flush_cnt[0] +
- hw_lro_timestamp_flush_cnt[1] +
- hw_lro_timestamp_flush_cnt[2])
- );
- seq_printf(seq, "No LRO rule: %d %d %d %d\n",
- hw_lro_norule_flush_cnt[0],
- hw_lro_norule_flush_cnt[1],
- hw_lro_norule_flush_cnt[2],
- (hw_lro_norule_flush_cnt[0] +
- hw_lro_norule_flush_cnt[1] +
- hw_lro_norule_flush_cnt[2])
- );
- }
-
- return 0;
-}
-
-static int hw_lro_stats_open(struct inode *inode, struct file *file)
-{
- return single_open(file, hw_lro_stats_read, NULL);
-}
-
-static const struct file_operations hw_lro_stats_fops = {
- .owner = THIS_MODULE,
- .open = hw_lro_stats_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = hw_lro_stats_write,
- .release = single_release
-};
-
-int hwlro_agg_cnt_ctrl(int par1, int par2)
-{
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, par2);
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, par2);
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, par2);
- return 0;
-}
-
-int hwlro_agg_time_ctrl(int par1, int par2)
-{
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, par2);
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, par2);
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, par2);
- return 0;
-}
-
-int hwlro_age_time_ctrl(int par1, int par2)
-{
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, par2);
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, par2);
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, par2);
- return 0;
-}
-
-int hwlro_threshold_ctrl(int par1, int par2)
-{
- /* bandwidth threshold setting */
- SET_PDMA_LRO_BW_THRESHOLD(par2);
- return 0;
-}
-
-int hwlro_ring_enable_ctrl(int par1, int par2)
-{
- if (!par2) {
- pr_info("[hwlro_ring_enable_ctrl]Disable HW LRO rings\n");
- SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 0);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
- } else {
- pr_info("[hwlro_ring_enable_ctrl]Enable HW LRO rings\n");
- SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
- }
-
- return 0;
-}
-
-static const HWLRO_DBG_FUNC hw_lro_dbg_func[] = {
- [0] = hwlro_agg_cnt_ctrl,
- [1] = hwlro_agg_time_ctrl,
- [2] = hwlro_age_time_ctrl,
- [3] = hwlro_threshold_ctrl,
- [4] = hwlro_ring_enable_ctrl,
-};
-
-ssize_t hw_lro_auto_tlb_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- char buf[32];
- char *p_buf;
- int len = count;
- long x = 0, y = 0;
- char *p_token = NULL;
- char *p_delimiter = " \t";
- int ret;
-
- pr_info("[hw_lro_auto_tlb_write]write parameter len = %d\n\r",
- (int)len);
- if (len >= sizeof(buf)) {
- pr_info("input handling fail!\n");
- len = sizeof(buf) - 1;
- return -1;
- }
-
- if (copy_from_user(buf, buffer, len))
- return -EFAULT;
-
- buf[len] = '\0';
- pr_info("[hw_lro_auto_tlb_write]write parameter data = %s\n\r", buf);
-
- p_buf = buf;
- p_token = strsep(&p_buf, p_delimiter);
- if (!p_token)
- x = 0;
- else
- ret = kstrtol(p_token, 10, &x);
-
- p_token = strsep(&p_buf, "\t\n ");
- if (p_token) {
- ret = kstrtol(p_token, 10, &y);
- pr_info("y = %ld\n\r", y);
- }
-
- if (hw_lro_dbg_func[x] &&
- (ARRAY_SIZE(hw_lro_dbg_func) > x)) {
- (*hw_lro_dbg_func[x]) (x, y);
- }
-
- return count;
-}
-
-void hw_lro_auto_tlb_dump(struct seq_file *seq, unsigned int index)
-{
- int i;
- struct PDMA_LRO_AUTO_TLB_INFO pdma_lro_auto_tlb;
- unsigned int tlb_info[9];
- unsigned int dw_len, cnt, priority;
- unsigned int entry;
-
- if (index > 4)
- index = index - 1;
- entry = (index * 9) + 1;
-
- /* read valid entries of the auto-learn table */
- sys_reg_write(PDMA_FE_ALT_CF8, entry);
-
- /* seq_printf(seq, "\nEntry = %d\n", entry); */
- for (i = 0; i < 9; i++) {
- tlb_info[i] = sys_reg_read(PDMA_FE_ALT_SEQ_CFC);
- /* seq_printf(seq, "tlb_info[%d] = 0x%x\n", i, tlb_info[i]); */
- }
- memcpy(&pdma_lro_auto_tlb, tlb_info,
- sizeof(struct PDMA_LRO_AUTO_TLB_INFO));
-
- dw_len = pdma_lro_auto_tlb.auto_tlb_info7.DW_LEN;
- cnt = pdma_lro_auto_tlb.auto_tlb_info6.CNT;
-
- if (sys_reg_read(ADMA_LRO_CTRL_DW0) & PDMA_LRO_ALT_SCORE_MODE)
- priority = cnt; /* packet count */
- else
- priority = dw_len; /* byte count */
-
- /* dump valid entries of the auto-learn table */
- if (index >= 4)
- seq_printf(seq, "\n===== TABLE Entry: %d (Act) =====\n", index);
- else
- seq_printf(seq, "\n===== TABLE Entry: %d (LRU) =====\n", index);
- if (pdma_lro_auto_tlb.auto_tlb_info8.IPV4) {
- seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv4)\n",
- pdma_lro_auto_tlb.auto_tlb_info4.SIP3,
- pdma_lro_auto_tlb.auto_tlb_info3.SIP2,
- pdma_lro_auto_tlb.auto_tlb_info2.SIP1,
- pdma_lro_auto_tlb.auto_tlb_info1.SIP0);
- } else {
- seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n",
- pdma_lro_auto_tlb.auto_tlb_info4.SIP3,
- pdma_lro_auto_tlb.auto_tlb_info3.SIP2,
- pdma_lro_auto_tlb.auto_tlb_info2.SIP1,
- pdma_lro_auto_tlb.auto_tlb_info1.SIP0);
- }
- seq_printf(seq, "DIP_ID = %d\n",
- pdma_lro_auto_tlb.auto_tlb_info8.DIP_ID);
- seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n",
- pdma_lro_auto_tlb.auto_tlb_info0.STP,
- pdma_lro_auto_tlb.auto_tlb_info0.DTP);
- seq_printf(seq, "VLAN_VID_VLD = %d\n",
- pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID_VLD);
- seq_printf(seq, "VLAN1 = %d | VLAN2 = %d | VLAN3 = %d | VLAN4 =%d\n",
- (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 & 0xfff),
- ((pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 >> 12) & 0xfff),
- ((pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1 << 8) |
- ((pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 >> 24)
- & 0xfff)),
- ((pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1 >> 4) & 0xfff));
- seq_printf(seq, "TPUT = %d | FREQ = %d\n", dw_len, cnt);
- seq_printf(seq, "PRIORITY = %d\n", priority);
-}
-
-int hw_lro_auto_tlb_read(struct seq_file *seq, void *v)
-{
- int i;
- unsigned int reg_val;
- unsigned int reg_op1, reg_op2, reg_op3, reg_op4;
- unsigned int agg_cnt, agg_time, age_time;
-
- seq_puts(seq, "Usage of /proc/mt76xx/hw_lro_auto_tlb:\n");
- seq_puts(seq, "echo [function] [setting] > /proc/mt76xx/hw_lro_auto_tlb\n");
- seq_puts(seq, "Functions:\n");
- seq_puts(seq, "[0] = hwlro_agg_cnt_ctrl\n");
- seq_puts(seq, "[1] = hwlro_agg_time_ctrl\n");
- seq_puts(seq, "[2] = hwlro_age_time_ctrl\n");
- seq_puts(seq, "[3] = hwlro_threshold_ctrl\n");
- seq_puts(seq, "[4] = hwlro_ring_enable_ctrl\n\n");
-
- /* Read valid entries of the auto-learn table */
- sys_reg_write(PDMA_FE_ALT_CF8, 0);
- reg_val = sys_reg_read(PDMA_FE_ALT_SEQ_CFC);
-
- seq_printf(seq,
- "HW LRO Auto-learn Table: (PDMA_LRO_ALT_CFC_RSEQ_DBG=0x%x)\n",
- reg_val);
-
- for (i = 7; i >= 0; i--) {
- if (reg_val & (1 << i))
- hw_lro_auto_tlb_dump(seq, i);
- }
-
- /* Read the agg_time/age_time/agg_cnt of LRO rings */
- seq_puts(seq, "\nHW LRO Ring Settings\n");
- for (i = 1; i <= 3; i++) {
- reg_op1 = sys_reg_read(LRO_RX_RING0_CTRL_DW1 + (i * 0x40));
- reg_op2 = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + (i * 0x40));
- reg_op3 = sys_reg_read(LRO_RX_RING0_CTRL_DW3 + (i * 0x40));
- reg_op4 = sys_reg_read(ADMA_LRO_CTRL_DW2);
- agg_cnt =
- ((reg_op3 & 0x03) << PDMA_LRO_AGG_CNT_H_OFFSET) |
- ((reg_op2 >> PDMA_LRO_RING_AGG_CNT1_OFFSET) & 0x3f);
- agg_time = (reg_op2 >> PDMA_LRO_RING_AGG_OFFSET) & 0xffff;
- age_time =
- ((reg_op2 & 0x03f) << PDMA_LRO_AGE_H_OFFSET) |
- ((reg_op1 >> PDMA_LRO_RING_AGE1_OFFSET) & 0x3ff);
- seq_printf(seq,
- "Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n",
- i, agg_cnt, agg_time, age_time, reg_op4);
- }
- seq_puts(seq, "\n");
-
- return 0;
-}
-
-static int hw_lro_auto_tlb_open(struct inode *inode, struct file *file)
-{
- return single_open(file, hw_lro_auto_tlb_read, NULL);
-}
-
-static const struct file_operations hw_lro_auto_tlb_fops = {
- .owner = THIS_MODULE,
- .open = hw_lro_auto_tlb_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = hw_lro_auto_tlb_write,
- .release = single_release
-};
-
-int hwlro_debug_proc_init(struct proc_dir_entry *proc_reg_dir)
-{
- proc_rx_ring1 =
- proc_create(PROCREG_RXRING1, 0, proc_reg_dir, &rx_ring1_fops);
- if (!proc_rx_ring1)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING1);
-
- proc_rx_ring2 =
- proc_create(PROCREG_RXRING2, 0, proc_reg_dir, &rx_ring2_fops);
- if (!proc_rx_ring2)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING2);
-
- proc_rx_ring3 =
- proc_create(PROCREG_RXRING3, 0, proc_reg_dir, &rx_ring3_fops);
- if (!proc_rx_ring3)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING3);
-
- proc_hw_lro_stats =
- proc_create(PROCREG_HW_LRO_STATS, 0, proc_reg_dir,
- &hw_lro_stats_fops);
- if (!proc_hw_lro_stats)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_STATS);
-
- proc_hw_lro_auto_tlb =
- proc_create(PROCREG_HW_LRO_AUTO_TLB, 0, proc_reg_dir,
- &hw_lro_auto_tlb_fops);
- if (!proc_hw_lro_auto_tlb)
- pr_info("!! FAIL to create %s PROC !!\n",
- PROCREG_HW_LRO_AUTO_TLB);
-
- return 0;
-}
-EXPORT_SYMBOL(hwlro_debug_proc_init);
-
-void hwlro_debug_proc_exit(struct proc_dir_entry *proc_reg_dir)
-{
- if (proc_rx_ring1)
- remove_proc_entry(PROCREG_RXRING1, proc_reg_dir);
- if (proc_rx_ring2)
- remove_proc_entry(PROCREG_RXRING2, proc_reg_dir);
- if (proc_rx_ring3)
- remove_proc_entry(PROCREG_RXRING3, proc_reg_dir);
- if (proc_hw_lro_stats)
- remove_proc_entry(PROCREG_HW_LRO_STATS, proc_reg_dir);
- if (proc_hw_lro_auto_tlb)
- remove_proc_entry(PROCREG_HW_LRO_AUTO_TLB, proc_reg_dir);
-}
-EXPORT_SYMBOL(hwlro_debug_proc_exit);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.c
deleted file mode 100644
index 468dc84..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.c
+++ /dev/null
@@ -1,1672 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "ra_dbg_proc.h"
-#include "ra_ethtool.h"
-
-int txd_cnt[MAX_SKB_FRAGS / 2 + 1];
-int tso_cnt[16];
-
-#define MAX_AGGR 64
-#define MAX_DESC 8
-int lro_stats_cnt[MAX_AGGR + 1];
-int lro_flush_cnt[MAX_AGGR + 1];
-int lro_len_cnt1[16];
-/* int lro_len_cnt2[16]; */
-int aggregated[MAX_DESC];
-int lro_aggregated;
-int lro_flushed;
-int lro_nodesc;
-int force_flush;
-int tot_called1;
-int tot_called2;
-
-struct raeth_int_t raeth_int;
-struct proc_dir_entry *proc_reg_dir;
-static struct proc_dir_entry *proc_gmac, *proc_sys_cp0, *proc_tx_ring,
-*proc_rx_ring, *proc_skb_free;
-static struct proc_dir_entry *proc_gmac2;
-static struct proc_dir_entry *proc_ra_snmp;
-static struct proc_dir_entry *proc_num_of_txd, *proc_tso_len;
-static struct proc_dir_entry *proc_sche;
-static struct proc_dir_entry *proc_int_dbg;
-static struct proc_dir_entry *proc_set_lan_ip;
-/*extern unsigned int M2Q_table[64];
- * extern struct QDMA_txdesc *free_head;
- * extern struct SFQ_table *sfq0;
- * extern struct SFQ_table *sfq1;
- * extern struct SFQ_table *sfq2;
- * extern struct SFQ_table *sfq3;
- */
-
-static int ra_snmp_seq_show(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & USER_SNMPD) {
- seq_printf(seq, "rx counters: %x %x %x %x %x %x %x\n",
- sys_reg_read(GDMA_RX_GBCNT0),
- sys_reg_read(GDMA_RX_GPCNT0),
- sys_reg_read(GDMA_RX_OERCNT0),
- sys_reg_read(GDMA_RX_FERCNT0),
- sys_reg_read(GDMA_RX_SERCNT0),
- sys_reg_read(GDMA_RX_LERCNT0),
- sys_reg_read(GDMA_RX_CERCNT0));
- seq_printf(seq, "fc config: %x %x %p %x\n",
- sys_reg_read(CDMA_FC_CFG),
- sys_reg_read(GDMA1_FC_CFG),
- PDMA_FC_CFG, sys_reg_read(PDMA_FC_CFG));
- seq_printf(seq, "ports: %x %x %x %x %x %x\n",
- sys_reg_read(PORT0_PKCOUNT),
- sys_reg_read(PORT1_PKCOUNT),
- sys_reg_read(PORT2_PKCOUNT),
- sys_reg_read(PORT3_PKCOUNT),
- sys_reg_read(PORT4_PKCOUNT),
- sys_reg_read(PORT5_PKCOUNT));
- }
-
- return 0;
-}
-
-static int ra_snmp_seq_open(struct inode *inode, struct file *file)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & USER_SNMPD)
- return single_open(file, ra_snmp_seq_show, NULL);
- else
- return 0;
-}
-
-static const struct file_operations ra_snmp_seq_fops = {
- .owner = THIS_MODULE,
- .open = ra_snmp_seq_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-/*Routine Name : get_idx(mode, index)
- * Description: calculate ring usage for tx/rx rings
- * Mode 1 : Tx Ring
- * Mode 2 : Rx Ring
- */
-int get_ring_usage(int mode, int i)
-{
- unsigned long tx_ctx_idx, tx_dtx_idx, tx_usage;
- unsigned long rx_calc_idx, rx_drx_idx, rx_usage;
-
- struct PDMA_rxdesc *rxring;
- struct PDMA_txdesc *txring;
-
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (mode == 2) {
- /* cpu point to the next descriptor of rx dma ring */
- rx_calc_idx = *(unsigned long *)RX_CALC_IDX0;
- rx_drx_idx = *(unsigned long *)RX_DRX_IDX0;
- rxring = (struct PDMA_rxdesc *)RX_BASE_PTR0;
-
- rx_usage =
- (rx_drx_idx - rx_calc_idx - 1 + num_rx_desc) % num_rx_desc;
- if (rx_calc_idx == rx_drx_idx) {
- if (rxring[rx_drx_idx].rxd_info2.DDONE_bit == 1)
- tx_usage = num_rx_desc;
- else
- tx_usage = 0;
- }
- return rx_usage;
- }
-
- switch (i) {
- case 0:
- tx_ctx_idx = *(unsigned long *)TX_CTX_IDX0;
- tx_dtx_idx = *(unsigned long *)TX_DTX_IDX0;
- txring = ei_local->tx_ring0;
- break;
- default:
- pr_debug("get_tx_idx failed %d %d\n", mode, i);
- return 0;
- };
-
- tx_usage = (tx_ctx_idx - tx_dtx_idx + num_tx_desc) % num_tx_desc;
- if (tx_ctx_idx == tx_dtx_idx) {
- if (txring[tx_ctx_idx].txd_info2.DDONE_bit == 1)
- tx_usage = 0;
- else
- tx_usage = num_tx_desc;
- }
- return tx_usage;
-}
-
-void dump_reg(struct seq_file *s)
-{
- int fe_int_enable;
- int rx_usage;
- int dly_int_cfg;
- int rx_base_ptr0;
- int rx_max_cnt0;
- int rx_calc_idx0;
- int rx_drx_idx0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- int tx_usage = 0;
- int tx_base_ptr[4];
- int tx_max_cnt[4];
- int tx_ctx_idx[4];
- int tx_dtx_idx[4];
- int i;
-
- fe_int_enable = sys_reg_read(FE_INT_ENABLE);
- rx_usage = get_ring_usage(2, 0);
-
- dly_int_cfg = sys_reg_read(DLY_INT_CFG);
-
- if (!(ei_local->features & FE_QDMA)) {
- tx_usage = get_ring_usage(1, 0);
-
- tx_base_ptr[0] = sys_reg_read(TX_BASE_PTR0);
- tx_max_cnt[0] = sys_reg_read(TX_MAX_CNT0);
- tx_ctx_idx[0] = sys_reg_read(TX_CTX_IDX0);
- tx_dtx_idx[0] = sys_reg_read(TX_DTX_IDX0);
-
- tx_base_ptr[1] = sys_reg_read(TX_BASE_PTR1);
- tx_max_cnt[1] = sys_reg_read(TX_MAX_CNT1);
- tx_ctx_idx[1] = sys_reg_read(TX_CTX_IDX1);
- tx_dtx_idx[1] = sys_reg_read(TX_DTX_IDX1);
-
- tx_base_ptr[2] = sys_reg_read(TX_BASE_PTR2);
- tx_max_cnt[2] = sys_reg_read(TX_MAX_CNT2);
- tx_ctx_idx[2] = sys_reg_read(TX_CTX_IDX2);
- tx_dtx_idx[2] = sys_reg_read(TX_DTX_IDX2);
-
- tx_base_ptr[3] = sys_reg_read(TX_BASE_PTR3);
- tx_max_cnt[3] = sys_reg_read(TX_MAX_CNT3);
- tx_ctx_idx[3] = sys_reg_read(TX_CTX_IDX3);
- tx_dtx_idx[3] = sys_reg_read(TX_DTX_IDX3);
- }
-
- rx_base_ptr0 = sys_reg_read(RX_BASE_PTR0);
- rx_max_cnt0 = sys_reg_read(RX_MAX_CNT0);
- rx_calc_idx0 = sys_reg_read(RX_CALC_IDX0);
- rx_drx_idx0 = sys_reg_read(RX_DRX_IDX0);
-
- seq_printf(s, "\n\nFE_INT_ENABLE : 0x%08x\n", fe_int_enable);
-
- if (!(ei_local->features & FE_QDMA))
- seq_printf(s, "TxRing PktCnt: %d/%d\n", tx_usage, num_tx_desc);
-
- seq_printf(s, "RxRing PktCnt: %d/%d\n\n", rx_usage, num_rx_desc);
- seq_printf(s, "DLY_INT_CFG : 0x%08x\n", dly_int_cfg);
-
- if (!(ei_local->features & FE_QDMA)) {
- for (i = 0; i < 4; i++) {
- seq_printf(s, "TX_BASE_PTR%d : 0x%08x\n", i,
- tx_base_ptr[i]);
- seq_printf(s, "TX_MAX_CNT%d : 0x%08x\n", i,
- tx_max_cnt[i]);
- seq_printf(s, "TX_CTX_IDX%d : 0x%08x\n", i,
- tx_ctx_idx[i]);
- seq_printf(s, "TX_DTX_IDX%d : 0x%08x\n", i,
- tx_dtx_idx[i]);
- }
- }
-
- seq_printf(s, "RX_BASE_PTR0 : 0x%08x\n", rx_base_ptr0);
- seq_printf(s, "RX_MAX_CNT0 : 0x%08x\n", rx_max_cnt0);
- seq_printf(s, "RX_CALC_IDX0 : 0x%08x\n", rx_calc_idx0);
- seq_printf(s, "RX_DRX_IDX0 : 0x%08x\n", rx_drx_idx0);
-
- if (ei_local->features & FE_ETHTOOL)
- seq_printf(s,
- "The current PHY address selected by ethtool is %d\n",
- get_current_phy_address());
-}
-
-int reg_read_main(struct seq_file *seq, void *v)
-{
- dump_reg(seq);
- return 0;
-}
-
-static void *seq_skb_free_start(struct seq_file *seq, loff_t *pos)
-{
- if (*pos < num_tx_desc)
- return pos;
- return NULL;
-}
-
-static void *seq_skb_free_next(struct seq_file *seq, void *v, loff_t *pos)
-{
- (*pos)++;
- if (*pos >= num_tx_desc)
- return NULL;
- return pos;
-}
-
-static void seq_skb_free_stop(struct seq_file *seq, void *v)
-{
- /* Nothing to do */
-}
-
-static int seq_skb_free_show(struct seq_file *seq, void *v)
-{
- int i = *(loff_t *)v;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- seq_printf(seq, "%d: %08x\n", i, *(int *)&ei_local->skb_free[i]);
-
- return 0;
-}
-
-static const struct seq_operations seq_skb_free_ops = {
- .start = seq_skb_free_start,
- .next = seq_skb_free_next,
- .stop = seq_skb_free_stop,
- .show = seq_skb_free_show
-};
-
-static int skb_free_open(struct inode *inode, struct file *file)
-{
- return seq_open(file, &seq_skb_free_ops);
-}
-
-static const struct file_operations skb_free_fops = {
- .owner = THIS_MODULE,
- .open = skb_free_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release
-};
-
-int qdma_read_64queue(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_QDMA) {
- unsigned int temp, i;
- unsigned int sw_fq, hw_fq;
- unsigned int min_en, min_rate, max_en, max_rate, sch, weight;
- unsigned int queue, tx_des_cnt, hw_resv, sw_resv, queue_head,
- queue_tail, queue_no;
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- seq_puts(seq, "==== General Information ====\n");
- temp = sys_reg_read(QDMA_FQ_CNT);
- sw_fq = (temp & 0xFFFF0000) >> 16;
- hw_fq = (temp & 0x0000FFFF);
- seq_printf(seq, "SW TXD: %d/%d; HW TXD: %d/%d\n", sw_fq,
- num_tx_desc, hw_fq, NUM_QDMA_PAGE);
- seq_printf(seq, "SW TXD virtual start address: 0x%p\n",
- ei_local->txd_pool);
- seq_printf(seq, "HW TXD virtual start address: 0x%p\n\n",
- free_head);
-
- seq_puts(seq, "==== Scheduler Information ====\n");
- temp = sys_reg_read(QDMA_TX_SCH);
- max_en = (temp & 0x00000800) >> 11;
- max_rate = (temp & 0x000007F0) >> 4;
- for (i = 0; i < (temp & 0x0000000F); i++)
- max_rate *= 10;
- seq_printf(seq, "SCH1 rate control:%d. Rate is %dKbps.\n",
- max_en, max_rate);
- max_en = (temp & 0x08000000) >> 27;
- max_rate = (temp & 0x07F00000) >> 20;
- for (i = 0; i < (temp & 0x000F0000); i++)
- max_rate *= 10;
- seq_printf(seq, "SCH2 rate control:%d. Rate is %dKbps.\n\n",
- max_en, max_rate);
-
- seq_puts(seq, "==== Physical Queue Information ====\n");
- sys_reg_write(QDMA_PAGE, 0);
- for (queue = 0; queue < 64; queue++) {
- if (queue < 16) {
- sys_reg_write(QDMA_PAGE, 0);
- queue_no = queue;
- } else if (queue > 15 && queue <= 31) {
- sys_reg_write(QDMA_PAGE, 1);
- queue_no = queue % 16;
- } else if (queue > 31 && queue <= 47) {
- sys_reg_write(QDMA_PAGE, 2);
- queue_no = queue % 32;
- } else if (queue > 47 && queue <= 63) {
- sys_reg_write(QDMA_PAGE, 3);
- queue_no = queue % 48;
- }
-
- temp = sys_reg_read(QTX_CFG_0 + 0x10 * queue_no);
- tx_des_cnt = (temp & 0xffff0000) >> 16;
- hw_resv = (temp & 0xff00) >> 8;
- sw_resv = (temp & 0xff);
- temp = sys_reg_read(QTX_CFG_0 + (0x10 * queue_no) + 0x4);
- sch = (temp >> 31) + 1;
- min_en = (temp & 0x8000000) >> 27;
- min_rate = (temp & 0x7f00000) >> 20;
- for (i = 0; i < (temp & 0xf0000) >> 16; i++)
- min_rate *= 10;
- max_en = (temp & 0x800) >> 11;
- max_rate = (temp & 0x7f0) >> 4;
- for (i = 0; i < (temp & 0xf); i++)
- max_rate *= 10;
- weight = (temp & 0xf000) >> 12;
- queue_head = sys_reg_read(QTX_HEAD_0 + 0x10 * queue_no);
- queue_tail = sys_reg_read(QTX_TAIL_0 + 0x10 * queue_no);
-
- seq_printf(seq, "Queue#%d Information:\n", queue);
- seq_printf(seq,
- "%d packets in the queue; head address is 0x%08x, tail address is 0x%08x.\n",
- tx_des_cnt, queue_head, queue_tail);
- seq_printf(seq,
- "HW_RESV: %d; SW_RESV: %d; SCH: %d; Weighting: %d\n",
- hw_resv, sw_resv, sch, weight);
- seq_printf(seq,
- "Min_Rate_En is %d, Min_Rate is %dKbps; Max_Rate_En is %d, Max_Rate is %dKbps.\n\n",
- min_en, min_rate, max_en, max_rate);
- }
- if (ei_local->features & FE_HW_SFQ) {
- seq_puts(seq, "==== Virtual Queue Information ====\n");
- seq_printf(seq,
- "VQTX_TB_BASE_0:0x%p;VQTX_TB_BASE_1:0x%p;VQTX_TB_BASE_2:0x%p;VQTX_TB_BASE_3:0x%p\n",
- sfq0, sfq1, sfq2, sfq3);
- temp = sys_reg_read(VQTX_NUM);
- seq_printf(seq,
- "VQTX_NUM_0:0x%01x;VQTX_NUM_1:0x%01x;VQTX_NUM_2:0x%01x;VQTX_NUM_3:0x%01x\n\n",
- temp & 0xF, (temp & 0xF0) >> 4,
- (temp & 0xF00) >> 8, (temp & 0xF000) >> 12);
- }
-
- seq_puts(seq, "==== Flow Control Information ====\n");
- temp = sys_reg_read(QDMA_FC_THRES);
- seq_printf(seq,
- "SW_DROP_EN:%x; SW_DROP_FFA:%d; SW_DROP_MODE:%d\n",
- (temp & 0x1000000) >> 24, (temp & 0x2000000) >> 25,
- (temp & 0x30000000) >> 28);
- seq_printf(seq,
- "WH_DROP_EN:%x; HW_DROP_FFA:%d; HW_DROP_MODE:%d\n",
- (temp & 0x10000) >> 16, (temp & 0x20000) >> 17,
- (temp & 0x300000) >> 20);
- seq_printf(seq, "SW_DROP_FSTVQ_MODE:%d;SW_DROP_FSTVQ:%d\n",
- (temp & 0xC0000000) >> 30,
- (temp & 0x08000000) >> 27);
- seq_printf(seq, "HW_DROP_FSTVQ_MODE:%d;HW_DROP_FSTVQ:%d\n",
- (temp & 0xC00000) >> 22, (temp & 0x080000) >> 19);
-
- seq_puts(seq, "\n==== FSM Information\n");
- temp = sys_reg_read(QDMA_DMA);
- seq_printf(seq, "VQTB_FSM:0x%01x\n", (temp & 0x0F000000) >> 24);
- seq_printf(seq, "FQ_FSM:0x%01x\n", (temp & 0x000F0000) >> 16);
- seq_printf(seq, "TX_FSM:0x%01x\n", (temp & 0x00000F00) >> 8);
- seq_printf(seq, "RX_FSM:0x%01x\n\n", (temp & 0x0000000f));
-
- seq_puts(seq, "==== M2Q Information ====\n");
- for (i = 0; i < 64; i += 8) {
- seq_printf(seq,
- " (%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)\n",
- i, M2Q_table[i], i + 1, M2Q_table[i + 1],
- i + 2, M2Q_table[i + 2], i + 3,
- M2Q_table[i + 3], i + 4, M2Q_table[i + 4],
- i + 5, M2Q_table[i + 5], i + 6,
- M2Q_table[i + 6], i + 7, M2Q_table[i + 7]);
- }
-
- return 0;
- } else {
- return 0;
- }
-}
-
-int qdma_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_QDMA) {
- unsigned int temp, i;
- unsigned int sw_fq, hw_fq;
- unsigned int min_en, min_rate, max_en, max_rate, sch, weight;
- unsigned int queue, tx_des_cnt, hw_resv, sw_resv, queue_head,
- queue_tail;
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- seq_puts(seq, "==== General Information ====\n");
- temp = sys_reg_read(QDMA_FQ_CNT);
- sw_fq = (temp & 0xFFFF0000) >> 16;
- hw_fq = (temp & 0x0000FFFF);
- seq_printf(seq, "SW TXD: %d/%d; HW TXD: %d/%d\n", sw_fq,
- num_tx_desc, hw_fq, NUM_QDMA_PAGE);
- seq_printf(seq, "SW TXD virtual start address: 0x%p\n",
- ei_local->txd_pool);
- seq_printf(seq, "HW TXD virtual start address: 0x%p\n\n",
- free_head);
-
- seq_puts(seq, "==== Scheduler Information ====\n");
- temp = sys_reg_read(QDMA_TX_SCH);
- max_en = (temp & 0x00000800) >> 11;
- max_rate = (temp & 0x000007F0) >> 4;
- for (i = 0; i < (temp & 0x0000000F); i++)
- max_rate *= 10;
- seq_printf(seq, "SCH1 rate control:%d. Rate is %dKbps.\n",
- max_en, max_rate);
- max_en = (temp & 0x08000000) >> 27;
- max_rate = (temp & 0x07F00000) >> 20;
- for (i = 0; i < (temp & 0x000F0000); i++)
- max_rate *= 10;
- seq_printf(seq, "SCH2 rate control:%d. Rate is %dKbps.\n\n",
- max_en, max_rate);
-
- seq_puts(seq, "==== Physical Queue Information ====\n");
- for (queue = 0; queue < 16; queue++) {
- temp = sys_reg_read(QTX_CFG_0 + 0x10 * queue);
- tx_des_cnt = (temp & 0xffff0000) >> 16;
- hw_resv = (temp & 0xff00) >> 8;
- sw_resv = (temp & 0xff);
- temp = sys_reg_read(QTX_CFG_0 + (0x10 * queue) + 0x4);
- sch = (temp >> 31) + 1;
- min_en = (temp & 0x8000000) >> 27;
- min_rate = (temp & 0x7f00000) >> 20;
- for (i = 0; i < (temp & 0xf0000) >> 16; i++)
- min_rate *= 10;
- max_en = (temp & 0x800) >> 11;
- max_rate = (temp & 0x7f0) >> 4;
- for (i = 0; i < (temp & 0xf); i++)
- max_rate *= 10;
- weight = (temp & 0xf000) >> 12;
- queue_head = sys_reg_read(QTX_HEAD_0 + 0x10 * queue);
- queue_tail = sys_reg_read(QTX_TAIL_0 + 0x10 * queue);
-
- seq_printf(seq, "Queue#%d Information:\n", queue);
- seq_printf(seq,
- "%d packets in the queue; head address is 0x%08x, tail address is 0x%08x.\n",
- tx_des_cnt, queue_head, queue_tail);
- seq_printf(seq,
- "HW_RESV: %d; SW_RESV: %d; SCH: %d; Weighting: %d\n",
- hw_resv, sw_resv, sch, weight);
- seq_printf(seq,
- "Min_Rate_En is %d, Min_Rate is %dKbps; Max_Rate_En is %d, Max_Rate is %dKbps.\n\n",
- min_en, min_rate, max_en, max_rate);
- }
- if (ei_local->features & FE_HW_SFQ) {
- seq_puts(seq, "==== Virtual Queue Information ====\n");
- seq_printf(seq,
- "VQTX_TB_BASE_0:0x%p;VQTX_TB_BASE_1:0x%p;VQTX_TB_BASE_2:0x%p;VQTX_TB_BASE_3:0x%p\n",
- sfq0, sfq1, sfq2, sfq3);
- temp = sys_reg_read(VQTX_NUM);
- seq_printf(seq,
- "VQTX_NUM_0:0x%01x;VQTX_NUM_1:0x%01x;VQTX_NUM_2:0x%01x;VQTX_NUM_3:0x%01x\n\n",
- temp & 0xF, (temp & 0xF0) >> 4,
- (temp & 0xF00) >> 8, (temp & 0xF000) >> 12);
- }
-
- seq_puts(seq, "==== Flow Control Information ====\n");
- temp = sys_reg_read(QDMA_FC_THRES);
- seq_printf(seq,
- "SW_DROP_EN:%x; SW_DROP_FFA:%d; SW_DROP_MODE:%d\n",
- (temp & 0x1000000) >> 24, (temp & 0x2000000) >> 25,
- (temp & 0x30000000) >> 28);
- seq_printf(seq,
- "WH_DROP_EN:%x; HW_DROP_FFA:%d; HW_DROP_MODE:%d\n",
- (temp & 0x10000) >> 16, (temp & 0x20000) >> 17,
- (temp & 0x300000) >> 20);
- seq_printf(seq, "SW_DROP_FSTVQ_MODE:%d;SW_DROP_FSTVQ:%d\n",
- (temp & 0xC0000000) >> 30,
- (temp & 0x08000000) >> 27);
- seq_printf(seq, "HW_DROP_FSTVQ_MODE:%d;HW_DROP_FSTVQ:%d\n",
- (temp & 0xC00000) >> 22, (temp & 0x080000) >> 19);
-
- seq_puts(seq, "\n==== FSM Information\n");
- temp = sys_reg_read(QDMA_DMA);
- seq_printf(seq, "VQTB_FSM:0x%01x\n", (temp & 0x0F000000) >> 24);
- seq_printf(seq, "FQ_FSM:0x%01x\n", (temp & 0x000F0000) >> 16);
- seq_printf(seq, "TX_FSM:0x%01x\n", (temp & 0x00000F00) >> 8);
- seq_printf(seq, "RX_FSM:0x%01x\n\n", (temp & 0x0000000f));
-
- seq_puts(seq, "==== M2Q Information ====\n");
- for (i = 0; i < 64; i += 8) {
- seq_printf(seq,
- " (%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)\n",
- i, M2Q_table[i], i + 1, M2Q_table[i + 1],
- i + 2, M2Q_table[i + 2], i + 3,
- M2Q_table[i + 3], i + 4, M2Q_table[i + 4],
- i + 5, M2Q_table[i + 5], i + 6,
- M2Q_table[i + 6], i + 7, M2Q_table[i + 7]);
- }
-
- return 0;
- } else {
- return 0;
- }
-}
-
-static int qdma_open(struct inode *inode, struct file *file)
-{
- return single_open(file, qdma_read, NULL);
-}
-
-static const struct file_operations qdma_fops = {
- .owner = THIS_MODULE,
- .open = qdma_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-int tx_ring_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- struct PDMA_txdesc *tx_ring;
- int i = 0;
-
- tx_ring = kmalloc_array(num_tx_desc, sizeof(*tx_ring), GFP_KERNEL);
-
- if (!tx_ring)
- /*seq_puts(seq, " allocate temp tx_ring fail.\n"); */
- return 0;
-
- for (i = 0; i < num_tx_desc; i++)
- tx_ring[i] = ei_local->tx_ring0[i];
-
- for (i = 0; i < num_tx_desc; i++) {
- seq_printf(seq, "%d: %08x %08x %08x %08x\n", i,
- *(int *)&tx_ring[i].txd_info1,
- *(int *)&tx_ring[i].txd_info2,
- *(int *)&tx_ring[i].txd_info3,
- *(int *)&tx_ring[i].txd_info4);
- }
-
- kfree(tx_ring);
- return 0;
-}
-
-static int tx_ring_open(struct inode *inode, struct file *file)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (!(ei_local->features & FE_QDMA)) {
- return single_open(file, tx_ring_read, NULL);
- } else if (ei_local->features & FE_QDMA) {
- if (ei_local->chip_name == MT7622_FE)
- return single_open(file, qdma_read_64queue, NULL);
- else
- return single_open(file, qdma_read, NULL);
- } else {
- return 0;
- }
-}
-
-static const struct file_operations tx_ring_fops = {
- .owner = THIS_MODULE,
- .open = tx_ring_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-int rx_ring_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- struct PDMA_rxdesc *rx_ring;
- int i = 0;
-
- rx_ring = kmalloc_array(num_rx_desc, sizeof(*rx_ring), GFP_KERNEL);
- if (!rx_ring)
- /*seq_puts(seq, " allocate temp rx_ring fail.\n"); */
- return 0;
-
- for (i = 0; i < num_rx_desc; i++) {
- memcpy(&rx_ring[i], &ei_local->rx_ring[0][i],
- sizeof(struct PDMA_rxdesc));
- }
-
- for (i = 0; i < num_rx_desc; i++) {
- seq_printf(seq, "%d: %08x %08x %08x %08x\n", i,
- *(int *)&rx_ring[i].rxd_info1,
- *(int *)&rx_ring[i].rxd_info2,
- *(int *)&rx_ring[i].rxd_info3,
- *(int *)&rx_ring[i].rxd_info4);
- }
-
- kfree(rx_ring);
- return 0;
-}
-
-static int rx_ring_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rx_ring_read, NULL);
-}
-
-static const struct file_operations rx_ring_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-int num_of_txd_update(int num_of_txd)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO)
- txd_cnt[num_of_txd]++;
- return 0;
-}
-
-static void *seq_tso_txd_num_start(struct seq_file *seq, loff_t *pos)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- seq_puts(seq, "TXD | Count\n");
- if (*pos < (MAX_SKB_FRAGS / 2 + 1))
- return pos;
- }
- return NULL;
-}
-
-static void *seq_tso_txd_num_next(struct seq_file *seq, void *v, loff_t *pos)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- (*pos)++;
- if (*pos >= (MAX_SKB_FRAGS / 2 + 1))
- return NULL;
- return pos;
- } else {
- return NULL;
- }
-}
-
-static void seq_tso_txd_num_stop(struct seq_file *seq, void *v)
-{
- /* Nothing to do */
-}
-
-static int seq_tso_txd_num_show(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- int i = *(loff_t *)v;
-
- seq_printf(seq, "%d: %d\n", i, txd_cnt[i]);
- }
- return 0;
-}
-
-ssize_t num_of_txd_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- memset(txd_cnt, 0, sizeof(txd_cnt));
- pr_debug("clear txd cnt table\n");
- return count;
- } else {
- return 0;
- }
-}
-
-int tso_len_update(int tso_len)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- if (tso_len > 70000)
- tso_cnt[14]++;
- else if (tso_len > 65000)
- tso_cnt[13]++;
- else if (tso_len > 60000)
- tso_cnt[12]++;
- else if (tso_len > 55000)
- tso_cnt[11]++;
- else if (tso_len > 50000)
- tso_cnt[10]++;
- else if (tso_len > 45000)
- tso_cnt[9]++;
- else if (tso_len > 40000)
- tso_cnt[8]++;
- else if (tso_len > 35000)
- tso_cnt[7]++;
- else if (tso_len > 30000)
- tso_cnt[6]++;
- else if (tso_len > 25000)
- tso_cnt[5]++;
- else if (tso_len > 20000)
- tso_cnt[4]++;
- else if (tso_len > 15000)
- tso_cnt[3]++;
- else if (tso_len > 10000)
- tso_cnt[2]++;
- else if (tso_len > 5000)
- tso_cnt[1]++;
- else
- tso_cnt[0]++;
- }
- return 0;
-}
-
-ssize_t tso_len_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- memset(tso_cnt, 0, sizeof(tso_cnt));
- pr_debug("clear tso cnt table\n");
- return count;
- } else {
- return 0;
- }
-}
-
-static void *seq_tso_len_start(struct seq_file *seq, loff_t *pos)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- seq_puts(seq, " Length | Count\n");
- if (*pos < 15)
- return pos;
- }
- return NULL;
-}
-
-static void *seq_tso_len_next(struct seq_file *seq, void *v, loff_t *pos)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- (*pos)++;
- if (*pos >= 15)
- return NULL;
- return pos;
- } else {
- return NULL;
- }
-}
-
-static void seq_tso_len_stop(struct seq_file *seq, void *v)
-{
- /* Nothing to do */
-}
-
-static int seq_tso_len_show(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_TSO) {
- int i = *(loff_t *)v;
-
- seq_printf(seq, "%d~%d: %d\n", i * 5000, (i + 1) * 5000,
- tso_cnt[i]);
- }
- return 0;
-}
-
-static const struct seq_operations seq_tso_txd_num_ops = {
- .start = seq_tso_txd_num_start,
- .next = seq_tso_txd_num_next,
- .stop = seq_tso_txd_num_stop,
- .show = seq_tso_txd_num_show
-};
-
-static int tso_txd_num_open(struct inode *inode, struct file *file)
-{
- return seq_open(file, &seq_tso_txd_num_ops);
-}
-
-static const struct file_operations tso_txd_num_fops = {
- .owner = THIS_MODULE,
- .open = tso_txd_num_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = num_of_txd_write,
- .release = seq_release
-};
-
-static const struct seq_operations seq_tso_len_ops = {
- .start = seq_tso_len_start,
- .next = seq_tso_len_next,
- .stop = seq_tso_len_stop,
- .show = seq_tso_len_show
-};
-
-static int tso_len_open(struct inode *inode, struct file *file)
-{
- return seq_open(file, &seq_tso_len_ops);
-}
-
-static const struct file_operations tso_len_fops = {
- .owner = THIS_MODULE,
- .open = tso_len_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = tso_len_write,
- .release = seq_release
-};
-
-static struct proc_dir_entry *proc_esw_cnt;
-static struct proc_dir_entry *proc_eth_cnt;
-
-void internal_gsw_cnt_read(struct seq_file *seq)
-{
- unsigned int pkt_cnt = 0;
- int i = 0;
-
- seq_printf(seq,
- "===================== %8s %8s %8s %8s %8s %8s %8s\n",
- "Port0", "Port1", "Port2", "Port3", "Port4",
- "Port5", "Port6");
- seq_puts(seq, "Tx Drop Packet :");
- DUMP_EACH_PORT(0x4000);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx CRC Error :");
- DUMP_EACH_PORT(0x4004);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx Unicast Packet :");
- DUMP_EACH_PORT(0x4008);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx Multicast Packet :");
- DUMP_EACH_PORT(0x400C);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx Broadcast Packet :");
- DUMP_EACH_PORT(0x4010);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx Collision Event :");
- DUMP_EACH_PORT(0x4014);
- seq_puts(seq, "\n");
- seq_puts(seq, "Tx Pause Packet :");
- DUMP_EACH_PORT(0x402C);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Drop Packet :");
- DUMP_EACH_PORT(0x4060);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Filtering Packet :");
- DUMP_EACH_PORT(0x4064);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Unicast Packet :");
- DUMP_EACH_PORT(0x4068);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Multicast Packet :");
- DUMP_EACH_PORT(0x406C);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Broadcast Packet :");
- DUMP_EACH_PORT(0x4070);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Alignment Error :");
- DUMP_EACH_PORT(0x4074);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx CRC Error :");
- DUMP_EACH_PORT(0x4078);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Undersize Error :");
- DUMP_EACH_PORT(0x407C);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Fragment Error :");
- DUMP_EACH_PORT(0x4080);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Oversize Error :");
- DUMP_EACH_PORT(0x4084);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Jabber Error :");
- DUMP_EACH_PORT(0x4088);
- seq_puts(seq, "\n");
- seq_puts(seq, "Rx Pause Packet :");
- DUMP_EACH_PORT(0x408C);
- mii_mgr_write(31, 0x4fe0, 0xf0);
- mii_mgr_write(31, 0x4fe0, 0x800000f0);
-
- seq_puts(seq, "\n");
-}
-
-void pse_qdma_drop_cnt(void)
-{
- u8 i;
-
- pr_info(" <<PSE DROP CNT>>\n");
- pr_info("| FQ_PCNT_MIN : %010u |\n",
- (sys_reg_read(FE_PSE_FREE) & 0xff0000) >> 16);
- pr_info("| FQ_PCNT : %010u |\n",
- sys_reg_read(FE_PSE_FREE) & 0x00ff);
- pr_info("| FE_DROP_FQ : %010u |\n",
- sys_reg_read(FE_DROP_FQ));
- pr_info("| FE_DROP_FC : %010u |\n",
- sys_reg_read(FE_DROP_FC));
- pr_info("| FE_DROP_PPE : %010u |\n",
- sys_reg_read(FE_DROP_PPE));
- pr_info("\n <<QDMA PKT/DROP CNT>>\n");
-
- sys_reg_write(QTX_MIB_IF, 0x90000000);
- for (i = 0; i < NUM_PQ; i++) {
- if (i <= 15) {
- sys_reg_write(QDMA_PAGE, 0);
- pr_info("QDMA Q%d PKT CNT: %010u, DROP CNT: %010u\n", i,
- sys_reg_read(QTX_CFG_0 + i * 16),
- sys_reg_read(QTX_SCH_0 + i * 16));
- } else if (i > 15 && i <= 31) {
- sys_reg_write(QDMA_PAGE, 1);
- pr_info("QDMA Q%d PKT CNT: %010u, DROP CNT: %010u\n", i,
- sys_reg_read(QTX_CFG_0 + (i - 16) * 16),
- sys_reg_read(QTX_SCH_0 + (i - 16) * 16));
- } else if (i > 31 && i <= 47) {
- sys_reg_write(QDMA_PAGE, 2);
- pr_info("QDMA Q%d PKT CNT: %010u, DROP CNT: %010u\n", i,
- sys_reg_read(QTX_CFG_0 + (i - 32) * 16),
- sys_reg_read(QTX_SCH_0 + (i - 32) * 16));
- } else if (i > 47 && i <= 63) {
- sys_reg_write(QDMA_PAGE, 3);
- pr_info("QDMA Q%d PKT CNT: %010u, DROP CNT: %010u\n", i,
- sys_reg_read(QTX_CFG_0 + (i - 48) * 16),
- sys_reg_read(QTX_SCH_0 + (i - 48) * 16));
- }
- }
- sys_reg_write(QDMA_PAGE, 0);
- sys_reg_write(QTX_MIB_IF, 0x0);
-}
-
-void embedded_sw_cnt_read(struct seq_file *seq)
-{
- seq_puts(seq, "\n <<CPU>>\n");
- seq_puts(seq, " |\n");
- seq_puts(seq, " ^\n");
- seq_printf(seq, " | Port6 Rx:%08u Good Pkt\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xE0) & 0xFFFF);
- seq_printf(seq, " | Port6 Tx:%08u Good Pkt\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xE0) >> 16);
- seq_puts(seq, "+---------------------v-------------------------+\n");
- seq_puts(seq, "| P6 |\n");
- seq_puts(seq, "| <<10/100 Embedded Switch>> |\n");
- seq_puts(seq, "| P0 P1 P2 P3 P4 P5 |\n");
- seq_puts(seq, "+-----------------------------------------------+\n");
- seq_puts(seq, " | | | | | |\n");
- seq_printf(seq,
- "Port0 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xE8) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x150) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xE8) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x150) >> 16);
-
- seq_printf(seq,
- "Port1 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xEC) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x154) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xEC) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x154) >> 16);
-
- seq_printf(seq,
- "Port2 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF0) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x158) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF0) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x158) >> 16);
-
- seq_printf(seq,
- "Port3 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF4) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x15C) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF4) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x15c) >> 16);
-
- seq_printf(seq,
- "Port4 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF8) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x160) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xF8) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x160) >> 16);
-
- seq_printf(seq,
- "Port5 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n",
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xFC) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x164) & 0xFFFF,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0xFC) >> 16,
- sys_reg_read(ETHDMASYS_ETH_SW_BASE + 0x164) >> 16);
-}
-
-int eth_cnt_read(struct seq_file *seq, void *v)
-{
- pse_qdma_drop_cnt();
- return 0;
-}
-
-int esw_cnt_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- seq_puts(seq, " <<CPU>>\n");
- seq_puts(seq, "+-----------------------------------------------+\n");
- seq_puts(seq, "| <<PSE>> |\n");
- seq_puts(seq, "+-----------------------------------------------+\n");
- seq_puts(seq, "+-----------------------------------------------+\n");
- seq_puts(seq, "| <<GDMA>> |\n");
-
- seq_printf(seq,
- "| GDMA1_RX_GBCNT : %010u (Rx Good Bytes) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C00));
- seq_printf(seq,
- "| GDMA1_RX_GPCNT : %010u (Rx Good Pkts) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C08));
- seq_printf(seq,
- "| GDMA1_RX_OERCNT : %010u (overflow error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C10));
- seq_printf(seq, "| GDMA1_RX_FERCNT : %010u (FCS error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C14));
- seq_printf(seq, "| GDMA1_RX_SERCNT : %010u (too short) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C18));
- seq_printf(seq, "| GDMA1_RX_LERCNT : %010u (too long) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C1C));
- seq_printf(seq,
- "| GDMA1_RX_CERCNT : %010u (checksum error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C20));
- seq_printf(seq,
- "| GDMA1_RX_FCCNT : %010u (flow control) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C24));
- seq_printf(seq,
- "| GDMA1_TX_SKIPCNT: %010u (about count) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C28));
- seq_printf(seq,
- "| GDMA1_TX_COLCNT : %010u (collision count) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C2C));
- seq_printf(seq,
- "| GDMA1_TX_GBCNT : %010u (Tx Good Bytes) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C30));
- seq_printf(seq,
- "| GDMA1_TX_GPCNT : %010u (Tx Good Pkts) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C38));
- seq_puts(seq, "| |\n");
- seq_printf(seq,
- "| GDMA2_RX_GBCNT : %010u (Rx Good Bytes) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C40));
- seq_printf(seq,
- "| GDMA2_RX_GPCNT : %010u (Rx Good Pkts) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C48));
- seq_printf(seq,
- "| GDMA2_RX_OERCNT : %010u (overflow error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C50));
- seq_printf(seq, "| GDMA2_RX_FERCNT : %010u (FCS error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C54));
- seq_printf(seq, "| GDMA2_RX_SERCNT : %010u (too short) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C58));
- seq_printf(seq, "| GDMA2_RX_LERCNT : %010u (too long) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C5C));
- seq_printf(seq,
- "| GDMA2_RX_CERCNT : %010u (checksum error) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C60));
- seq_printf(seq,
- "| GDMA2_RX_FCCNT : %010u (flow control) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C64));
- seq_printf(seq,
- "| GDMA2_TX_SKIPCNT: %010u (skip) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C68));
- seq_printf(seq, "| GDMA2_TX_COLCNT : %010u (collision) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C6C));
- seq_printf(seq,
- "| GDMA2_TX_GBCNT : %010u (Tx Good Bytes) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C70));
- seq_printf(seq,
- "| GDMA2_TX_GPCNT : %010u (Tx Good Pkts) |\n",
- sys_reg_read(RALINK_FRAME_ENGINE_BASE + 0x1C78));
-
- seq_puts(seq, "+-----------------------------------------------+\n");
-
- seq_puts(seq, "\n");
-
- if ((ei_local->chip_name == MT7623_FE) || ei_local->chip_name == MT7621_FE)
- internal_gsw_cnt_read(seq);
- if (ei_local->architecture & RAETH_ESW)
- embedded_sw_cnt_read(seq);
-
- return 0;
-}
-
-static int switch_count_open(struct inode *inode, struct file *file)
-{
- return single_open(file, esw_cnt_read, NULL);
-}
-
-static int eth_count_open(struct inode *inode, struct file *file)
-{
- return single_open(file, eth_cnt_read, NULL);
-}
-
-static const struct file_operations switch_count_fops = {
- .owner = THIS_MODULE,
- .open = switch_count_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static const struct file_operations eth_count_fops = {
- .owner = THIS_MODULE,
- .open = eth_count_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-/* proc write procedure */
-static ssize_t change_phyid(struct file *file,
- const char __user *buffer, size_t count,
- loff_t *data)
-{
- int val = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) {
- char buf[32];
- struct net_device *cur_dev_p;
- struct END_DEVICE *ei_local;
- char if_name[64];
- unsigned int phy_id;
-
- if (count > 32)
- count = 32;
- memset(buf, 0, 32);
- if (copy_from_user(buf, buffer, count))
- return -EFAULT;
-
- /* determine interface name */
- strncpy(if_name, DEV_NAME, sizeof(if_name) - 1); /* "eth2" by default */
- if (isalpha(buf[0])) {
- val = sscanf(buf, "%4s %1d", if_name, &phy_id);
- if (val == -1)
- return -EFAULT;
- } else {
- phy_id = kstrtol(buf, 10, NULL);
- }
- cur_dev_p = dev_get_by_name(&init_net, DEV_NAME);
-
- if (!cur_dev_p)
- return -EFAULT;
-
- ei_local = netdev_priv(cur_dev_p);
-
- ei_local->mii_info.phy_id = (unsigned char)phy_id;
- return count;
- } else {
- return 0;
- }
-}
-
-static ssize_t change_gmac2_phyid(struct file *file,
- const char __user *buffer,
- size_t count, loff_t *data)
-{
- int val = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) {
- char buf[32];
- struct net_device *cur_dev_p;
- struct PSEUDO_ADAPTER *p_pseudo_ad;
- char if_name[64];
- unsigned int phy_id;
-
- if (count > 32)
- count = 32;
- memset(buf, 0, 32);
- if (copy_from_user(buf, buffer, count))
- return -EFAULT;
- /* determine interface name */
- strncpy(if_name, DEV2_NAME, sizeof(if_name) - 1); /* "eth3" by default */
- if (isalpha(buf[0])) {
- val = sscanf(buf, "%4s %1d", if_name, &phy_id);
- if (val == -1)
- return -EFAULT;
- } else {
- phy_id = kstrtol(buf, 10, NULL);
- }
- cur_dev_p = dev_get_by_name(&init_net, DEV2_NAME);
-
- if (!cur_dev_p)
- return -EFAULT;
- p_pseudo_ad = netdev_priv(cur_dev_p);
- p_pseudo_ad->mii_info.phy_id = (unsigned char)phy_id;
- return count;
- } else {
- return 0;
- }
-}
-
-static const struct file_operations gmac2_fops = {
- .owner = THIS_MODULE,
- .write = change_gmac2_phyid
-};
-
-static int gmac_open(struct inode *inode, struct file *file)
-{
- return single_open(file, reg_read_main, NULL);
-}
-
-static const struct file_operations gmac_fops = {
- .owner = THIS_MODULE,
- .open = gmac_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = change_phyid,
- .release = single_release
-};
-
-/* #if defined(TASKLET_WORKQUEUE_SW) */
-
-static int schedule_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & TASKLET_WORKQUEUE_SW) {
- if (init_schedule == 1)
- seq_printf(seq,
- "Initialize Raeth with workqueque<%d>\n",
- init_schedule);
- else
- seq_printf(seq,
- "Initialize Raeth with tasklet<%d>\n",
- init_schedule);
- if (working_schedule == 1)
- seq_printf(seq,
- "Raeth is running at workqueque<%d>\n",
- working_schedule);
- else
- seq_printf(seq,
- "Raeth is running at tasklet<%d>\n",
- working_schedule);
- }
-
- return 0;
-}
-
-static ssize_t schedule_write(struct file *file,
- const char __user *buffer, size_t count,
- loff_t *data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & TASKLET_WORKQUEUE_SW) {
- char buf[2];
- int old;
-
- if (copy_from_user(buf, buffer, count))
- return -EFAULT;
- old = init_schedule;
- init_schedule = kstrtol(buf, 10, NULL);
- pr_debug
- ("ChangeRaethInitScheduleFrom <%d> to <%d>\n",
- old, init_schedule);
- pr_debug("Not running schedule at present !\n");
-
- return count;
- } else {
- return 0;
- }
-}
-
-static int schedule_switch_open(struct inode *inode, struct file *file)
-{
- return single_open(file, schedule_read, NULL);
-}
-
-static const struct file_operations schedule_sw_fops = {
- .owner = THIS_MODULE,
- .open = schedule_switch_open,
- .read = seq_read,
- .write = schedule_write,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-int int_stats_update(unsigned int int_status)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_RAETH_INT_DBG) {
- if (int_status & (RX_COHERENT | TX_COHERENT | RXD_ERROR)) {
- if (int_status & RX_COHERENT)
- raeth_int.RX_COHERENT_CNT++;
- if (int_status & TX_COHERENT)
- raeth_int.TX_COHERENT_CNT++;
- if (int_status & RXD_ERROR)
- raeth_int.RXD_ERROR_CNT++;
- }
- if (int_status &
- (RX_DLY_INT | RING1_RX_DLY_INT | RING2_RX_DLY_INT |
- RING3_RX_DLY_INT)) {
- if (int_status & RX_DLY_INT)
- raeth_int.RX_DLY_INT_CNT++;
- if (int_status & RING1_RX_DLY_INT)
- raeth_int.RING1_RX_DLY_INT_CNT++;
- if (int_status & RING2_RX_DLY_INT)
- raeth_int.RING2_RX_DLY_INT_CNT++;
- if (int_status & RING3_RX_DLY_INT)
- raeth_int.RING3_RX_DLY_INT_CNT++;
- }
- if (int_status & (TX_DLY_INT))
- raeth_int.TX_DLY_INT_CNT++;
- if (int_status &
- (RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 |
- RX_DONE_INT3)) {
- if (int_status & RX_DONE_INT0)
- raeth_int.RX_DONE_INT0_CNT++;
- if (int_status & RX_DONE_INT1)
- raeth_int.RX_DONE_INT1_CNT++;
- if (int_status & RX_DONE_INT2)
- raeth_int.RX_DONE_INT2_CNT++;
- if (int_status & RX_DONE_INT3)
- raeth_int.RX_DONE_INT3_CNT++;
- }
- if (int_status &
- (TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 |
- TX_DONE_INT3)) {
- if (int_status & TX_DONE_INT0)
- raeth_int.TX_DONE_INT0_CNT++;
- if (int_status & TX_DONE_INT1)
- raeth_int.TX_DONE_INT1_CNT++;
- if (int_status & TX_DONE_INT2)
- raeth_int.TX_DONE_INT2_CNT++;
- if (int_status & TX_DONE_INT3)
- raeth_int.TX_DONE_INT3_CNT++;
- }
- if (int_status &
- (ALT_RPLC_INT1 | ALT_RPLC_INT2 | ALT_RPLC_INT3)) {
- if (int_status & ALT_RPLC_INT1)
- raeth_int.ALT_RPLC_INT1_CNT++;
- if (int_status & ALT_RPLC_INT2)
- raeth_int.ALT_RPLC_INT2_CNT++;
- if (int_status & ALT_RPLC_INT3)
- raeth_int.ALT_RPLC_INT3_CNT++;
- }
- }
- return 0;
-}
-
-static int int_dbg_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_RAETH_INT_DBG) {
- seq_puts(seq, "Raether Interrupt Statistics\n");
- seq_printf(seq, "RX_COHERENT = %d\n",
- raeth_int.RX_COHERENT_CNT);
- seq_printf(seq, "RX_DLY_INT = %d\n", raeth_int.RX_DLY_INT_CNT);
- seq_printf(seq, "TX_COHERENT = %d\n",
- raeth_int.TX_COHERENT_CNT);
- seq_printf(seq, "TX_DLY_INT = %d\n", raeth_int.TX_DLY_INT_CNT);
- seq_printf(seq, "RING3_RX_DLY_INT = %d\n",
- raeth_int.RING3_RX_DLY_INT_CNT);
- seq_printf(seq, "RING2_RX_DLY_INT = %d\n",
- raeth_int.RING2_RX_DLY_INT_CNT);
- seq_printf(seq, "RING1_RX_DLY_INT = %d\n",
- raeth_int.RING1_RX_DLY_INT_CNT);
- seq_printf(seq, "RXD_ERROR = %d\n", raeth_int.RXD_ERROR_CNT);
- seq_printf(seq, "ALT_RPLC_INT3 = %d\n",
- raeth_int.ALT_RPLC_INT3_CNT);
- seq_printf(seq, "ALT_RPLC_INT2 = %d\n",
- raeth_int.ALT_RPLC_INT2_CNT);
- seq_printf(seq, "ALT_RPLC_INT1 = %d\n",
- raeth_int.ALT_RPLC_INT1_CNT);
- seq_printf(seq, "RX_DONE_INT3 = %d\n",
- raeth_int.RX_DONE_INT3_CNT);
- seq_printf(seq, "RX_DONE_INT2 = %d\n",
- raeth_int.RX_DONE_INT2_CNT);
- seq_printf(seq, "RX_DONE_INT1 = %d\n",
- raeth_int.RX_DONE_INT1_CNT);
- seq_printf(seq, "RX_DONE_INT0 = %d\n",
- raeth_int.RX_DONE_INT0_CNT);
- seq_printf(seq, "TX_DONE_INT3 = %d\n",
- raeth_int.TX_DONE_INT3_CNT);
- seq_printf(seq, "TX_DONE_INT2 = %d\n",
- raeth_int.TX_DONE_INT2_CNT);
- seq_printf(seq, "TX_DONE_INT1 = %d\n",
- raeth_int.TX_DONE_INT1_CNT);
- seq_printf(seq, "TX_DONE_INT0 = %d\n",
- raeth_int.TX_DONE_INT0_CNT);
-
- memset(&raeth_int, 0, sizeof(raeth_int));
- }
- return 0;
-}
-
-static int int_dbg_open(struct inode *inode, struct file *file)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_RAETH_INT_DBG) {
- /* memset(&raeth_int, 0, sizeof(raeth_int)); */
- return single_open(file, int_dbg_read, NULL);
- } else {
- return 0;
- }
-}
-
-static ssize_t int_dbg_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *data)
-{
- return 0;
-}
-
-static const struct file_operations int_dbg_sw_fops = {
- .owner = THIS_MODULE,
- .open = int_dbg_open,
- .read = seq_read,
- .write = int_dbg_write
-};
-
-static int set_lan_ip_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- seq_printf(seq, "ei_local->lan_ip4_addr = %s\n",
- ei_local->lan_ip4_addr);
-
- return 0;
-}
-
-static int set_lan_ip_open(struct inode *inode, struct file *file)
-{
- return single_open(file, set_lan_ip_read, NULL);
-}
-
-static ssize_t set_lan_ip_write(struct file *file,
- const char __user *buffer, size_t count,
- loff_t *data)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- char ip_tmp[IP4_ADDR_LEN];
-
- if (count > IP4_ADDR_LEN)
- return -EFAULT;
-
- if (copy_from_user(ip_tmp, buffer, count))
- return -EFAULT;
-
- strncpy(ei_local->lan_ip4_addr, ip_tmp, count);
-
- pr_info("[%s]LAN IP = %s\n", __func__, ei_local->lan_ip4_addr);
-
-
- if (ei_local->features & FE_HW_LRO)
- fe_set_hw_lro_my_ip(ei_local->lan_ip4_addr);
-
- return count;
-}
-
-static const struct file_operations set_lan_ip_fops = {
- .owner = THIS_MODULE,
- .open = set_lan_ip_open,
- .read = seq_read,
- .write = set_lan_ip_write
-};
-
-int debug_proc_init(void)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (!proc_reg_dir)
- proc_reg_dir = proc_mkdir(PROCREG_DIR, NULL);
-
- if (ei_local->features & FE_HW_LRO)
- hwlro_debug_proc_init(proc_reg_dir);
- else if (ei_local->features & (FE_RSS_4RING | FE_RSS_2RING))
- rss_debug_proc_init(proc_reg_dir);
-
- if (ei_local->features & FE_HW_IOCOHERENT)
- hwioc_debug_proc_init(proc_reg_dir);
- proc_gmac = proc_create(PROCREG_GMAC, 0, proc_reg_dir, &gmac_fops);
- if (!proc_gmac)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_GMAC);
-
- if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) {
- proc_gmac2 =
- proc_create(PROCREG_GMAC2, 0, proc_reg_dir, &gmac2_fops);
- if (!proc_gmac2)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_GMAC2);
- }
- proc_skb_free =
- proc_create(PROCREG_SKBFREE, 0, proc_reg_dir, &skb_free_fops);
- if (!proc_skb_free)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_SKBFREE);
- proc_tx_ring = proc_create(PROCREG_TXRING, 0, proc_reg_dir,
- &tx_ring_fops);
- if (!proc_tx_ring)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_TXRING);
- proc_rx_ring = proc_create(PROCREG_RXRING, 0,
- proc_reg_dir, &rx_ring_fops);
- if (!proc_rx_ring)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_RXRING);
-
- if (ei_local->features & FE_TSO) {
- proc_num_of_txd =
- proc_create(PROCREG_NUM_OF_TXD, 0, proc_reg_dir,
- &tso_txd_num_fops);
- if (!proc_num_of_txd)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_NUM_OF_TXD);
- proc_tso_len =
- proc_create(PROCREG_TSO_LEN, 0, proc_reg_dir,
- &tso_len_fops);
- if (!proc_tso_len)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_TSO_LEN);
- }
-
- if (ei_local->features & USER_SNMPD) {
- proc_ra_snmp =
- proc_create(PROCREG_SNMP, S_IRUGO, proc_reg_dir,
- &ra_snmp_seq_fops);
- if (!proc_ra_snmp)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_SNMP);
- }
- proc_esw_cnt =
- proc_create(PROCREG_ESW_CNT, 0, proc_reg_dir, &switch_count_fops);
- if (!proc_esw_cnt)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_ESW_CNT);
-
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- proc_eth_cnt =
- proc_create(PROCREG_ETH_CNT, 0, proc_reg_dir, ð_count_fops);
- if (!proc_eth_cnt)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_ETH_CNT);
- }
-
- if (ei_local->features & TASKLET_WORKQUEUE_SW) {
- proc_sche =
- proc_create(PROCREG_SCHE, 0, proc_reg_dir,
- &schedule_sw_fops);
- if (!proc_sche)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_SCHE);
- }
-
- if (ei_local->features & FE_RAETH_INT_DBG) {
- proc_int_dbg =
- proc_create(PROCREG_INT_DBG, 0, proc_reg_dir,
- &int_dbg_sw_fops);
- if (!proc_int_dbg)
- pr_debug("!! FAIL to create %s PROC !!\n",
- PROCREG_INT_DBG);
- }
-
- /* Set LAN IP address */
- proc_set_lan_ip =
- proc_create(PROCREG_SET_LAN_IP, 0, proc_reg_dir, &set_lan_ip_fops);
- if (!proc_set_lan_ip)
- pr_debug("!! FAIL to create %s PROC !!\n", PROCREG_SET_LAN_IP);
-
- pr_debug("PROC INIT OK!\n");
- return 0;
-}
-
-void debug_proc_exit(void)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_HW_LRO)
- hwlro_debug_proc_exit(proc_reg_dir);
- else if (ei_local->features & (FE_RSS_4RING | FE_RSS_2RING))
- rss_debug_proc_exit(proc_reg_dir);
-
- if (ei_local->features & FE_HW_IOCOHERENT)
- hwioc_debug_proc_exit(proc_reg_dir);
-
- if (proc_sys_cp0)
- remove_proc_entry(PROCREG_CP0, proc_reg_dir);
-
- if (proc_gmac)
- remove_proc_entry(PROCREG_GMAC, proc_reg_dir);
-
- if (ei_local->features & (FE_ETHTOOL | FE_GE2_SUPPORT)) {
- if (proc_gmac)
- remove_proc_entry(PROCREG_GMAC, proc_reg_dir);
- }
-
- if (proc_skb_free)
- remove_proc_entry(PROCREG_SKBFREE, proc_reg_dir);
-
- if (proc_tx_ring)
- remove_proc_entry(PROCREG_TXRING, proc_reg_dir);
-
- if (proc_rx_ring)
- remove_proc_entry(PROCREG_RXRING, proc_reg_dir);
-
- if (ei_local->features & FE_TSO) {
- if (proc_num_of_txd)
- remove_proc_entry(PROCREG_NUM_OF_TXD, proc_reg_dir);
-
- if (proc_tso_len)
- remove_proc_entry(PROCREG_TSO_LEN, proc_reg_dir);
- }
-
- if (ei_local->features & USER_SNMPD) {
- if (proc_ra_snmp)
- remove_proc_entry(PROCREG_SNMP, proc_reg_dir);
- }
-
- if (proc_esw_cnt)
- remove_proc_entry(PROCREG_ESW_CNT, proc_reg_dir);
-
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- if (proc_eth_cnt)
- remove_proc_entry(PROCREG_ETH_CNT, proc_reg_dir);
- }
-
- /* if (proc_reg_dir) */
- /* remove_proc_entry(PROCREG_DIR, 0); */
-
- pr_debug("proc exit\n");
-}
-EXPORT_SYMBOL(proc_reg_dir);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.h
deleted file mode 100644
index 8acb29e..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_dbg_proc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_DBG_PROC_H
-#define RA_DBG_PROC_H
-
-#include <linux/ctype.h>
-#include <linux/proc_fs.h>
-#include "raeth_config.h"
-
-extern struct net_device *dev_raether;
-
-void dump_qos(void);
-void dump_reg(struct seq_file *s);
-void dump_cp0(void);
-
-int debug_proc_init(void);
-void debug_proc_exit(void);
-
-int tso_len_update(int tso_len);
-int num_of_txd_update(int num_of_txd);
-#ifdef CONFIG_RAETH_LRO
-int lro_stats_update(struct net_lro_mgr *lro_mgr, bool all_flushed);
-#endif
-extern unsigned int M2Q_table[64];
-extern struct QDMA_txdesc *free_head;
-extern struct SFQ_table *sfq0;
-extern struct SFQ_table *sfq1;
-extern struct SFQ_table *sfq2;
-extern struct SFQ_table *sfq3;
-extern int init_schedule;
-extern int working_schedule;
-struct raeth_int_t {
- unsigned int RX_COHERENT_CNT;
- unsigned int RX_DLY_INT_CNT;
- unsigned int TX_COHERENT_CNT;
- unsigned int TX_DLY_INT_CNT;
- unsigned int RING3_RX_DLY_INT_CNT;
- unsigned int RING2_RX_DLY_INT_CNT;
- unsigned int RING1_RX_DLY_INT_CNT;
- unsigned int RXD_ERROR_CNT;
- unsigned int ALT_RPLC_INT3_CNT;
- unsigned int ALT_RPLC_INT2_CNT;
- unsigned int ALT_RPLC_INT1_CNT;
- unsigned int RX_DONE_INT3_CNT;
- unsigned int RX_DONE_INT2_CNT;
- unsigned int RX_DONE_INT1_CNT;
- unsigned int RX_DONE_INT0_CNT;
- unsigned int TX_DONE_INT3_CNT;
- unsigned int TX_DONE_INT2_CNT;
- unsigned int TX_DONE_INT1_CNT;
- unsigned int TX_DONE_INT0_CNT;
-};
-
-int int_stats_update(unsigned int int_status);
-
-#define DUMP_EACH_PORT(base) \
- for (i = 0; i < 7; i++) { \
- mii_mgr_read(31, (base) + (i * 0x100), &pkt_cnt); \
- seq_printf(seq, "%8u ", pkt_cnt); \
- } \
-
-/* HW LRO functions */
-int hwlro_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
-void hwlro_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
-
-int rss_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
-void rss_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
-
-/* HW IO-Coherent functions */
-#ifdef CONFIG_RAETH_HW_IOCOHERENT
-void hwioc_debug_proc_init(struct proc_dir_entry *proc_reg_dir);
-void hwioc_debug_proc_exit(struct proc_dir_entry *proc_reg_dir);
-#else
-static inline void hwioc_debug_proc_init(struct proc_dir_entry *proc_reg_dir)
-{
-}
-
-static inline void hwioc_debug_proc_exit(struct proc_dir_entry *proc_reg_dir)
-{
-}
-#endif /* CONFIG_RAETH_HW_IOCOHERENT */
-
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.c
deleted file mode 100644
index 9ff7e0e..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "ra_ethtool.h"
-
-#define RAETHER_DRIVER_NAME "raether"
-#define RA_NUM_STATS 4
-
-unsigned char get_current_phy_address(void)
-{
- struct net_device *cur_dev_p;
- struct END_DEVICE *ei_local;
-
- cur_dev_p = dev_get_by_name(&init_net, DEV_NAME);
- if (!cur_dev_p)
- return 0;
- ei_local = netdev_priv(cur_dev_p);
- return ei_local->mii_info.phy_id;
-}
-
-#define MII_CR_ADDR 0x00
-#define MII_CR_MR_AUTONEG_ENABLE BIT(12)
-#define MII_CR_MR_RESTART_NEGOTIATION BIT(9)
-
-#define AUTO_NEGOTIATION_ADVERTISEMENT 0x04
-#define AN_PAUSE BIT(10)
-
-u32 et_get_link(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- return mii_link_ok(&ei_local->mii_info);
-}
-
-int et_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- mii_ethtool_gset(&ei_local->mii_info, cmd);
- return 0;
-}
-
-/* mii_mgr_read wrapper for mii.o ethtool */
-int mdio_read(struct net_device *dev, int phy_id, int location)
-{
- unsigned int result;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- mii_mgr_read((unsigned int)ei_local->mii_info.phy_id,
- (unsigned int)location, &result);
-/* printk("\n%s mii.o query= phy_id:%d\n",dev->name, phy_id);*/
-/*printk("address:%d retval:%x\n", location, result); */
- return (int)result;
-}
-
-/* mii_mgr_write wrapper for mii.o ethtool */
-void mdio_write(struct net_device *dev, int phy_id, int location, int value)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- mii_mgr_write((unsigned int)ei_local->mii_info.phy_id,
- (unsigned int)location, (unsigned int)value);
-/* printk("mii.o write= phy_id:%d\n", phy_id);*/
-/*printk("address:%d value:%x\n", location, value); */
-}
-
-/* #ifdef CONFIG_PSEUDO_SUPPORT */
-/*We unable to re-use the Raether functions because it is hard to tell
- * where the calling from is. From eth2 or eth3?
- *
- * These code size is around 950 bytes.
- */
-
-u32 et_virt_get_link(struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev);
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_GE2_SUPPORT)
- return mii_link_ok(&pseudo->mii_info);
- else
- return 0;
-}
-
-int et_virt_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
- struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev);
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_GE2_SUPPORT)
- mii_ethtool_gset(&pseudo->mii_info, cmd);
- return 0;
-}
-
-int mdio_virt_read(struct net_device *dev, int phy_id, int location)
-{
- unsigned int result;
- struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev);
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- mii_mgr_read((unsigned int)pseudo->mii_info.phy_id,
- (unsigned int)location, &result);
-/* printk("%s mii.o query= phy_id:%d,\n", dev->name, phy_id); */
-/*printk("address:%d retval:%d\n", location, result);*/
- return (int)result;
- } else {
- return 0;
- }
-}
-
-void mdio_virt_write(struct net_device *dev, int phy_id, int location,
- int value)
-{
- struct PSEUDO_ADAPTER *pseudo = netdev_priv(dev);
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- mii_mgr_write((unsigned int)pseudo->mii_info.phy_id,
- (unsigned int)location, (unsigned int)value);
- }
-
-/* printk("mii.o write= phy_id:%d\n", phy_id);*/
-/*printk("address:%d value:%d\n)", location, value); */
-}
-
-void ethtool_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- /* init mii structure */
- ei_local->mii_info.dev = dev;
- ei_local->mii_info.mdio_read = mdio_read;
- ei_local->mii_info.mdio_write = mdio_write;
- ei_local->mii_info.phy_id_mask = 0x1f;
- ei_local->mii_info.reg_num_mask = 0x1f;
- ei_local->mii_info.supports_gmii =
- mii_check_gmii_support(&ei_local->mii_info);
-
- /* TODO: phy_id: 0~4 */
- ei_local->mii_info.phy_id = 1;
-}
-
-void ethtool_virt_init(struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev);
-
- /* init mii structure */
- p_pseudo_ad->mii_info.dev = dev;
- p_pseudo_ad->mii_info.mdio_read = mdio_virt_read;
- p_pseudo_ad->mii_info.mdio_write = mdio_virt_write;
- p_pseudo_ad->mii_info.phy_id_mask = 0x1f;
- p_pseudo_ad->mii_info.reg_num_mask = 0x1f;
- p_pseudo_ad->mii_info.phy_id = 0x1e;
- p_pseudo_ad->mii_info.supports_gmii =
- mii_check_gmii_support(&p_pseudo_ad->mii_info);
-}
-
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.h
deleted file mode 100644
index cff52e2..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ethtool.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_ETHTOOL_H
-#define RA_ETHTOOL_H
-
-extern struct net_device *dev_raether;
-
-/* ethtool related */
-void ethtool_init(struct net_device *dev);
-int et_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
-u32 et_get_link(struct net_device *dev);
-unsigned char get_current_phy_address(void);
-int mdio_read(struct net_device *dev, int phy_id, int location);
-void mdio_write(struct net_device *dev, int phy_id, int location, int value);
-
-/* for pseudo interface */
-void ethtool_virt_init(struct net_device *dev);
-int et_virt_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
-u32 et_virt_get_link(struct net_device *dev);
-int mdio_virt_read(struct net_device *dev, int phy_id, int location);
-void mdio_virt_write(struct net_device *dev, int phy_id, int location,
- int value);
-
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ioctl.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ioctl.h
deleted file mode 100644
index b94cb33..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_ioctl.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _RAETH_IOCTL_H
-#define _RAETH_IOCTL_H
-
-/* ioctl commands */
-#define RAETH_SW_IOCTL 0x89F0
-#define RAETH_ESW_REG_READ 0x89F1
-#define RAETH_ESW_REG_WRITE 0x89F2
-#define RAETH_MII_READ 0x89F3
-#define RAETH_MII_WRITE 0x89F4
-#define RAETH_ESW_INGRESS_RATE 0x89F5
-#define RAETH_ESW_EGRESS_RATE 0x89F6
-#define RAETH_ESW_PHY_DUMP 0x89F7
-#define RAETH_QDMA_IOCTL 0x89F8
-#define RAETH_EPHY_IOCTL 0x89F9
-#define RAETH_MII_READ_CL45 0x89FC
-#define RAETH_MII_WRITE_CL45 0x89FD
-#define RAETH_QDMA_SFQ_WEB_ENABLE 0x89FE
-#define RAETH_SET_LAN_IP 0x89FF
-
-/* switch ioctl commands */
-#define SW_IOCTL_SET_EGRESS_RATE 0x0000
-#define SW_IOCTL_SET_INGRESS_RATE 0x0001
-#define SW_IOCTL_SET_VLAN 0x0002
-#define SW_IOCTL_DUMP_VLAN 0x0003
-#define SW_IOCTL_DUMP_TABLE 0x0004
-#define SW_IOCTL_ADD_L2_ADDR 0x0005
-#define SW_IOCTL_DEL_L2_ADDR 0x0006
-#define SW_IOCTL_ADD_MCAST_ADDR 0x0007
-#define SW_IOCTL_DEL_MCAST_ADDR 0x0008
-#define SW_IOCTL_DUMP_MIB 0x0009
-#define SW_IOCTL_ENABLE_IGMPSNOOP 0x000A
-#define SW_IOCTL_DISABLE_IGMPSNOOP 0x000B
-#define SW_IOCTL_SET_PORT_TRUNK 0x000C
-#define SW_IOCTL_GET_PORT_TRUNK 0x000D
-#define SW_IOCTL_SET_PORT_MIRROR 0x000E
-#define SW_IOCTL_GET_PHY_STATUS 0x000F
-#define SW_IOCTL_READ_REG 0x0010
-#define SW_IOCTL_WRITE_REG 0x0011
-#define SW_IOCTL_QOS_EN 0x0012
-#define SW_IOCTL_QOS_SET_TABLE2TYPE 0x0013
-#define SW_IOCTL_QOS_GET_TABLE2TYPE 0x0014
-#define SW_IOCTL_QOS_SET_PORT2TABLE 0x0015
-#define SW_IOCTL_QOS_GET_PORT2TABLE 0x0016
-#define SW_IOCTL_QOS_SET_PORT2PRI 0x0017
-#define SW_IOCTL_QOS_GET_PORT2PRI 0x0018
-#define SW_IOCTL_QOS_SET_DSCP2PRI 0x0019
-#define SW_IOCTL_QOS_GET_DSCP2PRI 0x001a
-#define SW_IOCTL_QOS_SET_PRI2QUEUE 0x001b
-#define SW_IOCTL_QOS_GET_PRI2QUEUE 0x001c
-#define SW_IOCTL_QOS_SET_QUEUE_WEIGHT 0x001d
-#define SW_IOCTL_QOS_GET_QUEUE_WEIGHT 0x001e
-#define SW_IOCTL_SET_PHY_TEST_MODE 0x001f
-#define SW_IOCTL_GET_PHY_REG 0x0020
-#define SW_IOCTL_SET_PHY_REG 0x0021
-#define SW_IOCTL_VLAN_TAG 0x0022
-#define SW_IOCTL_CLEAR_TABLE 0x0023
-#define SW_IOCTL_CLEAR_VLAN 0x0024
-#define SW_IOCTL_SET_VLAN_MODE 0x0025
-
-/*****************QDMA IOCTL DATA*************/
-#define RAETH_QDMA_REG_READ 0x0000
-#define RAETH_QDMA_REG_WRITE 0x0001
-#define RAETH_QDMA_QUEUE_MAPPING 0x0002
-#define RAETH_QDMA_READ_CPU_CLK 0x0003
-/*********************************************/
-/******************EPHY IOCTL DATA************/
-/*MT7622 10/100 phy cal*/
-#define RAETH_VBG_IEXT_CALIBRATION 0x0000
-#define RAETH_TXG_R50_CALIBRATION 0x0001
-#define RAETH_TXG_OFFSET_CALIBRATION 0x0002
-#define RAETH_TXG_AMP_CALIBRATION 0x0003
-#define GE_TXG_R50_CALIBRATION 0x0004
-#define GE_TXG_OFFSET_CALIBRATION 0x0005
-#define GE_TXG_AMP_CALIBRATION 0x0006
-/*********************************************/
-#define REG_ESW_WT_MAC_MFC 0x10
-#define REG_ESW_ISC 0x18
-#define REG_ESW_WT_MAC_ATA1 0x74
-#define REG_ESW_WT_MAC_ATA2 0x78
-#define REG_ESW_WT_MAC_ATWD 0x7C
-#define REG_ESW_WT_MAC_ATC 0x80
-
-#define REG_ESW_TABLE_TSRA1 0x84
-#define REG_ESW_TABLE_TSRA2 0x88
-#define REG_ESW_TABLE_ATRD 0x8C
-
-#define REG_ESW_VLAN_VTCR 0x90
-#define REG_ESW_VLAN_VAWD1 0x94
-#define REG_ESW_VLAN_VAWD2 0x98
-
-#if defined(CONFIG_MACH_MT7623)
-#define REG_ESW_VLAN_ID_BASE 0x100
-#else
-#define REG_ESW_VLAN_ID_BASE 0x50
-#endif
-#define REG_ESW_VLAN_MEMB_BASE 0x70
-#define REG_ESW_TABLE_SEARCH 0x24
-#define REG_ESW_TABLE_STATUS0 0x28
-#define REG_ESW_TABLE_STATUS1 0x2C
-#define REG_ESW_TABLE_STATUS2 0x30
-#define REG_ESW_WT_MAC_AD0 0x34
-#define REG_ESW_WT_MAC_AD1 0x38
-#define REG_ESW_WT_MAC_AD2 0x3C
-
-#if defined(CONFIG_MACH_MT7623)
-#define REG_ESW_MAX 0xFC
-#else
-#define REG_ESW_MAX 0x16C
-#endif
-#define REG_HQOS_MAX 0x3FFF
-
-struct esw_reg {
- unsigned int off;
- unsigned int val;
-};
-
-struct ra_mii_ioctl_data {
- __u32 phy_id;
- __u32 reg_num;
- __u32 val_in;
- __u32 val_out;
- __u32 port_num;
- __u32 dev_addr;
- __u32 reg_addr;
-};
-
-struct ra_switch_ioctl_data {
- unsigned int cmd;
- unsigned int on_off;
- unsigned int port;
- unsigned int bw;
- unsigned int vid;
- unsigned int fid;
- unsigned int port_map;
- unsigned int rx_port_map;
- unsigned int tx_port_map;
- unsigned int igmp_query_interval;
- unsigned int reg_addr;
- unsigned int reg_val;
- unsigned int mode;
- unsigned int qos_queue_num;
- unsigned int qos_type;
- unsigned int qos_pri;
- unsigned int qos_dscp;
- unsigned int qos_table_idx;
- unsigned int qos_weight;
- unsigned char mac[6];
-};
-
-struct qdma_ioctl_data {
- unsigned int cmd;
- unsigned int off;
- unsigned int val;
-};
-
-struct ephy_ioctl_data {
- unsigned int cmd;
-};
-
-struct esw_rate {
- unsigned int on_off;
- unsigned int port;
- unsigned int bw; /*Mbps */
-};
-#endif /* _RAETH_IOCTL_H */
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.c
deleted file mode 100644
index ad822bb..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-
-void enable_auto_negotiate(struct END_DEVICE *ei_local)
-{
- u32 reg_value;
- pr_info("=================================\n");
- pr_info("enable_auto_negotiate\n");
-
- /* FIXME: we don't know how to deal with PHY end addr */
- reg_value = sys_reg_read(ESW_PHY_POLLING);
- reg_value |= (1 << 31);
- reg_value &= ~(0x1f);
- reg_value &= ~(0x1f << 8);
-
- if (ei_local->architecture & (GE2_RGMII_AN | GE2_SGMII_AN)) {
- /* setup PHY address for auto polling (Start Addr). */
- /*avoid end phy address = 0 */
- reg_value |= ((mac_to_gigaphy_mode_addr2 - 1) & 0x1f);
- /* setup PHY address for auto polling (End Addr). */
- reg_value |= (mac_to_gigaphy_mode_addr2 << 8);
- } else if (ei_local->architecture & (GE1_RGMII_AN | GE1_SGMII_AN | LEOPARD_EPHY)) {
- /* setup PHY address for auto polling (Start Addr). */
- reg_value |= (mac_to_gigaphy_mode_addr << 0);
- /* setup PHY address for auto polling (End Addr). */
- reg_value |= ((mac_to_gigaphy_mode_addr + 1) << 8);
- }
-
- sys_reg_write(ESW_PHY_POLLING, reg_value);
-}
-
-void ra2880stop(struct END_DEVICE *ei_local)
-{
- unsigned int reg_value;
-
- pr_info("ra2880stop()...");
-
- reg_value = sys_reg_read(DMA_GLO_CFG);
- reg_value &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
- sys_reg_write(DMA_GLO_CFG, reg_value);
-
- pr_info("Done\n");
-}
-
-void set_mac_address(unsigned char p[6])
-{
- unsigned long reg_value;
-
- reg_value = (p[0] << 8) | (p[1]);
- sys_reg_write(GDMA1_MAC_ADRH, reg_value);
-
- reg_value = (unsigned long)((p[2] << 24) | (p[3] << 16) | (p[4] << 8) | p[5]);
- sys_reg_write(GDMA1_MAC_ADRL, reg_value);
-}
-
-void set_mac2_address(unsigned char p[6])
-{
- unsigned long reg_value;
-
- reg_value = (p[0] << 8) | (p[1]);
- sys_reg_write(GDMA2_MAC_ADRH, reg_value);
-
- reg_value = (unsigned long)((p[2] << 24) | (p[3] << 16) | (p[4] << 8) | p[5]);
- sys_reg_write(GDMA2_MAC_ADRL, reg_value);
-}
-
-static int getnext(const char *src, int separator, char *dest)
-{
- char *c;
- int len;
-
- if (!src || !dest)
- return -1;
-
- c = strchr(src, separator);
- if (!c) {
- strcpy(dest, src);
- return -1;
- }
- len = c - src;
- strncpy(dest, src, len);
- dest[len] = '\0';
- return len + 1;
-}
-
-int str_to_ip(unsigned int *ip, const char *str)
-{
- int len;
- const char *ptr = str;
- char buf[128];
- unsigned char c[4];
- int i;
- int ret;
-
- for (i = 0; i < 3; ++i) {
- len = getnext(ptr, '.', buf);
- if (len == -1)
- return 1; /* parse error */
-
- ret = kstrtoul(buf, 10, (unsigned long *)&c[i]);
- if (ret)
- return ret;
-
- ptr += len;
- }
- ret = kstrtoul(ptr, 0, (unsigned long *)&c[3]);
- if (ret)
- return ret;
-
- *ip = (c[0] << 24) + (c[1] << 16) + (c[2] << 8) + c[3];
-
- return 0;
-}
-
-void set_ge1_force_1000(void)
-{
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x100, 0x2105e33b);
-}
-
-void set_ge2_force_1000(void)
-{
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x200, 0x2105e33b);
-}
-
-void set_ge1_an(void)
-{
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x100, 0x21056300);
-}
-
-void set_ge2_an(void)
-{
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x200, 0x21056300);
-}
-
-void set_ge2_gmii(void)
-{
- void __iomem *virt_addr;
- unsigned int reg_value;
-
- virt_addr = ioremap(ETHSYS_BASE, 0x20);
- reg_value = sys_reg_read(virt_addr + 0x14);
- /*[15:14] =0 RGMII, [8] = 0 SGMII disable*/
- reg_value = reg_value & (~0xc100);
- reg_value = reg_value | 0x4000;
- sys_reg_write(virt_addr + 0x14, reg_value);
- iounmap(virt_addr);
-}
-
-void set_ge0_gmii(void)
-{
- void __iomem *virt_addr;
- unsigned int reg_value;
-
- virt_addr = ioremap(ETHSYS_BASE, 0x20);
- reg_value = sys_reg_read(virt_addr + 0x14);
- /*[15:14] =0 RGMII, [8] = 0 SGMII disable*/
- reg_value = reg_value & (~0xc000);
- reg_value = reg_value | 0x400;
- sys_reg_write(virt_addr + 0x14, reg_value);
- iounmap(virt_addr);
-}
-
-void set_ge2_force_link_down(void)
-{
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x200, 0x2105e300);
-}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.h
deleted file mode 100644
index c329703..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_mac.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_MAC_H
-#define RA_MAC_H
-
-void ra2880stop(struct END_DEVICE *ei_local);
-void set_mac_address(unsigned char p[6]);
-void set_mac2_address(unsigned char p[6]);
-int str_to_ip(unsigned int *ip, const char *str);
-void enable_auto_negotiate(struct END_DEVICE *ei_local);
-void set_ge1_force_1000(void);
-void set_ge2_force_1000(void);
-void set_ge1_an(void);
-void set_ge2_an(void);
-void set_ge2_gmii(void);
-void set_ge0_gmii(void);
-void set_ge2_force_link_down(void);
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.c
deleted file mode 100644
index cee06b6..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.c
+++ /dev/null
@@ -1,4249 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "ra_switch.h"
-#include "ra_mac.h"
-#include "raeth_reg.h"
-
-#define MT7622_CHIP_ID 0x08000008
-
-void reg_bit_zero(void __iomem *addr, unsigned int bit, unsigned int len)
-{
- int reg_val;
- int i;
-
- reg_val = sys_reg_read(addr);
- for (i = 0; i < len; i++)
- reg_val &= ~(1 << (bit + i));
- sys_reg_write(addr, reg_val);
-}
-
-void reg_bit_one(void __iomem *addr, unsigned int bit, unsigned int len)
-{
- unsigned int reg_val;
- unsigned int i;
-
- reg_val = sys_reg_read(addr);
- for (i = 0; i < len; i++)
- reg_val |= 1 << (bit + i);
- sys_reg_write(addr, reg_val);
-}
-
-u8 fe_cal_flag;
-u8 fe_cal_flag_mdix;
-u8 fe_cal_tx_offset_flag;
-u8 fe_cal_tx_offset_flag_mdix;
-u8 fe_cal_r50_flag;
-u8 fe_cal_vbg_flag;
-u32 iext_cal_result;
-u32 r50_p0_cal_result;
-u8 ge_cal_r50_raeth_flag;
-u8 ge_cal_tx_offset_raeth_flag;
-u8 ge_cal_flag_raeth;
-int show_time;
-static u8 ephy_addr_base;
-
-/* 50ohm_new*/
-const u8 ZCAL_TO_R50OHM_TBL_100[64] = {
- 127, 121, 116, 115, 111, 109, 108, 104,
- 102, 99, 97, 96, 77, 76, 73, 72,
- 70, 69, 67, 66, 47, 46, 45, 43,
- 42, 41, 40, 38, 37, 36, 35, 34,
- 32, 16, 15, 14, 13, 12, 11, 10,
- 9, 8, 7, 6, 6, 5, 4, 4,
- 3, 2, 2, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-const u8 ZCAL_TO_R50ohm_GE_TBL_100[64] = {
- 63, 63, 63, 63, 63, 63, 63, 63,
- 63, 63, 63, 63, 63, 63, 63, 60,
- 57, 55, 53, 51, 48, 46, 44, 42,
- 40, 38, 37, 36, 34, 32, 30, 28,
- 27, 26, 25, 23, 22, 21, 19, 18,
- 16, 15, 14, 13, 12, 11, 10, 9,
- 8, 7, 6, 5, 4, 4, 3, 2,
- 1, 0, 0, 0, 0, 0, 0, 0
-};
-
-const u8 ZCAL_TO_R50ohm_GE_TBL[64] = {
- 63, 63, 63, 63, 63, 63, 63, 63,
- 63, 63, 63, 63, 63, 63, 63, 60,
- 57, 55, 53, 51, 48, 46, 44, 42,
- 40, 38, 37, 36, 34, 32, 30, 28,
- 27, 26, 25, 23, 22, 21, 19, 18,
- 16, 15, 14, 13, 12, 11, 10, 9,
- 8, 7, 6, 5, 4, 4, 3, 2,
- 1, 0, 0, 0, 0, 0, 0, 0
-};
-
-const u8 ZCAL_TO_REXT_TBL[64] = {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 1,
- 1, 2, 2, 2, 2, 2, 2, 3,
- 3, 3, 3, 3, 3, 4, 4, 4,
- 4, 4, 4, 4, 5, 5, 5, 5,
- 5, 5, 6, 6, 6, 6, 6, 6,
- 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7
-};
-
-const u8 ZCAL_TO_FILTER_TBL[64] = {
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 1,
- 1, 2, 2, 2, 3, 3, 3, 4,
- 4, 4, 4, 5, 5, 5, 6, 6,
- 7, 7, 7, 8, 8, 8, 9, 9,
- 9, 10, 10, 10, 11, 11, 11, 11,
- 12, 12, 12, 12, 12, 12, 12, 12
-};
-
-void tc_phy_write_g_reg(u8 port_num, u8 page_num,
- u8 reg_num, u32 reg_data)
-{
- u32 r31 = 0;
-
- r31 |= 0 << 15; /* global */
- r31 |= ((page_num & 0x7) << 12); /* page no */
- mii_mgr_write(port_num, 31, r31); /* change Global page */
- mii_mgr_write(port_num, reg_num, reg_data);
-}
-
-void tc_phy_write_l_reg(u8 port_no, u8 page_no,
- u8 reg_num, u32 reg_data)
-{
- u32 r31 = 0;
-
- r31 |= 1 << 15; /* local */
- r31 |= ((page_no & 0x7) << 12); /* page no */
- mii_mgr_write(port_no, 31, r31); /* select local page x */
- mii_mgr_write(port_no, reg_num, reg_data);
-}
-
-u32 tc_phy_read_g_reg(u8 port_num, u8 page_num, u8 reg_num)
-{
- u32 phy_val;
-
- u32 r31 = 0;
-
- r31 |= 0 << 15; /* global */
- r31 |= ((page_num & 0x7) << 12); /* page no */
- mii_mgr_write(port_num, 31, r31); /* change Global page */
- mii_mgr_read(port_num, reg_num, &phy_val);
- return phy_val;
-}
-
-u32 tc_phy_read_l_reg(u8 port_no, u8 page_no, u8 reg_num)
-{
- u32 phy_val;
- u32 r31 = 0;
-
- r31 |= 1 << 15; /* local */
- r31 |= ((page_no & 0x7) << 12); /* page no */
- mii_mgr_write(port_no, 31, r31); /* select local page x */
- mii_mgr_read(port_no, reg_num, &phy_val);
- return phy_val;
-}
-
-u32 tc_phy_read_dev_reg_raeth(u32 port_num, u32 dev_addr, u32 reg_addr)
-{
- u32 phy_val;
-
- mii_mgr_read_cl45(port_num, dev_addr, reg_addr, &phy_val);
- return phy_val;
-}
-
-void tc_phy_write_dev_reg_raeth(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
-{
- mii_mgr_write_cl45(port_num, dev_addr, reg_addr, write_data);
-}
-
-u32 tc_mii_read(u32 phy_addr, u32 phy_register)
-{
- u32 phy_val;
-
- mii_mgr_read(phy_addr, phy_register, &phy_val);
- return phy_val;
-}
-
-void tc_mii_write(u32 phy_addr, u32 phy_register, u32 write_data)
-{
- mii_mgr_write(phy_addr, phy_register, write_data);
-}
-
-void clear_ckinv_ana_txvos(void)
-{
- u16 g7r24_tmp;
- /*clear RG_CAL_CKINV/RG_ANA_CALEN/RG_TXVOS_CALEN*/
- /*g7r24[13]:0x0, RG_ANA_CALEN_P0*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x2000)));
-
- /*g7r24[14]:0x0, RG_CAL_CKINV_P0*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x4000)));
-
- /*g7r24[12]:0x0, DA_TXVOS_CALEN_P0*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x1000)));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0);
-}
-
-u8 all_fe_ana_cal_wait_txamp(u32 delay, u8 port_num)
-{ /* for EN7512 FE // allen_20160616 */
- u8 all_ana_cal_status;
- u16 cnt, g7r24_temp;
-
- tc_phy_write_l_reg(FE_CAL_COMMON, 4, 23, (0x0000));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp | 0x10);
-
- cnt = 1000;
- do {
- udelay(delay);
- cnt--;
- all_ana_cal_status =
- ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) >> 1) & 0x1);
- } while ((all_ana_cal_status == 0) && (cnt != 0));
-
- tc_phy_write_l_reg(FE_CAL_COMMON, 4, 23, (0x0000));
- tc_phy_write_l_reg(port_num, 4, 23, (0x0000));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
- return all_ana_cal_status;
-}
-
-u8 all_fe_ana_cal_wait(u32 delay, u8 port_num)
-{
- u8 all_ana_cal_status;
- u16 cnt, g7r24_temp;
-
- tc_phy_write_l_reg(FE_CAL_COMMON, 4, 23, (0x0000));
- tc_phy_write_l_reg(port_num, 4, 23, (0x0000));
-
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp | 0x10);
- cnt = 1000;
- do {
- udelay(delay);
- cnt--;
- all_ana_cal_status =
- ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) >> 1) & 0x1);
-
- } while ((all_ana_cal_status == 0) && (cnt != 0));
-
- tc_phy_write_l_reg(FE_CAL_COMMON, 4, 23, (0x0000));
- tc_phy_write_l_reg(port_num, 4, 23, (0x0000));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
-
- return all_ana_cal_status;
-}
-
-void fe_cal_tx_amp(u8 port_num, u32 delay)
-{
- u8 all_ana_cal_status;
- int ad_cal_comp_out_init;
- u16 l3r25_temp, l0r26_temp, l2r20_temp;
- u16 l2r23_temp = 0;
- int calibration_polarity;
- u8 tx_amp_reg_shift = 0;
- int tx_amp_temp = 0, cnt = 0, phyaddr, tx_amp_cnt = 0;
- u16 tx_amp_final;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- phyaddr = port_num + ephy_addr_base;
- tx_amp_temp = 0x20;
- /* *** Tx Amp Cal start ********************** */
-
-/*Set device in 100M mode*/
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
-/*TXG output DC differential 1V*/
- tc_phy_write_g_reg(port_num, 2, 25, 0x10c0);
-
- tc_phy_write_g_reg(port_num, 1, 26, (0x8000 | DAC_IN_2V));
- tc_phy_write_g_reg(port_num, 4, 21, (0x0800)); /* set default */
- tc_phy_write_l_reg(port_num, 0, 30, (0x02c0));
- tc_phy_write_l_reg(port_num, 4, 21, (0x0000));
-
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, (0xc800));
- tc_phy_write_l_reg(port_num, 3, 25, (0xc800));
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x7000);
-
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x400));
-
- /*decide which port calibration RG_ZCALEN by port_num*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- l3r25_temp = l3r25_temp | 0x1000;
- l3r25_temp = l3r25_temp & ~(0x200);
- tc_phy_write_l_reg(port_num, 3, 25, l3r25_temp);
-
- /*DA_PGA_MDIX_STASTUS_P0=0(L0R26[15:14] = 0x01*/
- l0r26_temp = tc_phy_read_l_reg(port_num, 0, 26);
- l0r26_temp = l0r26_temp & (~0xc000);
- tc_phy_write_l_reg(port_num, 0, 26, 0x5203);/* Kant */
-
- /*RG_RX2TX_EN_P0=0(L2R20[10] =0),*/
- l2r20_temp = tc_phy_read_l_reg(port_num, 2, 20);
- l2r20_temp = l2r20_temp & (~0x400);
- tc_phy_write_l_reg(port_num, 2, 20, l2r20_temp);
- tc_phy_write_l_reg(port_num, 2, 23, (tx_amp_temp));
-
- all_ana_cal_status = all_fe_ana_cal_wait_txamp(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx amp AnaCal ERROR! (init) \r\n");
- }
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
-
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- tx_amp_temp += calibration_polarity;
- cnt = 0;
- tx_amp_cnt = 0;
- while (all_ana_cal_status < ANACAL_ERROR) {
- tc_phy_write_l_reg(port_num, 2, 23, (tx_amp_temp));
- l2r23_temp = tc_phy_read_l_reg(port_num, 2, 23);
- cnt++;
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- all_ana_cal_status = all_fe_ana_cal_wait_txamp(delay, port_num);
-
- if (((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24)) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- fe_cal_flag = 1;
- }
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx amp AnaCal ERROR! (%d) \r\n", cnt);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- tx_amp_cnt++;
- all_ana_cal_status = ANACAL_FINISH;
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- ad_cal_comp_out_init =
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- } else {
- if ((l2r23_temp == 0x3f) || (l2r23_temp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info
- (" Tx amp Cal Saturation(%d)(%x)(%x)\r\n",
- cnt, tc_phy_read_l_reg(0, 3, 25),
- tc_phy_read_l_reg(1, 3, 25));
- pr_info
- (" Tx amp Cal Saturation(%x)(%x)(%x)\r\n",
- tc_phy_read_l_reg(2, 3, 25),
- tc_phy_read_l_reg(3, 3, 25),
- tc_phy_read_l_reg(0, 2, 30));
- /* tx_amp_temp += calibration_polarity; */
- } else {
- tx_amp_temp += calibration_polarity;
- }
- }
- }
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- l2r23_temp = tc_phy_read_l_reg(port_num, 2, 23);
- tc_phy_write_l_reg(port_num, 2, 23,
- ((tx_amp_temp << tx_amp_reg_shift)));
- l2r23_temp = tc_phy_read_l_reg(port_num, 2, 23);
- pr_info("[%d] %s, ANACAL_SATURATION\n", port_num, __func__);
- } else {
- if (ei_local->chip_name == MT7622_FE) {
- if (port_num == 0)
- l2r23_temp = l2r23_temp + 10;
- else if (port_num == 1)
- l2r23_temp = l2r23_temp + 11;
- else if (port_num == 2)
- l2r23_temp = l2r23_temp + 10;
- else if (port_num == 3)
- l2r23_temp = l2r23_temp + 9;
- else if (port_num == 4)
- l2r23_temp = l2r23_temp + 10;
- } else if (ei_local->chip_name == LEOPARD_FE) {
- if (port_num == 1)
- l2r23_temp = l2r23_temp + 3;
- else if (port_num == 2)
- l2r23_temp = l2r23_temp + 3;
- else if (port_num == 3)
- l2r23_temp = l2r23_temp + 3 - 2;
- else if (port_num == 4)
- l2r23_temp = l2r23_temp + 2 - 1 + 2;
- }
-
- tc_phy_write_l_reg(port_num, 2, 23, ((l2r23_temp) << tx_amp_reg_shift));
- fe_cal_flag = 1;
- }
-
- tx_amp_final = tc_phy_read_l_reg(port_num, 2, 23) & 0x3f;
- tc_phy_write_l_reg(port_num, 2, 24, ((tx_amp_final + 15) << 8) | 0x20);
-
- if (ei_local->chip_name == LEOPARD_FE) {
- if (port_num == 1)
- tc_phy_write_l_reg(port_num, 2, 24, ((tx_amp_final + 15 - 4) << 8) | 0x20);
- else if (port_num == 2)
- tc_phy_write_l_reg(port_num, 2, 24, ((tx_amp_final + 15 + 2) << 8) | 0x20);
- else if (port_num == 3)
- tc_phy_write_l_reg(port_num, 2, 24, ((tx_amp_final + 15 + 4) << 8) | 0x20);
- else if (port_num == 4)
- tc_phy_write_l_reg(port_num, 2, 24, ((tx_amp_final + 15 + 4) << 8) | 0x20);
- }
-
- pr_info("[%d] - tx_amp_final = 0x%x\n", port_num, tx_amp_final);
-
- /*clear RG_CAL_CKINV/RG_ANA_CALEN/RG_TXVOS_CALEN*/
- clear_ckinv_ana_txvos();
-
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
- tc_phy_write_g_reg(port_num, 1, 26, 0);
- /* *** Tx Amp Cal end *** */
-}
-
-void fe_cal_tx_amp_mdix(u8 port_num, u32 delay)
-{
- u8 all_ana_cal_status;
- int ad_cal_comp_out_init;
- u16 l3r25_temp, l4r26_temp, l0r26_temp;
- u16 l2r20_temp, l4r26_temp_amp;
- int calibration_polarity;
- int tx_amp_temp = 0, cnt = 0, phyaddr, tx_amp_cnt = 0;
- u16 tx_amp_mdix_final;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- phyaddr = port_num + ephy_addr_base;
- tx_amp_temp = 0x20;
-/*Set device in 100M mode*/
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
-/*TXG output DC differential 0V*/
- tc_phy_write_g_reg(port_num, 2, 25, 0x10c0);
-
- tc_phy_write_g_reg(port_num, 1, 26, (0x8000 | DAC_IN_2V));
- tc_phy_write_g_reg(port_num, 4, 21, (0x0800)); /* set default */
- tc_phy_write_l_reg(port_num, 0, 30, (0x02c0));/*0x3f80 // l0r30[9], [7], [6], [1]*/
- tc_phy_write_l_reg(port_num, 4, 21, (0x0000));
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, (0xc800));
- tc_phy_write_l_reg(port_num, 3, 25, (0xc800)); /* 0xca00 */
- /* *** Tx Amp Cal start ********************** */
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x7000);
- /* pr_info(" g7r24[%d] = %x\n", port_num, tc_phy_read_g_reg(port_num, 7, 24)); */
-
- /*RG_TXG_CALEN =1 l3r25[10]by port number*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x400));
- /*decide which port calibration RG_ZCALEN l3r25[12] by port_num*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- l3r25_temp = l3r25_temp | 0x1000;
- l3r25_temp = l3r25_temp & ~(0x200);
- tc_phy_write_l_reg(port_num, 3, 25, l3r25_temp);
-
- /*DA_PGA_MDIX_STASTUS_P0=0(L0R26[15:14] = 0x10) & RG_RX2TX_EN_P0=0(L2R20[10] =1),*/
- l0r26_temp = tc_phy_read_l_reg(port_num, 0, 26);
- l0r26_temp = l0r26_temp & (~0xc000);
- tc_phy_write_l_reg(port_num, 0, 26, 0x9203); /* Kant */
- l2r20_temp = tc_phy_read_l_reg(port_num, 2, 20);
- l2r20_temp = l2r20_temp | 0x400;
- tc_phy_write_l_reg(port_num, 2, 20, l2r20_temp);
-
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x0400));
-/*DA_TX_I2MPB_MDIX L4R26[5:0]*/
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- /* pr_info("111l4r26 =%x\n", tc_phy_read_l_reg(port_num, 4, 26)); */
- l4r26_temp = l4r26_temp & (~0x3f);
- tc_phy_write_l_reg(port_num, 4, 26, (l4r26_temp | tx_amp_temp));
- /* pr_info("222l4r26 =%x\n", tc_phy_read_l_reg(port_num, 4, 26)); */
- all_ana_cal_status = all_fe_ana_cal_wait_txamp(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx amp mdix AnaCal ERROR! (init) \r\n");
- }
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- /*ad_cal_comp_out_init = (tc_phy_read_l_reg(FE_CAL_COMMON, 4, 23) >> 4) & 0x1;*/
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- /* pr_info("mdix ad_cal_comp_out_init = %d\n", ad_cal_comp_out_init); */
- if (ad_cal_comp_out_init == 1) {
- calibration_polarity = -1;
- /* tx_amp_temp = 0x10; */
- } else {
- calibration_polarity = 1;
- }
- tx_amp_temp += calibration_polarity;
- cnt = 0;
- tx_amp_cnt = 0;
- while (all_ana_cal_status < ANACAL_ERROR) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp & (~0x3f);
- tc_phy_write_l_reg(port_num, 4, 26, (l4r26_temp | tx_amp_temp));
- l4r26_temp = (tc_phy_read_l_reg(port_num, 4, 26));
- l4r26_temp_amp = (tc_phy_read_l_reg(port_num, 4, 26)) & 0x3f;
- cnt++;
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- all_ana_cal_status = all_fe_ana_cal_wait_txamp(delay, port_num);
-
- if (((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24)) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- fe_cal_flag_mdix = 1;
- }
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx amp mdix AnaCal ERROR! (%d) \r\n", cnt);
- } else if (((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24)) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- ad_cal_comp_out_init =
- (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24)) & 0x1;
- } else {
- if ((l4r26_temp_amp == 0x3f) || (l4r26_temp_amp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info
- (" Tx amp Cal mdix Saturation(%d)(%x)(%x)\r\n",
- cnt, tc_phy_read_l_reg(0, 3, 25),
- tc_phy_read_l_reg(1, 3, 25));
- pr_info
- (" Tx amp Cal mdix Saturation(%x)(%x)(%x)\r\n",
- tc_phy_read_l_reg(2, 3, 25),
- tc_phy_read_l_reg(3, 3, 25),
- tc_phy_read_l_reg(0, 2, 30));
- /* tx_amp_temp += calibration_polarity; */
- } else {
- tx_amp_temp += calibration_polarity;
- }
- }
- }
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- pr_info(" FE-%d Tx amp AnaCal mdix Saturation! (%d)(l4r26=0x%x) \r\n",
- phyaddr, cnt, l4r26_temp);
- tc_phy_write_l_reg(port_num, 4, 26,
- ((l4r26_temp & (~0x3f)) | tx_amp_temp));
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- pr_info(" FE-%d Tx amp AnaCal mdix Saturation! (%d)(l4r26=0x%x) \r\n",
- phyaddr, cnt, l4r26_temp);
- pr_info("[%d] %s, ANACAL_SATURATION\n", port_num, __func__);
- } else {
- if (ei_local->chip_name == MT7622_FE) {
- if (port_num == 0) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 10;
- } else if (port_num == 1) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 11;
- } else if (port_num == 2) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 9;
- } else if (port_num == 3) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 9;
- } else if (port_num == 4) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 9;
- }
- } else if (ei_local->chip_name == LEOPARD_FE) {
- if (port_num == 1) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 4 - 2;
- } else if (port_num == 2) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 3 - 1;
- } else if (port_num == 3) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 4 - 3;
- } else if (port_num == 4) {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- l4r26_temp = l4r26_temp + 4 - 2 + 1;
- }
- }
- tc_phy_write_l_reg(port_num, 4, 26, l4r26_temp);
- fe_cal_flag_mdix = 1;
- }
-
- tx_amp_mdix_final = tc_phy_read_l_reg(port_num, 4, 26) & 0x3f;
- tc_phy_write_l_reg(port_num, 4, 27, ((tx_amp_mdix_final + 15) << 8) | 0x20);
- if (ei_local->chip_name == LEOPARD_FE) {
- if (port_num == 2)
- tc_phy_write_l_reg(port_num, 4, 27,
- ((tx_amp_mdix_final + 15 + 1) << 8) | 0x20);
- else if (port_num == 3)
- tc_phy_write_l_reg(port_num, 4, 27,
- ((tx_amp_mdix_final + 15 + 4) << 8) | 0x20);
- else if (port_num == 4)
- tc_phy_write_l_reg(port_num, 4, 27,
- ((tx_amp_mdix_final + 15 + 4) << 8) | 0x20);
- }
- pr_info("[%d] - tx_amp_mdix_final = 0x%x\n", port_num, tx_amp_mdix_final);
-
- clear_ckinv_ana_txvos();
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
- tc_phy_write_g_reg(port_num, 1, 26, 0);
- /* *** Tx Amp Cal end *** */
-}
-
-void fe_cal_tx_offset(u8 port_num, u32 delay)
-{
- u8 all_ana_cal_status;
- int ad_cal_comp_out_init;
- u16 l3r25_temp, l2r20_temp;
- u16 g4r21_temp, l0r30_temp, l4r17_temp, l0r26_temp;
- int calibration_polarity, tx_offset_temp;
- int cal_temp = 0;
- u8 tx_offset_reg_shift;
- u8 cnt = 0, phyaddr, tx_amp_cnt = 0;
- u16 tx_offset_final;
-
- phyaddr = port_num + ephy_addr_base;
-/*Set device in 100M mode*/
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
-
- /*// g4r21[11]:Hw bypass tx offset cal, Fw cal*/
- g4r21_temp = tc_phy_read_g_reg(port_num, 4, 21);
- tc_phy_write_g_reg(port_num, 4, 21, (g4r21_temp | 0x0800));
-
- /*l0r30[9], [7], [6], [1]*/
- l0r30_temp = tc_phy_read_l_reg(port_num, 0, 30);
- tc_phy_write_l_reg(port_num, 0, 30, (l0r30_temp | 0x02c0));
-
- /* tx_offset_temp = TX_AMP_OFFSET_0MV; */
- tx_offset_temp = 0x20;
- tx_offset_reg_shift = 8;
- tc_phy_write_g_reg(port_num, 1, 26, (0x8000 | DAC_IN_0V));
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x3000);
- /* pr_info(" g7r24[%d] = %x\n", port_num, tc_phy_read_g_reg(port_num, 7, 24)); */
- /*RG_TXG_CALEN =1 by port number*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x400));
- /*decide which port calibration RG_ZCALEN by port_num*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x1000));
-
- /*DA_PGA_MDIX_STASTUS_P0=0(L0R26[15:14] = 0x01) & RG_RX2TX_EN_P0=0(L2R20[10] =0),*/
- l0r26_temp = tc_phy_read_l_reg(port_num, 0, 26);
- l0r26_temp = l0r26_temp & (~0xc000);
- /* tc_phy_write_l_reg(port_num, 0, 26, (l0r26_temp | 0x4000)); */
- tc_phy_write_l_reg(port_num, 0, 26, 0x5203);/* Kant */
- /* pr_info("l0r26[%d] = %x\n", port_num, tc_phy_read_l_reg(port_num, 0, 26)); */
- l2r20_temp = tc_phy_read_l_reg(port_num, 2, 20);
- l2r20_temp = l2r20_temp & (~0x400);
- tc_phy_write_l_reg(port_num, 2, 20, l2r20_temp);
- /* pr_info("l2r20[%d] = %x\n", port_num, tc_phy_read_l_reg(port_num, 2, 20)); */
-
- tc_phy_write_l_reg(port_num, 4, 17, (0x0000));
- l4r17_temp = tc_phy_read_l_reg(port_num, 4, 17);
- tc_phy_write_l_reg(port_num, 4, 17,
- l4r17_temp |
- (tx_offset_temp << tx_offset_reg_shift));
-/*wat AD_CAL_CLK = 1*/
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx offset AnaCal ERROR! (init) \r\n");
- }
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
-/*GET AD_CAL_COMP_OUT g724[0]*/
- /*ad_cal_comp_out_init = (tc_phy_read_l_reg(FE_CAL_COMMON, 4, 23) >> 4) & 0x1;*/
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
-
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
- cnt = 0;
- tx_amp_cnt = 0;
- tx_offset_temp += calibration_polarity;
-
- while ((all_ana_cal_status < ANACAL_ERROR) && (cnt < 254)) {
- cnt++;
- cal_temp = tx_offset_temp;
- tc_phy_write_l_reg(port_num, 4, 17,
- (cal_temp << tx_offset_reg_shift));
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx offset AnaCal ERROR! (%d) \r\n", cnt);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
-
- ad_cal_comp_out_init =
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- } else {
- l4r17_temp = tc_phy_read_l_reg(port_num, 4, 17);
-
- if ((tx_offset_temp == 0x3f) || (tx_offset_temp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info("tx offset ANACAL_SATURATION\n");
- } else {
- tx_offset_temp += calibration_polarity;
- }
- }
- }
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- tx_offset_temp = TX_AMP_OFFSET_0MV;
- l4r17_temp = tc_phy_read_l_reg(port_num, 4, 17);
- tc_phy_write_l_reg(port_num, 4, 17,
- (l4r17_temp |
- (tx_offset_temp << tx_offset_reg_shift)));
- pr_info("[%d] %s, ANACAL_SATURATION\n", port_num, __func__);
- } else {
- fe_cal_tx_offset_flag = 1;
- }
- tx_offset_final = (tc_phy_read_l_reg(port_num, 4, 17) & 0x3f00) >> 8;
- pr_info("[%d] - tx_offset_final = 0x%x\n", port_num, tx_offset_final);
-
- clear_ckinv_ana_txvos();
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
- tc_phy_write_g_reg(port_num, 1, 26, 0);
-}
-
-void fe_cal_tx_offset_mdix(u8 port_num, u32 delay)
-{ /* for MT7622 */
- u8 all_ana_cal_status;
- int ad_cal_comp_out_init;
- u16 l3r25_temp, l2r20_temp, l4r26_temp;
- u16 g4r21_temp, l0r30_temp, l0r26_temp;
- int calibration_polarity, tx_offset_temp;
- int cal_temp = 0;
- u8 tx_offset_reg_shift;
- u8 cnt = 0, phyaddr;
- u16 tx_offset_final_mdix;
-
- phyaddr = port_num + ephy_addr_base;
-/*Set device in 100M mode*/
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
-
- /*// g4r21[11]:Hw bypass tx offset cal, Fw cal*/
- g4r21_temp = tc_phy_read_g_reg(port_num, 4, 21);
- tc_phy_write_g_reg(port_num, 4, 21, (g4r21_temp | 0x0800));
-
- /*l0r30[9], [7], [6], [1]*/
- l0r30_temp = tc_phy_read_l_reg(port_num, 0, 30);
- tc_phy_write_l_reg(port_num, 0, 30, (l0r30_temp | 0x02c0));
-
- tx_offset_temp = 0x20;
- tx_offset_reg_shift = 8;
- tc_phy_write_g_reg(port_num, 1, 26, (0x8000 | DAC_IN_0V));
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x3000);
-
- /*RG_TXG_CALEN =1 by port number*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x400));
-
- /*decide which port calibration RG_ZCALEN by port_num*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x1000));
-
- /*DA_PGA_MDIX_STASTUS_P0=0(L0R26[15:14] = 0x10) & RG_RX2TX_EN_P0=1(L2R20[10] =1),*/
- l0r26_temp = tc_phy_read_l_reg(port_num, 0, 26);
- l0r26_temp = l0r26_temp & (~0xc000);
- tc_phy_write_l_reg(port_num, 0, 26, 0x9203); /* Kant */
- l2r20_temp = tc_phy_read_l_reg(port_num, 2, 20);
- l2r20_temp = l2r20_temp | 0x400;
- tc_phy_write_l_reg(port_num, 2, 20, l2r20_temp);
-
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- tc_phy_write_l_reg(port_num, 4, 26, l4r26_temp & (~0x3f00));
- tc_phy_write_l_reg(port_num, 4, 26,
- (l4r26_temp & ~0x3f00) | (cal_temp << tx_offset_reg_shift));
-
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx offset mdix AnaCal ERROR! (init) \r\n");
- }
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
-
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
-
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- tx_offset_temp += calibration_polarity;
- while ((all_ana_cal_status < ANACAL_ERROR) && (cnt < 254)) {
- cnt++;
- cal_temp = tx_offset_temp;
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- tc_phy_write_l_reg(port_num, 4, 26,
- (l4r26_temp & ~0x3f00) | (cal_temp << tx_offset_reg_shift));
-
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE Tx offset mdix AnaCal ERROR! (%d) \r\n", cnt);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- ad_cal_comp_out_init =
- tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- } else {
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
-
- if ((tx_offset_temp == 0x3f) || (tx_offset_temp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info("tx offset ANACAL_SATURATION\n");
- } else {
- tx_offset_temp += calibration_polarity;
- }
- }
- }
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- tx_offset_temp = TX_AMP_OFFSET_0MV;
- l4r26_temp = tc_phy_read_l_reg(port_num, 4, 26);
- tc_phy_write_l_reg(port_num, 4, 26,
- (l4r26_temp & (~0x3f00)) | (cal_temp << tx_offset_reg_shift));
- pr_info("[%d] %s, ANACAL_SATURATION\n", port_num, __func__);
- } else {
- fe_cal_tx_offset_flag_mdix = 1;
- }
- tx_offset_final_mdix = (tc_phy_read_l_reg(port_num, 4, 26) & 0x3f00) >> 8;
- pr_info("[%d] - tx_offset_final_mdix = 0x%x\n", port_num, tx_offset_final_mdix);
-
- clear_ckinv_ana_txvos();
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
- tc_phy_write_g_reg(port_num, 1, 26, 0);
-}
-
-void set_r50_leopard(u8 port_num, u32 r50_cal_result)
-{
- int rg_zcal_ctrl_tx, rg_zcal_ctrl_rx;
- u16 l4r22_temp;
-
- rg_zcal_ctrl_rx = 0;
- rg_zcal_ctrl_tx = 0;
- pr_info("r50_cal_result = 0x%x\n", r50_cal_result);
- if (port_num == 0) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)];
- }
- if (port_num == 1) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 4;
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 4;
- }
- if (port_num == 2) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 4;
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 6;
- }
- if (port_num == 3) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 5;
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 6;
- }
- if (port_num == 4) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 4;
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result)] + 4;
- }
- if (rg_zcal_ctrl_tx > 0x7f)
- rg_zcal_ctrl_tx = 0x7f;
- if (rg_zcal_ctrl_rx > 0x7f)
- rg_zcal_ctrl_rx = 0x7f;
-/*R50OHM_RSEL_TX= LP4R22[14:8]*/
- tc_phy_write_l_reg(port_num, 4, 22, ((rg_zcal_ctrl_tx << 8)));
- l4r22_temp = tc_phy_read_l_reg(port_num, 4, 22);
-/*R50OHM_RSEL_RX= LP4R22[6:0]*/
- tc_phy_write_l_reg(port_num, 4, 22,
- (l4r22_temp | (rg_zcal_ctrl_rx << 0)));
- fe_cal_r50_flag = 1;
- pr_info("[%d] - r50 final result l4r22[%d] = %x\n", port_num,
- port_num, tc_phy_read_l_reg(port_num, 4, 22));
-}
-
-void set_r50_mt7622(u8 port_num, u32 r50_cal_result)
-{
- int rg_zcal_ctrl_tx, rg_zcal_ctrl_rx;
- u16 l4r22_temp;
-
- rg_zcal_ctrl_rx = 0;
- rg_zcal_ctrl_tx = 0;
- pr_info("r50_cal_result = 0x%x\n", r50_cal_result);
-
- if (port_num == 0) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 5)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 5)];
- }
- if (port_num == 1) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 3)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 3)];
- }
- if (port_num == 2) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 4)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 5)];
- }
- if (port_num == 3) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 4)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 3)];
- }
- if (port_num == 4) {
- rg_zcal_ctrl_tx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 4)];
- rg_zcal_ctrl_rx = ZCAL_TO_R50OHM_TBL_100[(r50_cal_result - 5)];
- }
-/*R50OHM_RSEL_TX= LP4R22[14:8]*/
- tc_phy_write_l_reg(port_num, 4, 22, ((rg_zcal_ctrl_tx << 8)));
- l4r22_temp = tc_phy_read_l_reg(port_num, 4, 22);
-/*R50OHM_RSEL_RX= LP4R22[6:0]*/
- tc_phy_write_l_reg(port_num, 4, 22,
- (l4r22_temp | (rg_zcal_ctrl_rx << 0)));
- fe_cal_r50_flag = 1;
- pr_info("[%d] - r50 final result l4r22[%d] = %x\n", port_num,
- port_num, tc_phy_read_l_reg(port_num, 4, 22));
-}
-
-void fe_ge_r50_common(u8 port_num)
-{
- u16 l3r25_temp, g7r24_tmp, l4r23_temp;
- u8 phyaddr;
-
- phyaddr = port_num;
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
- /*g2r25[7:5]:0x110, BG voltage output*/
- tc_phy_write_g_reg(FE_CAL_COMMON, 2, 25, 0xf0c0);
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x0000);
- /*g7r24[13]:0x01, RG_ANA_CALEN_P0=1*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x2000));
- /*g7r24[14]:0x01, RG_CAL_CKINV_P0=1*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x4000));
-
- /*g7r24[12]:0x01, DA_TXVOS_CALEN_P0=0*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x1000)));
-
- /*DA_R50OHM_CAL_EN l4r23[0] = 0*/
- l4r23_temp = tc_phy_read_l_reg(port_num, 4, 23);
- l4r23_temp = l4r23_temp & ~(0x01);
- tc_phy_write_l_reg(port_num, 4, 23, l4r23_temp);
-
- /*RG_REXT_CALEN l2r25[13] = 0*/
- l3r25_temp = tc_phy_read_l_reg(FE_CAL_COMMON, 3, 25);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, (l3r25_temp & (~0x2000)));
-}
-
-void fe_cal_r50(u8 port_num, u32 delay)
-{
- int rg_zcal_ctrl, all_ana_cal_status, rg_zcal_ctrl_tx, rg_zcal_ctrl_rx;
- int ad_cal_comp_out_init;
- u16 l3r25_temp, l0r4, g7r24_tmp, l4r23_temp;
- int calibration_polarity;
- u8 cnt = 0, phyaddr;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- phyaddr = port_num + ephy_addr_base;
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
- /*g2r25[7:5]:0x110, BG voltage output*/
- tc_phy_write_g_reg(FE_CAL_COMMON, 2, 25, 0xf0c0);
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x0000);
- /*g7r24[13]:0x01, RG_ANA_CALEN_P0=1*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x2000));
- /*g7r24[14]:0x01, RG_CAL_CKINV_P0=1*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x4000));
-
- /*g7r24[12]:0x01, DA_TXVOS_CALEN_P0=0*/
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x1000)));
-
- /* pr_info("g7r24 = %x\n", g7r24_tmp); */
-
- /*DA_R50OHM_CAL_EN l4r23[0] = 1*/
- l4r23_temp = tc_phy_read_l_reg(port_num, 4, 23);
- tc_phy_write_l_reg(port_num, 4, 23, (l4r23_temp | (0x01)));
-
- /*RG_REXT_CALEN l2r25[13] = 0*/
- l3r25_temp = tc_phy_read_l_reg(FE_CAL_COMMON, 3, 25);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, (l3r25_temp & (~0x2000)));
-
- /*decide which port calibration RG_ZCALEN by port_num*/
- l3r25_temp = tc_phy_read_l_reg(port_num, 3, 25);
- tc_phy_write_l_reg(port_num, 3, 25, (l3r25_temp | 0x1000));
-
- rg_zcal_ctrl = 0x20; /* start with 0 dB */
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
-
- /*wait AD_CAL_COMP_OUT = 1*/
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE R50 AnaCal ERROR! (init) \r\n");
- }
-
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
-
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- while ((all_ana_cal_status < ANACAL_ERROR) && (cnt < 254)) {
- cnt++;
-
- rg_zcal_ctrl += calibration_polarity;
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" FE R50 AnaCal ERROR! (%d) \r\n", cnt);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- } else {
- if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info(" FE R50 AnaCal Saturation! (%d) \r\n",
- cnt);
- } else {
- l0r4 = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- l0r4 = l0r4 & 0x1;
- }
- }
- }
- if (port_num == 0)
- r50_p0_cal_result = rg_zcal_ctrl;
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- rg_zcal_ctrl = 0x20; /* 0 dB */
- rg_zcal_ctrl_tx = 0x7f;
- rg_zcal_ctrl_rx = 0x7f;
- pr_info("[%d] %s, ANACAL_SATURATION\n", port_num, __func__);
- } else {
- fe_cal_r50_flag = 1;
- }
- if (ei_local->chip_name == MT7622_FE)
- set_r50_mt7622(port_num, rg_zcal_ctrl);
- else if (ei_local->chip_name == LEOPARD_FE)
- set_r50_leopard(port_num, rg_zcal_ctrl);
-
- clear_ckinv_ana_txvos();
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
-}
-
-void fe_cal_vbg(u8 port_num, u32 delay)
-{
- int rg_zcal_ctrl, all_ana_cal_status;
- int ad_cal_comp_out_init, port_no;
- u16 l3r25_temp, l0r4, g7r24_tmp, l3r26_temp;
- int calibration_polarity;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u16 g2r22_temp, rg_bg_rasel;
- u8 cnt = 0, phyaddr;
-
- rg_bg_rasel = 0;
- ephy_addr_base = 0;
- phyaddr = port_num + ephy_addr_base;
-
- tc_phy_write_g_reg(FE_CAL_COMMON, 2, 25, 0x30c0);
- tc_phy_write_g_reg(FE_CAL_COMMON, 0, 25, 0x0030);
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x2000));
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp | 0x4000));
-
- g7r24_tmp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, (g7r24_tmp & (~0x1000)));
-
- l3r25_temp = tc_phy_read_l_reg(FE_CAL_COMMON, 3, 25);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, (l3r25_temp | 0x2000));
-
- for (port_no = port_num; port_no < 5; port_no++) {
- l3r25_temp = tc_phy_read_l_reg(port_no, 3, 25);
- tc_phy_write_l_reg(port_no, 3, 25, (l3r25_temp & (~0x1000)));
- }
- rg_zcal_ctrl = 0x0; /* start with 0 dB */
-
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
-
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" fe_cal_vbg ERROR! (init) \r\n");
- }
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
-
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- while ((all_ana_cal_status < ANACAL_ERROR) && (cnt < 254)) {
- cnt++;
- rg_zcal_ctrl += calibration_polarity;
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
- all_ana_cal_status = all_fe_ana_cal_wait(delay, port_num);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info("VBG ERROR(%d)status=%d\n", cnt, all_ana_cal_status);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- } else {
- if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info(" VBG0 AnaCal Saturation! (%d) \r\n",
- cnt);
- } else {
- l0r4 = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- l0r4 = l0r4 & 0x1;
- }
- }
- }
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- rg_zcal_ctrl = 0x20; /* 0 dB */
- } else {
- fe_cal_vbg_flag = 1;
- }
-
- rg_zcal_ctrl = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (0xfc0)) >> 6;
- iext_cal_result = rg_zcal_ctrl;
- pr_info("iext_cal_result = 0x%x\n", iext_cal_result);
- if (ei_local->chip_name == LEOPARD_FE)
- rg_bg_rasel = ZCAL_TO_REXT_TBL[rg_zcal_ctrl];
-
- l3r26_temp = tc_phy_read_l_reg(FE_CAL_COMMON, 3, 26);
- l3r26_temp = l3r26_temp & (~0xfc0);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 26, l3r26_temp | ((rg_zcal_ctrl & 0x3f) << 6));
-
- g2r22_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 2, 22);
- g2r22_temp = g2r22_temp & (~0xe00);/*[11:9]*/
-
- if (ei_local->chip_name == LEOPARD_FE) {
- rg_bg_rasel = rg_bg_rasel & 0x7;
- tc_phy_write_g_reg(FE_CAL_COMMON, 2, 22,
- g2r22_temp | (rg_bg_rasel << 9));
- } else if (ei_local->chip_name == MT7622_FE) {
- rg_zcal_ctrl = rg_zcal_ctrl & 0x38;
- tc_phy_write_g_reg(FE_CAL_COMMON, 2, 22,
- g2r22_temp | (((rg_zcal_ctrl & 0x38) >> 3) << 9));
- }
- clear_ckinv_ana_txvos();
-
- tc_phy_write_l_reg(port_num, 3, 25, 0x0000);
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, 0x0000);
-}
-
-#define CALDLY 40
-
-void do_fe_phy_all_analog_cal(u8 port_num)
-{
- u16 l0r26_temp, l0r30_temp, l3r25_tmp;
- u8 cnt = 0, phyaddr, i, iext_port;
- u32 iext_s, iext_e, r50_s, r50_e, txo_s, txo_e, txa_s, txa_e;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- iext_port = 0;
- ephy_addr_base = 0;
- phyaddr = port_num + ephy_addr_base;
- l0r26_temp = tc_phy_read_l_reg(port_num, 0, 26);
- tc_phy_write_l_reg(port_num, 0, 26, 0x5600);
- tc_phy_write_l_reg(port_num, 4, 21, 0x0000);
- tc_phy_write_l_reg(port_num, 0, 0, 0x2100);
-
- l0r30_temp = tc_phy_read_l_reg(port_num, 0, 30);
-
-/*eye pic.*/
- tc_phy_write_g_reg(port_num, 5, 20, 0x0170);
- tc_phy_write_g_reg(port_num, 5, 23, 0x0220);
- tc_phy_write_g_reg(port_num, 5, 24, 0x0206);
- tc_phy_write_g_reg(port_num, 5, 26, 0x0370);
- tc_phy_write_g_reg(port_num, 5, 27, 0x02f2);
- tc_phy_write_g_reg(port_num, 5, 29, 0x001b);
- tc_phy_write_g_reg(port_num, 5, 30, 0x0002);
-/*Yiron default setting*/
- for (i = port_num; i < 5; i++) {
- tc_phy_write_g_reg(i, 3, 23, 0x0);
- tc_phy_write_l_reg(i, 3, 23, 0x2004);
- tc_phy_write_l_reg(i, 2, 21, 0x8551);
- tc_phy_write_l_reg(i, 4, 17, 0x2000);
- tc_phy_write_g_reg(i, 7, 20, 0x7c62);
- tc_phy_write_l_reg(i, 4, 20, 0x4444);
- tc_phy_write_l_reg(i, 2, 22, 0x1011);
- tc_phy_write_l_reg(i, 4, 28, 0x1011);
- tc_phy_write_l_reg(i, 4, 19, 0x2222);
- tc_phy_write_l_reg(i, 4, 29, 0x2222);
- tc_phy_write_l_reg(i, 2, 28, 0x3444);
- tc_phy_write_l_reg(i, 2, 29, 0x04c6);
- tc_phy_write_l_reg(i, 4, 30, 0x0006);
- tc_phy_write_l_reg(i, 5, 16, 0x04c6);
- }
- if (ei_local->chip_name == LEOPARD_FE) {
- tc_phy_write_l_reg(port_num, 0, 20, 0x0c0c);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x017d, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x017e, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x017f, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x0180, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x0181, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x0182, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x0183, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x0184, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x00db, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x00dc, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x003e, 0x0000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x00dd, 0x0000);
-
- /*eye pic.*/
- tc_phy_write_g_reg(1, 5, 19, 0x0100);
- tc_phy_write_g_reg(1, 5, 20, 0x0161);
- tc_phy_write_g_reg(1, 5, 21, 0x00f0);
- tc_phy_write_g_reg(1, 5, 22, 0x0046);
- tc_phy_write_g_reg(1, 5, 23, 0x0210);
- tc_phy_write_g_reg(1, 5, 24, 0x0206);
- tc_phy_write_g_reg(1, 5, 25, 0x0238);
- tc_phy_write_g_reg(1, 5, 26, 0x0360);
- tc_phy_write_g_reg(1, 5, 27, 0x02f2);
- tc_phy_write_g_reg(1, 5, 28, 0x0240);
- tc_phy_write_g_reg(1, 5, 29, 0x0010);
- tc_phy_write_g_reg(1, 5, 30, 0x0002);
- }
- if (ei_local->chip_name == MT7622_FE)
- iext_port = 0;
- else if (ei_local->chip_name == LEOPARD_FE)
- iext_port = 1;
-
- if (port_num == iext_port) {
- /*****VBG & IEXT Calibration*****/
- cnt = 0;
- while ((fe_cal_vbg_flag == 0) && (cnt < 0x03)) {
- iext_s = jiffies;
- fe_cal_vbg(port_num, 1); /* allen_20160608 */
- iext_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_cal_vbg time = %u\n",
- port_num, (iext_e - iext_s) * 4);
- cnt++;
- if (fe_cal_vbg_flag == 0)
- pr_info(" FE-%d VBG wait! (%d) \r\n", phyaddr, cnt);
- }
- fe_cal_vbg_flag = 0;
- /**** VBG & IEXT Calibration end ****/
- }
-
- /* *** R50 Cal start *************************************** */
- cnt = 0;
- while ((fe_cal_r50_flag == 0) && (cnt < 0x03)) {
- r50_s = jiffies;
-
- fe_cal_r50(port_num, 1);
-
- r50_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_r50 time = %u\n",
- port_num, (r50_e - r50_s) * 4);
- cnt++;
- if (fe_cal_r50_flag == 0)
- pr_info(" FE-%d R50 wait! (%d) \r\n", phyaddr, cnt);
- }
- fe_cal_r50_flag = 0;
- cnt = 0;
- /* *** R50 Cal end *** */
- /* *** Tx offset Cal start ********************************* */
-
- cnt = 0;
- while ((fe_cal_tx_offset_flag == 0) && (cnt < 0x03)) {
- txo_s = jiffies;
- fe_cal_tx_offset(port_num, CALDLY);
- txo_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_cal_tx_offset time = %u\n",
- port_num, (txo_e - txo_s) * 4);
- cnt++;
- }
- fe_cal_tx_offset_flag = 0;
- cnt = 0;
-
- while ((fe_cal_tx_offset_flag_mdix == 0) && (cnt < 0x03)) {
- txo_s = jiffies;
- fe_cal_tx_offset_mdix(port_num, CALDLY);
- txo_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_cal_tx_offset_mdix time = %u\n",
- port_num, (txo_e - txo_s) * 4);
- cnt++;
- }
- fe_cal_tx_offset_flag_mdix = 0;
- cnt = 0;
- /* *** Tx offset Cal end *** */
-
- /* *** Tx Amp Cal start ************************************** */
- cnt = 0;
- while ((fe_cal_flag == 0) && (cnt < 0x3)) {
- txa_s = jiffies;
- fe_cal_tx_amp(port_num, CALDLY); /* allen_20160608 */
- txa_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_cal_tx_amp time = %u\n",
- port_num, (txa_e - txa_s) * 4);
- cnt++;
- }
- fe_cal_flag = 0;
- cnt = 0;
- while ((fe_cal_flag_mdix == 0) && (cnt < 0x3)) {
- txa_s = jiffies;
- fe_cal_tx_amp_mdix(port_num, CALDLY);
- txa_e = jiffies;
- if (show_time)
- pr_info("port[%d] fe_cal_tx_amp_mdix time = %u\n",
- port_num, (txa_e - txa_s) * 4);
- cnt++;
- }
- fe_cal_flag_mdix = 0;
- cnt = 0;
-
- l3r25_tmp = tc_phy_read_l_reg(port_num, 3, 25);
- l3r25_tmp = l3r25_tmp & ~(0x1000);/*[12] RG_ZCALEN = 0*/
- tc_phy_write_l_reg(port_num, 3, 25, l3r25_tmp);
- tc_phy_write_g_reg(port_num, 1, 26, 0x0000);
- tc_phy_write_l_reg(port_num, 0, 26, l0r26_temp);
- tc_phy_write_l_reg(port_num, 0, 30, l0r30_temp);
- tc_phy_write_g_reg(port_num, 1, 26, 0x0000);
- tc_phy_write_l_reg(port_num, 0, 0, 0x3100);
- /*enable flow control*/
- tc_phy_write_g_reg(port_num, 0, 4, 0x5e1);
-}
-
-u8 all_ge_ana_cal_wait_raeth(unsigned int delay, u8 port_num) /* for EN7512 */
-{
- u8 all_ana_cal_status;
- u16 cnt, g7r24_temp;
-
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp | 0x10);
-
- cnt = 1000;
- do {
- udelay(delay);
- cnt--;
- all_ana_cal_status =
- ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) >> 1) & 0x1);
-
- } while ((all_ana_cal_status == 0) && (cnt != 0));
- g7r24_temp = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_temp & (~0x10));
-
- return all_ana_cal_status;
-}
-
-void ge_cal_rext_raeth_raeth(u8 phyaddr, unsigned int delay)
-{
- u8 rg_zcal_ctrl, all_ana_cal_status;
- u16 ad_cal_comp_out_init;
- u16 dev1e_e0_ana_cal_r5;
- int calibration_polarity;
- u8 cnt = 0;
- u16 dev1e_17a_tmp, dev1e_e0_tmp;
-
- /* *** Iext/Rext Cal start ************ */
- all_ana_cal_status = ANACAL_INIT;
- /* analog calibration enable, Rext calibration enable */
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[0]:rg_txvos_calen */
- /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x1110);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dc, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e1, 0x0000);
-
- rg_zcal_ctrl = 0x20;/* start with 0 dB */
- dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x00e0);
- /* 1e_e0[5:0]:rg_zcal_ctrl */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e0, (rg_zcal_ctrl));
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);/* delay 20 usec */
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Rext AnaCal ERROR! \r\n");
- }
- /* 1e_17a[8]:ad_cal_comp_out */
- ad_cal_comp_out_init = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x017a) >> 8) & 0x1;
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else /* ad_cal_comp_out_init == 0 */
- calibration_polarity = 1;
-
- cnt = 0;
- while (all_ana_cal_status < ANACAL_ERROR) {
- cnt++;
- rg_zcal_ctrl += calibration_polarity;
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e0, (rg_zcal_ctrl));
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr); /* delay 20 usec */
- dev1e_17a_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x017a);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Rext AnaCal ERROR! \r\n");
- } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- pr_info(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
- } else {
- dev1e_17a_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x017a);
- dev1e_e0_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0xe0);
- if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
- pr_info(" GE Rext AnaCal Saturation! \r\n");
- rg_zcal_ctrl = 0x20; /* 0 dB */
- } else {
- pr_info(" GE Rxet cal (%d)(%d)(%d)(0x%x) \r\n",
- cnt, ad_cal_comp_out_init,
- ((dev1e_17a_tmp >> 8) & 0x1), dev1e_e0_tmp);
- }
- }
- }
-
- if (all_ana_cal_status == ANACAL_ERROR) {
- rg_zcal_ctrl = 0x20; /* 0 dB */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
- } else {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
- /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
- pr_info(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
- ge_cal_flag_raeth = 1;
- }
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x0000);
- /* *** Iext/Rext Cal end *** */
-}
-
-void ge_cal_r50_raeth(u8 phyaddr, unsigned int delay)
-{
- u8 rg_zcal_ctrl, all_ana_cal_status, i;
- u16 ad_cal_comp_out_init;
- u16 dev1e_e0_ana_cal_r5;
- int calibration_polarity;
- u16 cal_pair, val_tmp, g7r24_tmp;
- u16 dev1e_174_tmp, dev1e_175_tmp, l3r25_temp;
- u8 rg_zcal_ctrl_filter, cnt = 0;
-
- /* *** R50 Cal start***************** */
- fe_ge_r50_common(phyaddr);
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[0]:rg_txvos_calen */
- /*disable RG_ZCALEN*/
- /*decide which port calibration RG_ZCALEN by port_num*/
- for (i = 1; i <= 4; i++) {
- l3r25_temp = tc_phy_read_l_reg(i, 3, 25);
- l3r25_temp = l3r25_temp & ~(0x1000);
- tc_phy_write_l_reg(i, 3, 25, l3r25_temp);
- }
- for (cal_pair = ANACAL_PAIR_A; cal_pair <= ANACAL_PAIR_D; cal_pair++) {
- rg_zcal_ctrl = 0x20;/* start with 0 dB */
- dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x00e0) & (~0x003f));
- /* 1e_e0[5:0]:rg_zcal_ctrl */
- if (cal_pair == ANACAL_PAIR_A) {
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x1000);
- } else if (cal_pair == ANACAL_PAIR_B) {
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[12]:rg_zcalen_b */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0100);
- } else if (cal_pair == ANACAL_PAIR_C) {
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[8]:rg_zcalen_c */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0010);
-
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
-
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[4]:rg_zcalen_d */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0001);
- }
- rg_zcal_ctrl = 0x20; /* start with 0 dB */
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
-
- /*wait AD_CAL_COMP_OUT = 1*/
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE R50 AnaCal ERROR! (init) \r\n");
- }
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- while ((all_ana_cal_status < ANACAL_ERROR) && (cnt < 254)) {
- cnt++;
-
- rg_zcal_ctrl += calibration_polarity;
- g7r24_tmp = (tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & (~0xfc0));
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24,
- g7r24_tmp | ((rg_zcal_ctrl & 0x3f) << 6));
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);
-
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE R50 AnaCal ERROR! (%d) \r\n", cnt);
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- } else {
- if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info(" GE R50 Cal Sat! rg_zcal_ctrl = 0x%x(%d)\n",
- cnt, rg_zcal_ctrl);
- }
- }
- }
-
- if ((all_ana_cal_status == ANACAL_ERROR) ||
- (all_ana_cal_status == ANACAL_SATURATION)) {
- rg_zcal_ctrl = 0x20; /* 0 dB */
- rg_zcal_ctrl_filter = 8; /*default value*/
- } else {
- /*DA_TX_R50*/
- rg_zcal_ctrl_filter = rg_zcal_ctrl;
- rg_zcal_ctrl = ZCAL_TO_R50ohm_GE_TBL[rg_zcal_ctrl];
- /*DA_TX_FILTER*/
- rg_zcal_ctrl_filter = ZCAL_TO_FILTER_TBL[rg_zcal_ctrl_filter];
- rg_zcal_ctrl_filter = rg_zcal_ctrl_filter & 0xf;
- rg_zcal_ctrl_filter = rg_zcal_ctrl_filter << 8 | rg_zcal_ctrl_filter;
- }
- if (all_ana_cal_status == ANACAL_FINISH) {
- if (cal_pair == ANACAL_PAIR_A) {
- dev1e_174_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0174);
- dev1e_174_tmp = dev1e_174_tmp & ~(0xff00);
- if (rg_zcal_ctrl > 4) {
- val_tmp = (((rg_zcal_ctrl - 4) << 8) & 0xff00) |
- dev1e_174_tmp;
- } else {
- val_tmp = (((0) << 8) & 0xff00) | dev1e_174_tmp;
- }
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0174, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x03a0, rg_zcal_ctrl_filter);
-
- pr_info("R50_PAIR_A : 1e_174 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0174));
- pr_info("R50_PAIR_A : 1e_3a0 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x03a0));
-
- } else if (cal_pair == ANACAL_PAIR_B) {
- dev1e_174_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0174);
- dev1e_174_tmp = dev1e_174_tmp & (~0x007f);
- if (rg_zcal_ctrl > 2) {
- val_tmp = (((rg_zcal_ctrl - 2) << 0) & 0xff) |
- dev1e_174_tmp;
- } else {
- val_tmp = (((0) << 0) & 0xff) |
- dev1e_174_tmp;
- }
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0174, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x03a1, rg_zcal_ctrl_filter);
- pr_info("R50_PAIR_B : 1e_174 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0174));
- pr_info("R50_PAIR_B : 1e_3a1 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x03a1));
- } else if (cal_pair == ANACAL_PAIR_C) {
- dev1e_175_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0175);
- dev1e_175_tmp = dev1e_175_tmp & (~0x7f00);
- if (rg_zcal_ctrl > 4) {
- val_tmp = dev1e_175_tmp |
- (((rg_zcal_ctrl - 4) << 8) & 0xff00);
- } else {
- val_tmp = dev1e_175_tmp | (((0) << 8) & 0xff00);
- }
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0175, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x03a2, rg_zcal_ctrl_filter);
- pr_info("R50_PAIR_C : 1e_175 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0175));
- pr_info("R50_PAIR_C : 1e_3a2 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x03a2));
-
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
- dev1e_175_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0175);
- dev1e_175_tmp = dev1e_175_tmp & (~0x007f);
- if (rg_zcal_ctrl > 6) {
- val_tmp = dev1e_175_tmp |
- (((rg_zcal_ctrl - 6) << 0) & 0xff);
- } else {
- val_tmp = dev1e_175_tmp |
- (((0) << 0) & 0xff);
- }
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0175, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x03a3, rg_zcal_ctrl_filter);
- pr_info("R50_PAIR_D : 1e_175 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0175));
- pr_info("R50_PAIR_D : 1e_3a3 = 0x%x\n",
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x03a3));
- }
- }
- }
- clear_ckinv_ana_txvos();
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x0000);
- ge_cal_r50_raeth_flag = 1;
- /* *** R50 Cal end *** */
-}
-
-void ge_cal_tx_amp_raeth(u8 phyaddr, unsigned int delay)
-{
- u8 all_ana_cal_status;
- u16 ad_cal_comp_out_init;
- int calibration_polarity;
- u16 cal_pair;
- u8 tx_amp_reg_shift;
- u16 reg_temp, val_tmp, l3r25_temp, val_tmp_100;
- u8 tx_amp_temp, tx_amp_reg, cnt = 0, tx_amp_reg_100;
-
- u16 tx_amp_temp_L, tx_amp_temp_M;
- u16 tx_amp_L_100, tx_amp_M_100;
- /* *** Tx Amp Cal start ***/
- tc_phy_write_l_reg(0, 0, 0, 0x0140);
-
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x3e, 0xf808);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x145, 0x5010);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x17d, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x17e, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x17f, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x180, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x181, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x182, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x183, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x184, 0x80f0);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x00db, 0x1000);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x00dc, 0x0001);
- tc_phy_write_dev_reg_raeth(0, 0x1f, 0x300, 0x4);
- tc_phy_write_dev_reg_raeth(0, 0x1f, 0x27a, 0x33);
- tc_phy_write_g_reg(1, 2, 25, 0xf020);
- tc_phy_write_dev_reg_raeth(0, 0x1f, 0x300, 0x14);
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x7000);
- l3r25_temp = tc_phy_read_l_reg(FE_CAL_COMMON, 3, 25);
- l3r25_temp = l3r25_temp | 0x200;
- tc_phy_write_l_reg(FE_CAL_COMMON, 3, 25, l3r25_temp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x11, 0xff00);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x273, 0);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0xc9, 0xffff);
- tc_phy_write_g_reg(1, 2, 25, 0xb020);
-
- for (cal_pair = ANACAL_PAIR_A; cal_pair <= ANACAL_PAIR_D; cal_pair++) {
- tx_amp_temp = 0x20; /* start with 0 dB */
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x7000);
- if (cal_pair == ANACAL_PAIR_A) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x1000);
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x012) & (~0xfc00));
- tx_amp_reg_shift = 10;
- tx_amp_reg = 0x12;
- tx_amp_reg_100 = 0x16;
- } else if (cal_pair == ANACAL_PAIR_B) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0100);
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x017) & (~0x3f00));
- tx_amp_reg_shift = 8;
- tx_amp_reg = 0x17;
- tx_amp_reg_100 = 0x18;
- } else if (cal_pair == ANACAL_PAIR_C) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0010);
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x019) & (~0x3f00));
- tx_amp_reg_shift = 8;
- tx_amp_reg = 0x19;
- tx_amp_reg_100 = 0x20;
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0001);
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x021) & (~0x3f00));
- tx_amp_reg_shift = 8;
- tx_amp_reg = 0x21;
- tx_amp_reg_100 = 0x22;
- }
- /* 1e_12, 1e_17, 1e_19, 1e_21 */
- val_tmp = tx_amp_temp | (tx_amp_temp << tx_amp_reg_shift);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100, val_tmp);
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Tx amp AnaCal ERROR! \r\n");
- }
-/* 1e_17a[8]:ad_cal_comp_out */
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- while (all_ana_cal_status < ANACAL_ERROR) {
- cnt++;
- tx_amp_temp += calibration_polarity;
-
- val_tmp = (tx_amp_temp | (tx_amp_temp << tx_amp_reg_shift));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100, val_tmp);
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Tx amp AnaCal ERROR!\n");
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- } else {
- if ((tx_amp_temp == 0x3f) || (tx_amp_temp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info(" GE Tx amp AnaCal Saturation! \r\n");
- }
- }
- }
- if (all_ana_cal_status == ANACAL_ERROR) {
- pr_info("ANACAL_ERROR\n");
- tx_amp_temp = 0x20;
- val_tmp = (reg_temp | (tx_amp_temp << tx_amp_reg_shift));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg, val_tmp);
- }
-
- if (all_ana_cal_status == ANACAL_FINISH) {
- if (cal_pair == ANACAL_PAIR_A) {
- tx_amp_temp_M = tx_amp_temp + 9;
- tx_amp_temp_L = tx_amp_temp + 18;
- } else if (cal_pair == ANACAL_PAIR_B) {
- tx_amp_temp_M = tx_amp_temp + 8;
- tx_amp_temp_L = tx_amp_temp + 22;
- } else if (cal_pair == ANACAL_PAIR_C) {
- tx_amp_temp_M = tx_amp_temp + 9;
- tx_amp_temp_L = tx_amp_temp + 9;
- } else if (cal_pair == ANACAL_PAIR_D) {
- tx_amp_temp_M = tx_amp_temp + 9;
- tx_amp_temp_L = tx_amp_temp + 9;
- }
- if (tx_amp_temp_L >= 0x3f)
- tx_amp_temp_L = 0x3f;
- if (tx_amp_temp_M >= 0x3f)
- tx_amp_temp_M = 0x3f;
- val_tmp = ((tx_amp_temp_L) |
- ((tx_amp_temp_M) << tx_amp_reg_shift));
- if (cal_pair == ANACAL_PAIR_A) {
- if (tx_amp_temp < 6)
- tx_amp_M_100 = 0;
- else
- tx_amp_M_100 = tx_amp_temp - 6;
-
- if ((tx_amp_temp + 9) >= 0x3f)
- tx_amp_L_100 = 0x3f;
- else
- tx_amp_L_100 = tx_amp_temp + 9;
- val_tmp_100 = ((tx_amp_L_100) |
- ((tx_amp_M_100) << tx_amp_reg_shift));
- } else if (cal_pair == ANACAL_PAIR_B) {
- if (tx_amp_temp < 7)
- tx_amp_M_100 = 0;
- else
- tx_amp_M_100 = tx_amp_temp - 7;
-
- if ((tx_amp_temp + 8) >= 0x3f)
- tx_amp_L_100 = 0x3f;
- else
- tx_amp_L_100 = tx_amp_temp + 8;
- val_tmp_100 = ((tx_amp_L_100) |
- ((tx_amp_M_100) << tx_amp_reg_shift));
- } else if (cal_pair == ANACAL_PAIR_C) {
- if ((tx_amp_temp + 9) >= 0x3f)
- tx_amp_L_100 = 0x3f;
- else
- tx_amp_L_100 = tx_amp_temp + 9;
- tx_amp_M_100 = tx_amp_L_100;
- val_tmp_100 = ((tx_amp_L_100) |
- ((tx_amp_M_100) << tx_amp_reg_shift));
- } else if (cal_pair == ANACAL_PAIR_D) {
- if ((tx_amp_temp + 9) >= 0x3f)
- tx_amp_L_100 = 0x3f;
- else
- tx_amp_L_100 = tx_amp_temp + 9;
-
- tx_amp_M_100 = tx_amp_L_100;
- val_tmp_100 = ((tx_amp_L_100) |
- ((tx_amp_M_100) << tx_amp_reg_shift));
- }
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg, val_tmp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100, val_tmp_100);
-
- if (cal_pair == ANACAL_PAIR_A) {
- pr_info("TX_AMP_PAIR_A : 1e_%x = 0x%x\n",
- tx_amp_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg));
- pr_info("TX_AMP_PAIR_A : 1e_%x = 0x%x\n",
- tx_amp_reg_100,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100));
- } else if (cal_pair == ANACAL_PAIR_B) {
- pr_info("TX_AMP_PAIR_B : 1e_%x = 0x%x\n",
- tx_amp_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg));
- pr_info("TX_AMP_PAIR_B : 1e_%x = 0x%x\n",
- tx_amp_reg_100,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100));
- } else if (cal_pair == ANACAL_PAIR_C) {
- pr_info("TX_AMP_PAIR_C : 1e_%x = 0x%x\n",
- tx_amp_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg));
- pr_info("TX_AMP_PAIR_C : 1e_%x = 0x%x\n",
- tx_amp_reg_100,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100));
-
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
- pr_info("TX_AMP_PAIR_D : 1e_%x = 0x%x\n",
- tx_amp_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg));
- pr_info("TX_AMP_PAIR_D : 1e_%x = 0x%x\n",
- tx_amp_reg_100,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_amp_reg_100));
- }
- }
- }
-
- ge_cal_flag_raeth = 1;
- pr_info("GE_TX_AMP END\n");
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017d, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017e, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017f, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0180, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0181, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0182, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0183, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0184, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x273, 0x2000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0xc9, 0x0fff);
- tc_phy_write_g_reg(1, 2, 25, 0xb020);
- tc_phy_write_dev_reg_raeth(0, 0x1e, 0x145, 0x1000);
-
-/* disable analog calibration circuit */
-/* disable Tx offset calibration circuit */
-/* disable Tx VLD force mode */
-/* disable Tx offset/amplitude calibration circuit */
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dc, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x003e, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0000);
- /* *** Tx Amp Cal end *** */
-}
-
-void ge_cal_tx_offset_raeth(u8 phyaddr, unsigned int delay)
-{
- u8 all_ana_cal_status;
- u16 ad_cal_comp_out_init;
- int calibration_polarity, tx_offset_temp;
- u16 cal_pair, cal_temp;
- u8 tx_offset_reg_shift;
- u16 tx_offset_reg, reg_temp, val_tmp;
- u8 cnt = 0;
-
- tc_phy_write_l_reg(0, 0, 0, 0x2100);
-
- /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
- /* 1e_dc[0]:rg_txvos_calen */
- /* 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x0100);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dc, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0096, 0x8000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x003e, 0xf808);/* 1e_3e */
- tc_phy_write_g_reg(FE_CAL_COMMON, 7, 24, 0x3000);
-
- for (cal_pair = ANACAL_PAIR_A; cal_pair <= ANACAL_PAIR_D; cal_pair++) {
- tx_offset_temp = 0x20;
-
- if (cal_pair == ANACAL_PAIR_A) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x145, 0x5010);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x1000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017d, (0x8000 | DAC_IN_0V));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0181, (0x8000 | DAC_IN_0V));
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0172) & (~0x3f00));
- tx_offset_reg_shift = 8;/* 1e_172[13:8] */
- tx_offset_reg = 0x0172;
-
- } else if (cal_pair == ANACAL_PAIR_B) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x145, 0x5018);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0100);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017e, (0x8000 | DAC_IN_0V));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0182, (0x8000 | DAC_IN_0V));
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0172) & (~0x003f));
- tx_offset_reg_shift = 0;
- tx_offset_reg = 0x0172;/* 1e_172[5:0] */
- } else if (cal_pair == ANACAL_PAIR_C) {
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0010);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017f, (0x8000 | DAC_IN_0V));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0183, (0x8000 | DAC_IN_0V));
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0173) & (~0x3f00));
- tx_offset_reg_shift = 8;
- tx_offset_reg = 0x0173;/* 1e_173[13:8] */
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0180, (0x8000 | DAC_IN_0V));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0184, (0x8000 | DAC_IN_0V));
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0173) & (~0x003f));
- tx_offset_reg_shift = 0;
- tx_offset_reg = 0x0173;/* 1e_173[5:0] */
- }
- /* 1e_172, 1e_173 */
- val_tmp = (reg_temp | (tx_offset_temp << tx_offset_reg_shift));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg, val_tmp);
-
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr); /* delay 20 usec */
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Tx offset AnaCal ERROR! \r\n");
- }
- ad_cal_comp_out_init = tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1;
- if (ad_cal_comp_out_init == 1)
- calibration_polarity = -1;
- else
- calibration_polarity = 1;
-
- cnt = 0;
- tx_offset_temp += calibration_polarity;
- while (all_ana_cal_status < ANACAL_ERROR) {
- cnt++;
- cal_temp = tx_offset_temp;
- val_tmp = (reg_temp | (cal_temp << tx_offset_reg_shift));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg, val_tmp);
-
- all_ana_cal_status = all_ge_ana_cal_wait_raeth(delay, phyaddr);
- if (all_ana_cal_status == 0) {
- all_ana_cal_status = ANACAL_ERROR;
- pr_info(" GE Tx offset AnaCal ERROR! \r\n");
- } else if ((tc_phy_read_g_reg(FE_CAL_COMMON, 7, 24) & 0x1) !=
- ad_cal_comp_out_init) {
- all_ana_cal_status = ANACAL_FINISH;
- } else {
- if ((tx_offset_temp == 0x3f) || (tx_offset_temp == 0x00)) {
- all_ana_cal_status = ANACAL_SATURATION;
- pr_info("GE tx offset ANACAL_SATURATION\n");
- /* tx_amp_temp += calibration_polarity; */
- } else {
- tx_offset_temp += calibration_polarity;
- }
- }
- }
- if (all_ana_cal_status == ANACAL_ERROR) {
- tx_offset_temp = 0x20;
- val_tmp = (reg_temp | (tx_offset_temp << tx_offset_reg_shift));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg, val_tmp);
- }
-
- if (all_ana_cal_status == ANACAL_FINISH) {
- if (cal_pair == ANACAL_PAIR_A) {
- pr_info("TX_OFFSET_PAIR_A : 1e_%x = 0x%x\n",
- tx_offset_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg));
- } else if (cal_pair == ANACAL_PAIR_B) {
- pr_info("TX_OFFSET_PAIR_B : 1e_%x = 0x%x\n",
- tx_offset_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg));
- } else if (cal_pair == ANACAL_PAIR_C) {
- pr_info("TX_OFFSET_PAIR_C : 1e_%x = 0x%x\n",
- tx_offset_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg));
-
- } else {/* if(cal_pair == ANACAL_PAIR_D) */
- pr_info("TX_OFFSET_PAIR_D : 1e_%x = 0x%x\n",
- tx_offset_reg,
- tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, tx_offset_reg));
- }
- }
- }
- ge_cal_tx_offset_raeth_flag = 1;
- clear_ckinv_ana_txvos();
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017d, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017e, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x017f, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0180, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0181, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0182, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0183, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0184, 0x0000);
-/* disable analog calibration circuit */
-/* disable Tx offset calibration circuit */
-/* disable Tx VLD force mode */
-/* disable Tx offset/amplitude calibration circuit */
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00db, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dc, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x003e, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x00dd, 0x0000);
-}
-
-void do_ge_phy_all_analog_cal(u8 phyaddr)
-{
- u16 reg0_temp, dev1e_145_temp, reg_temp;
- u16 reg_tmp;
-
- tc_mii_write(phyaddr, 0x1f, 0x0000);/* g0 */
- reg0_temp = tc_mii_read(phyaddr, 0x0);/* keep the default value */
-/* set [12]AN disable, [8]full duplex, [13/6]1000Mbps */
- tc_mii_write(phyaddr, 0x0, 0x0140);
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x0100, 0xc000);/* BG voltage output */
- dev1e_145_temp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0145);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0145, 0x1010);/* fix mdi */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0185, 0x0000);/* disable tx slew control */
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x27c, 0x1f1f);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x27c, 0x3300);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x273, 0);
-
- reg_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x11);
- reg_tmp = reg_tmp | (0xf << 12);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x11, reg_tmp);
-
- /* calibration start ============ */
- ge_cal_flag_raeth = 1; /*GE calibration not calibration*/
- while (ge_cal_flag_raeth == 0)
- ge_cal_rext_raeth_raeth(phyaddr, 100);
-
- /* *** R50 Cal start ***************************** */
- /*phyaddress = 0*/
- ge_cal_r50_raeth(phyaddr, CALDLY);
- /* *** R50 Cal end *** */
-
- /* *** Tx offset Cal start *********************** */
- ge_cal_tx_offset_raeth(phyaddr, CALDLY);
- /* *** Tx offset Cal end *** */
-
- /* *** Tx Amp Cal start *** */
- ge_cal_tx_amp_raeth(phyaddr, CALDLY);
- /* *** Tx Amp Cal end *** */
-
- /* *** Rx offset Cal start *************** */
- /* 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0096, 0x8000);
- /* tx/rx_cal_criteria_value */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0037, 0x0033);
- /* [14]: bypass all calibration, [11]: bypass adc offset cal analog */
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0039) & (~0x4800));
- /* rx offset cal by Hw setup */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0039, reg_temp);
- /* [12]: enable rtune calibration */
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1f, 0x0107) & (~0x1000));
- /* disable rtune calibration */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x0107, reg_temp);
- /* 1e_171[8:7]: bypass tx/rx dc offset cancellation process */
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0171) & (~0x0180));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0171, (reg_temp | 0x0180));
- reg_temp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0039);
- /* rx offset calibration start */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0039, (reg_temp | 0x2000));
- /* rx offset calibration end */
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0039, (reg_temp & (~0x2000)));
- mdelay(10); /* mdelay for Hw calibration finish */
- reg_temp = (tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x0171) & (~0x0180));
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0171, reg_temp);
-
- tc_mii_write(phyaddr, 0x0, reg0_temp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x0100, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0145, dev1e_145_temp);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x273, 0x2000);
- /* *** Rx offset Cal end *** */
- /*eye pic*/
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x0, 0x018d);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x1, 0x01c7);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x2, 0x01c0);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3, 0x003a);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x4, 0x0206);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x5, 0x0000);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x6, 0x038a);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x7, 0x03c8);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x8, 0x03c0);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x9, 0x0235);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0xa, 0x0008);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0xb, 0x0000);
-
- /*tmp maybe changed*/
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x27c, 0x1111);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x27b, 0x47);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1f, 0x273, 0x2200);
-
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3a8, 0x0810);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3aa, 0x0008);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3ab, 0x0810);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3ad, 0x0008);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3ae, 0x0106);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3b0, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3b1, 0x0106);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3b3, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x18c, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x18d, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x18e, 0x0001);
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x18f, 0x0001);
-
- /*da_tx_bias1_b_tx_standby = 5'b10 (dev1eh_reg3aah[12:8])*/
- reg_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x3aa);
- reg_tmp = reg_tmp & ~(0x1f00);
- reg_tmp = reg_tmp | 0x2 << 8;
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3aa, reg_tmp);
-
- /*da_tx_bias1_a_tx_standby = 5'b10 (dev1eh_reg3a9h[4:0])*/
- reg_tmp = tc_phy_read_dev_reg_raeth(phyaddr, 0x1e, 0x3a9);
- reg_tmp = reg_tmp & ~(0x1f);
- reg_tmp = reg_tmp | 0x2;
- tc_phy_write_dev_reg_raeth(phyaddr, 0x1e, 0x3a9, reg_tmp);
-}
-
-#if 0
-static void mt7622_ephy_cal(void)
-{
- int i;
- unsigned long t_s, t_e;
-
- t_s = jiffies;
- for (i = 0; i < 5; i++)
- do_fe_phy_all_analog_cal(i);
- t_e = jiffies;
- if (show_time)
- pr_info("cal time = %lu\n", (t_e - t_s) * 4);
-}
-
-static void leopard_ephy_cal(void)
-{
- int i, dbg;
- unsigned long t_s, t_e;
-
- dbg = 1;
- if (dbg) {
- t_s = jiffies;
- for (i = 1; i < 5; i++)
- do_fe_phy_all_analog_cal(i);
-
- do_ge_phy_all_analog_cal(0);
-
- t_e = jiffies;
- }
- if (show_time)
- pr_info("cal time = %lu\n", (t_e - t_s) * 4);
-}
-#endif
-static void wait_loop(void)
-{
- int i;
- int read_data;
-
- for (i = 0; i < 320; i = i + 1)
- read_data = sys_reg_read(RALINK_ETH_SW_BASE + 0x108);
-}
-
-static void trgmii_calibration_7623(void)
-{
- /* minimum delay for all correct */
- unsigned int tap_a[5] = {
- 0, 0, 0, 0, 0
- };
- /* maximum delay for all correct */
- unsigned int tap_b[5] = {
- 0, 0, 0, 0, 0
- };
- unsigned int final_tap[5];
- unsigned int rxc_step_size;
- unsigned int rxd_step_size;
- unsigned int read_data;
- unsigned int tmp;
- unsigned int rd_wd;
- int i;
- unsigned int err_cnt[5];
- unsigned int init_toggle_data;
- unsigned int err_flag[5];
- unsigned int err_total_flag;
- unsigned int training_word;
- unsigned int rd_tap;
-
- void __iomem *TRGMII_7623_base;
- void __iomem *TRGMII_7623_RD_0;
- void __iomem *temp_addr;
-
- TRGMII_7623_base = ETHDMASYS_ETH_SW_BASE + 0x0300;
- TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10;
- rxd_step_size = 0x1;
- rxc_step_size = 0x4;
- init_toggle_data = 0x00000055;
- training_word = 0x000000AC;
-
- /* RX clock gating in MT7623 */
- reg_bit_zero(TRGMII_7623_base + 0x04, 30, 2);
- /* Assert RX reset in MT7623 */
- reg_bit_one(TRGMII_7623_base + 0x00, 31, 1);
- /* Set TX OE edge in MT7623 */
- reg_bit_one(TRGMII_7623_base + 0x78, 13, 1);
- /* Disable RX clock gating in MT7623 */
- reg_bit_one(TRGMII_7623_base + 0x04, 30, 2);
- /* Release RX reset in MT7623 */
- reg_bit_zero(TRGMII_7623_base, 31, 1);
-
- for (i = 0; i < 5; i++)
- /* Set bslip_en = 1 */
- reg_bit_one(TRGMII_7623_RD_0 + i * 8, 31, 1);
-
- /* Enable Training Mode in MT7530 */
- mii_mgr_read(0x1F, 0x7A40, &read_data);
- read_data |= 0xc0000000;
- mii_mgr_write(0x1F, 0x7A40, read_data);
-
- err_total_flag = 0;
- read_data = 0x0;
- while (err_total_flag == 0 && read_data != 0x68) {
- /* Enable EDGE CHK in MT7623 */
- for (i = 0; i < 5; i++) {
- reg_bit_zero(TRGMII_7623_RD_0 + i * 8, 28, 4);
- reg_bit_one(TRGMII_7623_RD_0 + i * 8, 31, 1);
- }
- wait_loop();
- err_total_flag = 1;
- for (i = 0; i < 5; i++) {
- tmp = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- err_cnt[i] = (tmp >> 8) & 0x0000000f;
-
- tmp = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- rd_wd = (tmp >> 16) & 0x000000ff;
-
- if (err_cnt[i] != 0)
- err_flag[i] = 1;
- else if (rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
- err_total_flag = err_flag[i] & err_total_flag;
- }
-
- /* Disable EDGE CHK in MT7623 */
- for (i = 0; i < 5; i++) {
- reg_bit_one(TRGMII_7623_RD_0 + i * 8, 30, 1);
- reg_bit_zero(TRGMII_7623_RD_0 + i * 8, 28, 2);
- reg_bit_zero(TRGMII_7623_RD_0 + i * 8, 31, 1);
- }
- wait_loop();
- /* Adjust RXC delay */
- /* RX clock gating in MT7623 */
- reg_bit_zero(TRGMII_7623_base + 0x04, 30, 2);
- read_data = sys_reg_read(TRGMII_7623_base);
- if (err_total_flag == 0) {
- tmp = (read_data & 0x0000007f) + rxc_step_size;
- read_data >>= 8;
- read_data &= 0xffffff80;
- read_data |= tmp;
- read_data <<= 8;
- read_data &= 0xffffff80;
- read_data |= tmp;
- sys_reg_write(TRGMII_7623_base, read_data);
- } else {
- tmp = (read_data & 0x0000007f) + 16;
- read_data >>= 8;
- read_data &= 0xffffff80;
- read_data |= tmp;
- read_data <<= 8;
- read_data &= 0xffffff80;
- read_data |= tmp;
- sys_reg_write(TRGMII_7623_base, read_data);
- }
- read_data &= 0x000000ff;
- /* Disable RX clock gating in MT7623 */
- reg_bit_one(TRGMII_7623_base + 0x04, 30, 2);
- for (i = 0; i < 5; i++)
- reg_bit_one(TRGMII_7623_RD_0 + i * 8, 31, 1);
- }
- /* Read RD_WD MT7623 */
- for (i = 0; i < 5; i++) {
- temp_addr = TRGMII_7623_RD_0 + i * 8;
- rd_tap = 0;
- while (err_flag[i] != 0 && rd_tap != 128) {
- /* Enable EDGE CHK in MT7623 */
- tmp = sys_reg_read(temp_addr);
- tmp |= 0x40000000;
- reg_bit_zero(temp_addr, 28, 4);
- reg_bit_one(temp_addr, 30, 1);
- wait_loop();
- read_data = sys_reg_read(temp_addr);
- /* Read MT7623 Errcnt */
- err_cnt[i] = (read_data >> 8) & 0x0000000f;
- rd_wd = (read_data >> 16) & 0x000000ff;
- if (err_cnt[i] != 0 || rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
- /* Disable EDGE CHK in MT7623 */
- reg_bit_zero(temp_addr, 28, 2);
- reg_bit_zero(temp_addr, 31, 1);
- tmp |= 0x40000000;
- sys_reg_write(temp_addr, tmp & 0x4fffffff);
- wait_loop();
- if (err_flag[i] != 0) {
- /* Add RXD delay in MT7623 */
- rd_tap = (read_data & 0x7f) + rxd_step_size;
-
- read_data = (read_data & 0xffffff80) | rd_tap;
- sys_reg_write(temp_addr, read_data);
- tap_a[i] = rd_tap;
- } else {
- rd_tap = (read_data & 0x0000007f) + 48;
- read_data = (read_data & 0xffffff80) | rd_tap;
- sys_reg_write(temp_addr, read_data);
- }
- }
- pr_info("MT7623 %dth bit Tap_a = %d\n", i, tap_a[i]);
- }
- for (i = 0; i < 5; i++) {
- while ((err_flag[i] == 0) && (rd_tap != 128)) {
- read_data = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- /* Add RXD delay in MT7623 */
- rd_tap = (read_data & 0x7f) + rxd_step_size;
-
- read_data = (read_data & 0xffffff80) | rd_tap;
- sys_reg_write(TRGMII_7623_RD_0 + i * 8, read_data);
-
- /* Enable EDGE CHK in MT7623 */
- tmp = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- tmp |= 0x40000000;
- sys_reg_write(TRGMII_7623_RD_0 + i * 8,
- (tmp & 0x4fffffff));
- wait_loop();
- read_data = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- /* Read MT7623 Errcnt */
- err_cnt[i] = (read_data >> 8) & 0xf;
- rd_wd = (read_data >> 16) & 0x000000ff;
- if (err_cnt[i] != 0 || rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
-
- /* Disable EDGE CHK in MT7623 */
- tmp = sys_reg_read(TRGMII_7623_RD_0 + i * 8);
- tmp |= 0x40000000;
- sys_reg_write(TRGMII_7623_RD_0 + i * 8,
- (tmp & 0x4fffffff));
- wait_loop();
- }
- tap_b[i] = rd_tap; /* -rxd_step_size; */
- pr_info("MT7623 %dth bit Tap_b = %d\n", i, tap_b[i]);
- /* Calculate RXD delay = (TAP_A + TAP_B)/2 */
- final_tap[i] = (tap_a[i] + tap_b[i]) / 2;
- read_data = (read_data & 0xffffff80) | final_tap[i];
- sys_reg_write(TRGMII_7623_RD_0 + i * 8, read_data);
- }
-
- mii_mgr_read(0x1F, 0x7A40, &read_data);
- read_data &= 0x3fffffff;
- mii_mgr_write(0x1F, 0x7A40, read_data);
-}
-
-static void trgmii_calibration_7530(void)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned int tap_a[5] = {
- 0, 0, 0, 0, 0
- };
- unsigned int tap_b[5] = {
- 0, 0, 0, 0, 0
- };
- unsigned int final_tap[5];
- unsigned int rxc_step_size;
- unsigned int rxd_step_size;
- unsigned int read_data;
- unsigned int tmp = 0;
- int i;
- unsigned int err_cnt[5];
- unsigned int rd_wd;
- unsigned int init_toggle_data;
- unsigned int err_flag[5];
- unsigned int err_total_flag;
- unsigned int training_word;
- unsigned int rd_tap;
-
- void __iomem *TRGMII_7623_base;
- u32 TRGMII_7530_RD_0;
- u32 TRGMII_7530_base;
- u32 TRGMII_7530_TX_base;
-
- TRGMII_7623_base = ETHDMASYS_ETH_SW_BASE + 0x0300;
- TRGMII_7530_base = 0x7A00;
- TRGMII_7530_RD_0 = TRGMII_7530_base + 0x10;
- rxd_step_size = 0x1;
- rxc_step_size = 0x8;
- init_toggle_data = 0x00000055;
- training_word = 0x000000AC;
-
- TRGMII_7530_TX_base = TRGMII_7530_base + 0x50;
-
- reg_bit_one(TRGMII_7623_base + 0x40, 31, 1);
- mii_mgr_read(0x1F, 0x7a10, &read_data);
-
- /* RX clock gating in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base + 0x04, &read_data);
- read_data &= 0x3fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_base + 0x04, read_data);
-
- /* Set TX OE edge in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base + 0x78, &read_data);
- read_data |= 0x00002000;
- mii_mgr_write(0x1F, TRGMII_7530_base + 0x78, read_data);
-
- /* Assert RX reset in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
- read_data |= 0x80000000;
- mii_mgr_write(0x1F, TRGMII_7530_base, read_data);
-
- /* Release RX reset in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
- read_data &= 0x7fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_base, read_data);
-
- /* Disable RX clock gating in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base + 0x04, &read_data);
- read_data |= 0xC0000000;
- mii_mgr_write(0x1F, TRGMII_7530_base + 0x04, read_data);
-
- /*Enable Training Mode in MT7623 */
- reg_bit_zero(TRGMII_7623_base + 0x40, 30, 1);
- if (ei_local->architecture & GE1_TRGMII_FORCE_2000)
- reg_bit_one(TRGMII_7623_base + 0x40, 30, 2);
- else
- reg_bit_one(TRGMII_7623_base + 0x40, 31, 1);
- reg_bit_zero(TRGMII_7623_base + 0x78, 8, 4);
- reg_bit_zero(TRGMII_7623_base + 0x50, 8, 4);
- reg_bit_zero(TRGMII_7623_base + 0x58, 8, 4);
- reg_bit_zero(TRGMII_7623_base + 0x60, 8, 4);
- reg_bit_zero(TRGMII_7623_base + 0x68, 8, 4);
- reg_bit_zero(TRGMII_7623_base + 0x70, 8, 4);
- reg_bit_one(TRGMII_7623_base + 0x78, 11, 1);
-
- err_total_flag = 0;
- read_data = 0x0;
- while (err_total_flag == 0 && (read_data != 0x68)) {
- /* Enable EDGE CHK in MT7530 */
- for (i = 0; i < 5; i++) {
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &err_cnt[i]);
- err_cnt[i] >>= 8;
- err_cnt[i] &= 0x0000ff0f;
- rd_wd = err_cnt[i] >> 8;
- rd_wd &= 0x000000ff;
- err_cnt[i] &= 0x0000000f;
- if (err_cnt[i] != 0)
- err_flag[i] = 1;
- else if (rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
-
- if (i == 0)
- err_total_flag = err_flag[i];
- else
- err_total_flag = err_flag[i] & err_total_flag;
- /* Disable EDGE CHK in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- }
- /*Adjust RXC delay */
- if (err_total_flag == 0) {
- /* Assert RX reset in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
- read_data |= 0x80000000;
- mii_mgr_write(0x1F, TRGMII_7530_base, read_data);
-
- /* RX clock gating in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base + 0x04, &read_data);
- read_data &= 0x3fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_base + 0x04, read_data);
-
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
- tmp = read_data;
- tmp &= 0x0000007f;
- tmp += rxc_step_size;
- read_data &= 0xffffff80;
- read_data |= tmp;
- mii_mgr_write(0x1F, TRGMII_7530_base, read_data);
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
-
- /* Release RX reset in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base, &read_data);
- read_data &= 0x7fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_base, read_data);
-
- /* Disable RX clock gating in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_base + 0x04, &read_data);
- read_data |= 0xc0000000;
- mii_mgr_write(0x1F, TRGMII_7530_base + 0x04, read_data);
- }
- read_data = tmp;
- }
- /* Read RD_WD MT7530 */
- for (i = 0; i < 5; i++) {
- rd_tap = 0;
- while (err_flag[i] != 0 && rd_tap != 128) {
- /* Enable EDGE CHK in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- err_cnt[i] = (read_data >> 8) & 0x0000000f;
- rd_wd = (read_data >> 16) & 0x000000ff;
- if (err_cnt[i] != 0 || rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
-
- if (err_flag[i] != 0) {
- /* Add RXD delay in MT7530 */
- rd_tap = (read_data & 0x7f) + rxd_step_size;
- read_data = (read_data & 0xffffff80) | rd_tap;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- tap_a[i] = rd_tap;
- } else {
- /* Record the min delay TAP_A */
- tap_a[i] = (read_data & 0x0000007f);
- rd_tap = tap_a[i] + 0x4;
- read_data = (read_data & 0xffffff80) | rd_tap;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- }
-
- /* Disable EDGE CHK in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- }
- pr_info("MT7530 %dth bit Tap_a = %d\n", i, tap_a[i]);
- }
- for (i = 0; i < 5; i++) {
- rd_tap = 0;
- while (err_flag[i] == 0 && (rd_tap != 128)) {
- /* Enable EDGE CHK in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- err_cnt[i] = (read_data >> 8) & 0x0000000f;
- rd_wd = (read_data >> 16) & 0x000000ff;
- if (err_cnt[i] != 0 || rd_wd != 0x55)
- err_flag[i] = 1;
- else
- err_flag[i] = 0;
-
- if (err_flag[i] == 0 && (rd_tap != 128)) {
- /* Add RXD delay in MT7530 */
- rd_tap = (read_data & 0x7f) + rxd_step_size;
- read_data = (read_data & 0xffffff80) | rd_tap;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- }
- /* Disable EDGE CHK in MT7530 */
- mii_mgr_read(0x1F, TRGMII_7530_RD_0 + i * 8,
- &read_data);
- read_data |= 0x40000000;
- read_data &= 0x4fffffff;
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8,
- read_data);
- wait_loop();
- }
- tap_b[i] = rd_tap; /* - rxd_step_size; */
- pr_info("MT7530 %dth bit Tap_b = %d\n", i, tap_b[i]);
- /* Calculate RXD delay = (TAP_A + TAP_B)/2 */
- final_tap[i] = (tap_a[i] + tap_b[i]) / 2;
- read_data = (read_data & 0xffffff80) | final_tap[i];
- mii_mgr_write(0x1F, TRGMII_7530_RD_0 + i * 8, read_data);
- }
- if (ei_local->architecture & GE1_TRGMII_FORCE_2000)
- reg_bit_zero(TRGMII_7623_base + 0x40, 31, 1);
- else
- reg_bit_zero(TRGMII_7623_base + 0x40, 30, 2);
-}
-
-static void mt7530_trgmii_clock_setting(u32 xtal_mode)
-{
- u32 reg_value;
- /* TRGMII Clock */
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x1);
- if (xtal_mode == 1) { /* 25MHz */
- mii_mgr_write_cl45(0, 0x1f, 0x404, MT7530_TRGMII_PLL_25M);
- } else if (xtal_mode == 2) { /* 40MHz */
- mii_mgr_write_cl45(0, 0x1f, 0x404, MT7530_TRGMII_PLL_40M);
- }
- mii_mgr_write_cl45(0, 0x1f, 0x405, 0);
- if (xtal_mode == 1) /* 25MHz */
- mii_mgr_write_cl45(0, 0x1f, 0x409, 0x57);
- else
- mii_mgr_write_cl45(0, 0x1f, 0x409, 0x87);
-
- if (xtal_mode == 1) /* 25MHz */
- mii_mgr_write_cl45(0, 0x1f, 0x40a, 0x57);
- else
- mii_mgr_write_cl45(0, 0x1f, 0x40a, 0x87);
-
- mii_mgr_write_cl45(0, 0x1f, 0x403, 0x1800);
- mii_mgr_write_cl45(0, 0x1f, 0x403, 0x1c00);
- mii_mgr_write_cl45(0, 0x1f, 0x401, 0xc020);
- mii_mgr_write_cl45(0, 0x1f, 0x406, 0xa030);
- mii_mgr_write_cl45(0, 0x1f, 0x406, 0xa038);
- usleep_range(120, 130); /* for MT7623 bring up test */
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x3);
-
- mii_mgr_read(31, 0x7830, ®_value);
- reg_value &= 0xFFFFFFFC;
- reg_value |= 0x00000001;
- mii_mgr_write(31, 0x7830, reg_value);
-
- mii_mgr_read(31, 0x7a40, ®_value);
- reg_value &= ~(0x1 << 30);
- reg_value &= ~(0x1 << 28);
- mii_mgr_write(31, 0x7a40, reg_value);
-
- mii_mgr_write(31, 0x7a78, 0x55);
- usleep_range(100, 110); /* for mt7623 bring up test */
-
- /* Release MT7623 RXC reset */
- reg_bit_zero(ETHDMASYS_ETH_SW_BASE + 0x0300, 31, 1);
-
- trgmii_calibration_7623();
- trgmii_calibration_7530();
- /* Assert RX reset in MT7623 */
- reg_bit_one(ETHDMASYS_ETH_SW_BASE + 0x0300, 31, 1);
- /* Release RX reset in MT7623 */
- reg_bit_zero(ETHDMASYS_ETH_SW_BASE + 0x0300, 31, 1);
- mii_mgr_read(31, 0x7a00, ®_value);
- reg_value |= (0x1 << 31);
- mii_mgr_write(31, 0x7a00, reg_value);
- mdelay(1);
- reg_value &= ~(0x1 << 31);
- mii_mgr_write(31, 0x7a00, reg_value);
- mdelay(100);
-}
-
-void trgmii_set_7621(void)
-{
- u32 val = 0;
- u32 val_0 = 0;
-
- val = sys_reg_read(RSTCTRL);
- /* MT7621 need to reset GMAC and FE first */
- val = val | RALINK_FE_RST | RALINK_ETH_RST;
- sys_reg_write(RSTCTRL, val);
-
- /* set TRGMII clock */
- val_0 = sys_reg_read(CLK_CFG_0);
- val_0 &= 0xffffff9f;
- val_0 |= (0x1 << 5);
- sys_reg_write(CLK_CFG_0, val_0);
- mdelay(1);
- val_0 = sys_reg_read(CLK_CFG_0);
- pr_info("set CLK_CFG_0 = 0x%x!!!!!!!!!!!!!!!!!!1\n", val_0);
- val = val & ~(RALINK_FE_RST | RALINK_ETH_RST);
- sys_reg_write(RSTCTRL, val);
- pr_info("trgmii_set_7621 Completed!!\n");
-}
-
-void trgmii_set_7530(void)
-{
- u32 regValue;
-
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x404);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_read(31, 0x7800, ®Value);
- regValue = (regValue >> 9) & 0x3;
- if (regValue == 0x3)
- mii_mgr_write(0, 14, 0x0C00);/*25Mhz XTAL for 150Mhz CLK */
- else if (regValue == 0x2)
- mii_mgr_write(0, 14, 0x0780);/*40Mhz XTAL for 150Mhz CLK */
-
- mdelay(1);
-
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x409);
- mii_mgr_write(0, 13, 0x401f);
- if (regValue == 0x3) /* 25MHz */
- mii_mgr_write(0, 14, 0x57);
- else
- mii_mgr_write(0, 14, 0x87);
- mdelay(1);
-
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x40a);
- mii_mgr_write(0, 13, 0x401f);
- if (regValue == 0x3) /* 25MHz */
- mii_mgr_write(0, 14, 0x57);
- else
- mii_mgr_write(0, 14, 0x87);
-
-/* PLL BIAS en */
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x403);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_write(0, 14, 0x1800);
- mdelay(1);
-
-/* BIAS LPF en */
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x403);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_write(0, 14, 0x1c00);
-
-/* sys PLL en */
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x401);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_write(0, 14, 0xc020);
-
-/* LCDDDS PWDS */
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x406);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_write(0, 14, 0xa030);
- mdelay(1);
-
-/* GSW_2X_CLK */
- mii_mgr_write(0, 13, 0x1f);
- mii_mgr_write(0, 14, 0x410);
- mii_mgr_write(0, 13, 0x401f);
- mii_mgr_write(0, 14, 0x0003);
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x0003);
-
-/* enable P6 */
- mii_mgr_write(31, 0x3600, 0x5e33b);
-
-/* enable TRGMII */
- mii_mgr_write(31, 0x7830, 0x1);
-
- pr_info("trgmii_set_7530 Completed!!\n");
-}
-
-static void is_switch_vlan_table_busy(void)
-{
- int j = 0;
- unsigned int value = 0;
-
- for (j = 0; j < 20; j++) {
- mii_mgr_read(31, 0x90, &value);
- if ((value & 0x80000000) == 0) { /* table busy */
- break;
- }
- mdelay(70);
- }
- if (j == 20)
- pr_info("set vlan timeout value=0x%x.\n", value);
-}
-
-static void lan_wan_partition(void)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- /*Set MT7530 */
- if (ei_local->architecture & WAN_AT_P0) {
- pr_info("set LAN/WAN WLLLL\n");
- /*WLLLL, wan at P0 */
- /*LAN/WAN ports as security mode */
- mii_mgr_write(31, 0x2004, 0xff0003); /* port0 */
- mii_mgr_write(31, 0x2104, 0xff0003); /* port1 */
- mii_mgr_write(31, 0x2204, 0xff0003); /* port2 */
- mii_mgr_write(31, 0x2304, 0xff0003); /* port3 */
- mii_mgr_write(31, 0x2404, 0xff0003); /* port4 */
- mii_mgr_write(31, 0x2504, 0xff0003); /* port5 */
- mii_mgr_write(31, 0x2604, 0xff0003); /* port6 */
-
- /*set PVID */
- mii_mgr_write(31, 0x2014, 0x10002); /* port0 */
- mii_mgr_write(31, 0x2114, 0x10001); /* port1 */
- mii_mgr_write(31, 0x2214, 0x10001); /* port2 */
- mii_mgr_write(31, 0x2314, 0x10001); /* port3 */
- mii_mgr_write(31, 0x2414, 0x10001); /* port4 */
- mii_mgr_write(31, 0x2514, 0x10002); /* port5 */
- mii_mgr_write(31, 0x2614, 0x10001); /* port6 */
- /*port6 */
- /*VLAN member */
- is_switch_vlan_table_busy();
- mii_mgr_write(31, 0x94, 0x405e0001); /* VAWD1 */
- mii_mgr_write(31, 0x90, 0x80001001); /* VTCR, VID=1 */
- is_switch_vlan_table_busy();
-
- mii_mgr_write(31, 0x94, 0x40210001); /* VAWD1 */
- mii_mgr_write(31, 0x90, 0x80001002); /* VTCR, VID=2 */
- is_switch_vlan_table_busy();
- }
- if (ei_local->architecture & WAN_AT_P4) {
- pr_info("set LAN/WAN LLLLW\n");
- /*LLLLW, wan at P4 */
- /*LAN/WAN ports as security mode */
- mii_mgr_write(31, 0x2004, 0xff0003); /* port0 */
- mii_mgr_write(31, 0x2104, 0xff0003); /* port1 */
- mii_mgr_write(31, 0x2204, 0xff0003); /* port2 */
- mii_mgr_write(31, 0x2304, 0xff0003); /* port3 */
- mii_mgr_write(31, 0x2404, 0xff0003); /* port4 */
- mii_mgr_write(31, 0x2504, 0xff0003); /* port5 */
- mii_mgr_write(31, 0x2604, 0xff0003); /* port6 */
-
- /*set PVID */
- mii_mgr_write(31, 0x2014, 0x10001); /* port0 */
- mii_mgr_write(31, 0x2114, 0x10001); /* port1 */
- mii_mgr_write(31, 0x2214, 0x10001); /* port2 */
- mii_mgr_write(31, 0x2314, 0x10001); /* port3 */
- mii_mgr_write(31, 0x2414, 0x10002); /* port4 */
- mii_mgr_write(31, 0x2514, 0x10002); /* port5 */
- mii_mgr_write(31, 0x2614, 0x10001); /* port6 */
-
- /*VLAN member */
- is_switch_vlan_table_busy();
- mii_mgr_write(31, 0x94, 0x404f0001); /* VAWD1 */
- mii_mgr_write(31, 0x90, 0x80001001); /* VTCR, VID=1 */
- is_switch_vlan_table_busy();
- mii_mgr_write(31, 0x94, 0x40300001); /* VAWD1 */
- mii_mgr_write(31, 0x90, 0x80001002); /* VTCR, VID=2 */
- is_switch_vlan_table_busy();
- }
-}
-
-static void mt7530_phy_setting(void)
-{
- u32 i;
- u32 reg_value;
-
- for (i = 0; i < 5; i++) {
- /* Disable EEE */
- mii_mgr_write_cl45(i, 0x7, 0x3c, 0);
- /* Enable HW auto downshift */
- mii_mgr_write(i, 31, 0x1);
- mii_mgr_read(i, 0x14, ®_value);
- reg_value |= (1 << 4);
- mii_mgr_write(i, 0x14, reg_value);
- /* Increase SlvDPSready time */
- mii_mgr_write(i, 31, 0x52b5);
- mii_mgr_write(i, 16, 0xafae);
- mii_mgr_write(i, 18, 0x2f);
- mii_mgr_write(i, 16, 0x8fae);
- /* Incease post_update_timer */
- mii_mgr_write(i, 31, 0x3);
- mii_mgr_write(i, 17, 0x4b);
- /* Adjust 100_mse_threshold */
- mii_mgr_write_cl45(i, 0x1e, 0x123, 0xffff);
- /* Disable mcc */
- mii_mgr_write_cl45(i, 0x1e, 0xa6, 0x300);
- }
-}
-
-static void setup_internal_gsw(void)
-{
- void __iomem *gpio_base_virt = ioremap(ETH_GPIO_BASE, 0x1000);
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u32 reg_value;
- u32 xtal_mode;
- u32 i;
-
- if (ei_local->architecture &
- (GE1_TRGMII_FORCE_2000 | GE1_TRGMII_FORCE_2600))
- reg_bit_one(RALINK_SYSCTL_BASE + 0x2c, 11, 1);
- else
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x2c, 11, 1);
- reg_bit_one(ETHDMASYS_ETH_SW_BASE + 0x0390, 1, 1); /* TRGMII mode */
-
- #if defined(CONFIG_GE1_RGMII_FORCE_1200)
-
- if (ei_local->chip_name == MT7621_FE)
- trgmii_set_7621();
-
- #endif
-
- /*Hardware reset Switch */
-
- reg_bit_zero((void __iomem *)gpio_base_virt + 0x520, 1, 1);
- mdelay(1);
- reg_bit_one((void __iomem *)gpio_base_virt + 0x520, 1, 1);
- mdelay(100);
-
- /* Assert MT7623 RXC reset */
- reg_bit_one(ETHDMASYS_ETH_SW_BASE + 0x0300, 31, 1);
- /*For MT7623 reset MT7530 */
- reg_bit_one(RALINK_SYSCTL_BASE + 0x34, 2, 1);
- mdelay(1);
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x34, 2, 1);
- mdelay(100);
-
- /* Wait for Switch Reset Completed */
- for (i = 0; i < 100; i++) {
- mdelay(10);
- mii_mgr_read(31, 0x7800, ®_value);
- if (reg_value != 0) {
- pr_info("MT7530 Reset Completed!!\n");
- break;
- }
- if (i == 99)
- pr_info("MT7530 Reset Timeout!!\n");
- }
-
- for (i = 0; i <= 4; i++) {
- /*turn off PHY */
- mii_mgr_read(i, 0x0, ®_value);
- reg_value |= (0x1 << 11);
- mii_mgr_write(i, 0x0, reg_value);
- }
- mii_mgr_write(31, 0x7000, 0x3); /* reset switch */
- usleep_range(100, 110);
-
- #if defined(CONFIG_GE1_RGMII_FORCE_1200)
-
- if (ei_local->chip_name == MT7621_FE) {
- trgmii_set_7530();
- /* enable MDIO to control MT7530 */
- reg_value = sys_reg_read(RALINK_SYSCTL_BASE + 0x60);
- reg_value &= ~(0x3 << 12);
- sys_reg_write(RALINK_SYSCTL_BASE + 0x60, reg_value);
- }
-
- #endif
-
- /* (GE1, Force 1000M/FD, FC ON) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x100, 0x2105e33b);
- mii_mgr_write(31, 0x3600, 0x5e33b);
- mii_mgr_read(31, 0x3600, ®_value);
- /* (GE2, Link down) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x200, 0x00008000);
-
- mii_mgr_read(31, 0x7804, ®_value);
- reg_value &= ~(1 << 8); /* Enable Port 6 */
- reg_value |= (1 << 6); /* Disable Port 5 */
- reg_value |= (1 << 13); /* Port 5 as GMAC, no Internal PHY */
-
- if (ei_local->architecture & GMAC2) {
- /*RGMII2=Normal mode */
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x60, 15, 1);
-
- /*GMAC2= RGMII mode */
- reg_bit_zero(SYSCFG1, 14, 2);
- if (ei_local->architecture & GE2_RGMII_AN) {
- mii_mgr_write(31, 0x3500, 0x56300);
- /* (GE2, auto-polling) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x200, 0x21056300);
- reg_value |= (1 << 6); /* disable MT7530 P5 */
- enable_auto_negotiate(ei_local);
-
- } else {
- /* MT7530 P5 Force 1000 */
- mii_mgr_write(31, 0x3500, 0x5e33b);
- /* (GE2, Force 1000) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x200, 0x2105e33b);
- reg_value &= ~(1 << 6); /* enable MT7530 P5 */
- reg_value |= ((1 << 7) | (1 << 13) | (1 << 16));
- if (ei_local->architecture & WAN_AT_P0)
- reg_value |= (1 << 20);
- else
- reg_value &= ~(1 << 20);
- }
- }
- reg_value &= ~(1 << 5);
- reg_value |= (1 << 16); /* change HW-TRAP */
- pr_info("change HW-TRAP to 0x%x\n", reg_value);
- mii_mgr_write(31, 0x7804, reg_value);
- mii_mgr_read(31, 0x7800, ®_value);
- reg_value = (reg_value >> 9) & 0x3;
- if (reg_value == 0x3) { /* 25Mhz Xtal */
- xtal_mode = 1;
- /*Do Nothing */
- } else if (reg_value == 0x2) { /* 40Mhz */
- xtal_mode = 2;
- /* disable MT7530 core clock */
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x0);
-
- mii_mgr_write_cl45(0, 0x1f, 0x40d, 0x2020);
- mii_mgr_write_cl45(0, 0x1f, 0x40e, 0x119);
- mii_mgr_write_cl45(0, 0x1f, 0x40d, 0x2820);
- usleep_range(20, 30); /* suggest by CD */
- #if defined(CONFIG_GE1_RGMII_FORCE_1200)
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x3);
- #else
- mii_mgr_write_cl45(0, 0x1f, 0x410, 0x1);
- #endif
-
- } else {
- xtal_mode = 3;
- /* TODO */}
-
- /* set MT7530 central align */
- #if !defined(CONFIG_GE1_RGMII_FORCE_1200) /* for RGMII 1000HZ */
- mii_mgr_read(31, 0x7830, ®_value);
- reg_value &= ~1;
- reg_value |= 1 << 1;
- mii_mgr_write(31, 0x7830, reg_value);
-
- mii_mgr_read(31, 0x7a40, ®_value);
- reg_value &= ~(1 << 30);
- mii_mgr_write(31, 0x7a40, reg_value);
-
- reg_value = 0x855;
- mii_mgr_write(31, 0x7a78, reg_value);
- #endif
-
- mii_mgr_write(31, 0x7b00, 0x104); /* delay setting for 10/1000M */
- mii_mgr_write(31, 0x7b04, 0x10); /* delay setting for 10/1000M */
-
- /*Tx Driving */
- mii_mgr_write(31, 0x7a54, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7a5c, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7a64, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7a6c, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7a74, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7a7c, 0x88); /* lower GE1 driving */
- mii_mgr_write(31, 0x7810, 0x11); /* lower GE2 driving */
- /*Set MT7623 TX Driving */
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0354, 0x88);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x035c, 0x88);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0364, 0x88);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x036c, 0x88);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0374, 0x88);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x037c, 0x88);
-
- /* Set GE2 driving and slew rate */
- if (ei_local->architecture & GE2_RGMII_AN)
- sys_reg_write((void __iomem *)gpio_base_virt + 0xf00, 0xe00);
- else
- sys_reg_write((void __iomem *)gpio_base_virt + 0xf00, 0xa00);
- /* set GE2 TDSEL */
- sys_reg_write((void __iomem *)gpio_base_virt + 0x4c0, 0x5);
- /* set GE2 TUNE */
- sys_reg_write((void __iomem *)gpio_base_virt + 0xed0, 0);
-
- if (ei_local->chip_name == MT7623_FE)
- mt7530_trgmii_clock_setting(xtal_mode);
- if (ei_local->architecture & GE1_RGMII_FORCE_1000) {
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0350, 0x55);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0358, 0x55);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0360, 0x55);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0368, 0x55);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0370, 0x55);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x0378, 0x855);
- }
-
- lan_wan_partition();
- mt7530_phy_setting();
- for (i = 0; i <= 4; i++) {
- /*turn on PHY */
- mii_mgr_read(i, 0x0, ®_value);
- reg_value &= ~(0x1 << 11);
- mii_mgr_write(i, 0x0, reg_value);
- }
-
- mii_mgr_read(31, 0x7808, ®_value);
- reg_value |= (3 << 16); /* Enable INTR */
- mii_mgr_write(31, 0x7808, reg_value);
-
- iounmap(gpio_base_virt);
-}
-
-void setup_external_gsw(void)
-{
- /* reduce RGMII2 PAD driving strength */
- reg_bit_zero(PAD_RGMII2_MDIO_CFG, 4, 2);
- /*enable MDIO */
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x60, 12, 2);
-
- /*RGMII1=Normal mode */
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x60, 14, 1);
- /*GMAC1= RGMII mode */
- reg_bit_zero(SYSCFG1, 12, 2);
-
- /* (GE1, Link down) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x100, 0x00008000);
-
- /*RGMII2=Normal mode */
- reg_bit_zero(RALINK_SYSCTL_BASE + 0x60, 15, 1);
- /*GMAC2= RGMII mode */
- reg_bit_zero(SYSCFG1, 14, 2);
-
- /* (GE2, Force 1000M/FD, FC ON) */
- sys_reg_write(RALINK_ETH_SW_BASE + 0x200, 0x2105e33b);
-
-} int is_marvell_gigaphy(int ge)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u32 phy_id0 = 0, phy_id1 = 0, phy_address;
-
- if (ei_local->architecture & GE1_RGMII_AN)
- phy_address = mac_to_gigaphy_mode_addr;
- else
- phy_address = mac_to_gigaphy_mode_addr2;
-
- if (!mii_mgr_read(phy_address, 2, &phy_id0)) {
- pr_info("\n Read PhyID 1 is Fail!!\n");
- phy_id0 = 0;
- }
- if (!mii_mgr_read(phy_address, 3, &phy_id1)) {
- pr_info("\n Read PhyID 1 is Fail!!\n");
- phy_id1 = 0;
- }
-
- if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1))
- return 1;
- return 0;
-}
-
-int is_vtss_gigaphy(int ge)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- u32 phy_id0 = 0, phy_id1 = 0, phy_address;
-
- if (ei_local->architecture & GE1_RGMII_AN)
- phy_address = mac_to_gigaphy_mode_addr;
- else
- phy_address = mac_to_gigaphy_mode_addr2;
-
- if (!mii_mgr_read(phy_address, 2, &phy_id0)) {
- pr_info("\n Read PhyID 1 is Fail!!\n");
- phy_id0 = 0;
- }
- if (!mii_mgr_read(phy_address, 3, &phy_id1)) {
- pr_info("\n Read PhyID 1 is Fail!!\n");
- phy_id1 = 0;
- }
-
- if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1))
- return 1;
- return 0;
-}
-
-void fe_sw_preinit(struct END_DEVICE *ei_local)
-{
- struct device_node *np = ei_local->switch_np;
- struct platform_device *pdev = of_find_device_by_node(np);
- struct mtk_gsw *gsw;
- int ret;
-
- gsw = platform_get_drvdata(pdev);
- if (!gsw) {
- pr_info("Failed to get gsw\n");
- return;
- }
-
- regulator_set_voltage(gsw->supply, 1000000, 1000000);
- ret = regulator_enable(gsw->supply);
- if (ret)
- pr_info("Failed to enable mt7530 power: %d\n", ret);
-
- if (gsw->mcm) {
- regulator_set_voltage(gsw->b3v, 3300000, 3300000);
- ret = regulator_enable(gsw->b3v);
- if (ret)
- dev_err(&pdev->dev, "Failed to enable b3v: %d\n", ret);
- } else {
- ret = devm_gpio_request(&pdev->dev, gsw->reset_pin,
- "mediatek,reset-pin");
- if (ret)
- pr_info("fail to devm_gpio_request\n");
-
- gpio_direction_output(gsw->reset_pin, 0);
- usleep_range(1000, 1100);
- gpio_set_value(gsw->reset_pin, 1);
- mdelay(100);
- devm_gpio_free(&pdev->dev, gsw->reset_pin);
- }
-}
-
-void set_sgmii_force_link(int port_num, int speed)
-{
- void __iomem *virt_addr;
- unsigned int reg_value;
- unsigned int sgmii_reg_phya, sgmii_reg;
-
- virt_addr = ioremap(ETHSYS_BASE, 0x20);
- reg_value = sys_reg_read(virt_addr + 0x14);
-
- if (port_num == 1) {
- reg_value |= SGMII_CONFIG_0;
- sgmii_reg_phya = SGMII_REG_PHYA_BASE0;
- sgmii_reg = SGMII_REG_BASE0;
- set_ge1_force_1000();
- }
- if (port_num == 2) {
- reg_value |= SGMII_CONFIG_1;
- sgmii_reg_phya = SGMII_REG_PHYA_BASE1;
- sgmii_reg = SGMII_REG_BASE1;
- set_ge2_force_1000();
- }
-
- sys_reg_write(virt_addr + 0x14, reg_value);
- reg_value = sys_reg_read(virt_addr + 0x14);
- iounmap(virt_addr);
-
- /* Set SGMII GEN2 speed(2.5G) */
- virt_addr = ioremap(sgmii_reg_phya, 0x100);
- reg_value = sys_reg_read(virt_addr + 0x28);
- reg_value |= speed << 2;
- sys_reg_write(virt_addr + 0x28, reg_value);
- iounmap(virt_addr);
-
- virt_addr = ioremap(sgmii_reg, 0x100);
- /* disable SGMII AN */
- reg_value = sys_reg_read(virt_addr);
- reg_value &= ~(1 << 12);
- sys_reg_write(virt_addr, reg_value);
- /* SGMII force mode setting */
- reg_value = sys_reg_read(virt_addr + 0x20);
- sys_reg_write(virt_addr + 0x20, 0x31120019);
- reg_value = sys_reg_read(virt_addr + 0x20);
- /* Release PHYA power down state */
- reg_value = sys_reg_read(virt_addr + 0xe8);
- reg_value &= ~(1 << 4);
- sys_reg_write(virt_addr + 0xe8, reg_value);
- iounmap(virt_addr);
-}
-
-void set_sgmii_an(int port_num)
-{
- void __iomem *virt_addr;
- unsigned int reg_value;
- unsigned int sgmii_reg, sgmii_reg_phya;
-
- virt_addr = ioremap(ETHSYS_BASE, 0x20);
- reg_value = sys_reg_read(virt_addr + 0x14);
-
- if (port_num == 1) {
- reg_value |= SGMII_CONFIG_0;
- sgmii_reg_phya = SGMII_REG_PHYA_BASE0;
- sgmii_reg = SGMII_REG_BASE0;
- }
- if (port_num == 2) {
- reg_value |= SGMII_CONFIG_1;
- sgmii_reg_phya = SGMII_REG_PHYA_BASE1;
- sgmii_reg = SGMII_REG_BASE1;
- }
-
- sys_reg_write(virt_addr + 0x14, reg_value);
- iounmap(virt_addr);
-
- /* set auto polling */
- virt_addr = ioremap(ETHSYS_MAC_BASE, 0x300);
- sys_reg_write(virt_addr + (0x100 * port_num), 0x21056300);
- iounmap(virt_addr);
-
- virt_addr = ioremap(sgmii_reg, 0x100);
- /* set link timer */
- sys_reg_write(virt_addr + 0x18, 0x186a0);
- /* disable remote fault */
- reg_value = sys_reg_read(virt_addr + 0x20);
- reg_value |= 1 << 8;
- sys_reg_write(virt_addr + 0x20, reg_value);
- /* restart an */
- reg_value = sys_reg_read(virt_addr);
- reg_value |= 1 << 9;
- sys_reg_write(virt_addr, reg_value);
- /* Release PHYA power down state */
- reg_value = sys_reg_read(virt_addr + 0xe8);
- reg_value &= ~(1 << 4);
- sys_reg_write(virt_addr + 0xe8, reg_value);
- iounmap(virt_addr);
-}
-
-static void mt7622_esw_5port_gpio(void)
-{
- u32 ret, value, i;
-
- mii_mgr_write(0, 31, 0x2000); /* change G2 page */
-
- ret = mii_mgr_read(0, 31, &value);
- pr_debug("(%d) R31: %x!\n", ret, value);
-
- mii_mgr_read(0, 25, &value);
- value = 0xf020;
- mii_mgr_write(0, 25, value);
- mii_mgr_read(0, 25, &value);
- pr_debug("G2_R25: %x!\n", value);
-
- mii_mgr_write(0, 31, 0x7000); /* change G7 page */
- mii_mgr_read(0, 22, &value);
-
- if (value & 0x8000) {
- pr_debug("G7_R22[15]: 1\n");
- } else {
- mii_mgr_write(0, 22, (value | (1 << 15)));
- pr_debug("G7_R22[15]: set to 1\n");
- }
-
- mii_mgr_write(0, 31, 0x3000); /* change G3 page */
- mii_mgr_read(0, 16, &value);
- value |= (1 << 3);
- mii_mgr_write(0, 16, value);
-
- mii_mgr_read(0, 16, &value);
- pr_debug("G3_R16: %x!\n", value);
-
- mii_mgr_write(0, 31, 0x7000); /* change G7 page */
- mii_mgr_read(0, 22, &value);
- value |= (1 << 5);
- mii_mgr_write(0, 22, value);
-
- mii_mgr_read(0, 24, &value);
- value &= 0xDFFF;
- mii_mgr_write(0, 24, value);
-
- mii_mgr_read(0, 24, &value);
- value |= (1 << 14);
- mii_mgr_write(0, 24, value);
-
- mii_mgr_read(0, 22, &value);
- pr_debug("G7_R22: %x!\n", value);
-
- mii_mgr_read(0, 24, &value);
- pr_debug("G7_R24: %x!\n", value);
-
- for (i = 0; i <= 4; i++) {
- mii_mgr_write(i, 31, 0x8000); /* change L0 page */
-
- mii_mgr_read(i, 30, &value);
- value |= 0x3FFF;
- mii_mgr_write(i, 30, value);
- mii_mgr_read(i, 30, &value);
- pr_debug("port %d L0_R30: %x!\n", i, value);
-
- mii_mgr_write(i, 31, 0xB000); /* change L3 page */
-
- mii_mgr_read(i, 26, &value);
- value |= (1 << 12);
- mii_mgr_write(i, 26, value);
-
- mii_mgr_read(i, 26, &value);
- pr_debug("port %d L3_R26: %x!\n", i, value);
-
- mii_mgr_read(i, 25, &value);
- value |= (1 << 8);
- value |= (1 << 12);
- mii_mgr_write(i, 25, value);
-
- mii_mgr_read(i, 25, &value);
- pr_debug("port %d L3_R25: %x!\n", i, value);
- }
-
- mii_mgr_write(0, 31, 0x2000); /* change G2 page */
-
- mii_mgr_read(0, 25, &value);
-
- pr_debug("G2_R25 before: %x!\n", value);
- /* value &= 0xFFFF3FFF; */
- /* G2_R25: 1020!-->0020 */
- /* value &= 0xFFFF2FFF; */
- value = 0x20;
- mii_mgr_write(0, 25, value);
-
- mii_mgr_read(0, 25, &value);
- pr_debug("G2_R25: %x!\n", value);
-
- /* LDO */
- mii_mgr_write(0, 31, 0x7000); /* change G7 page */
-
- mii_mgr_read(0, 16, &value);
- value |= (1 << 2);
- mii_mgr_write(0, 16, value);
-
- mii_mgr_read(0, 16, &value);
- pr_debug("G7_R16: %x!\n", value);
-
- /* BG */
- mii_mgr_write(0, 31, 0x2000); /* change G2 page */
-
- mii_mgr_read(0, 22, &value);
- value |= (1 << 12);
- value |= (1 << 13);
- value |= (1 << 14);
- mii_mgr_write(0, 22, value);
-
- mii_mgr_read(0, 22, &value);
- pr_debug("G2_R22: %x!\n", value);
-
- mii_mgr_read(0, 22, &value);
- value &= 0x7FFF;
- mii_mgr_write(0, 22, value);
-
- mii_mgr_read(0, 22, &value);
- pr_debug("G2_R22: %x!\n", value);
-}
-
-void leopard_gmii_config(u8 enable)
-{
- unsigned int reg_value = 0;
- void __iomem *gpio_base_virt, *infra_base_virt;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- /*bit[1]: gphy connect GMAC0 or GMAC2 1:GMAC0. 0:GMAC2*/
- /*bit[0]: Co-QPHY path selection 0:U3path, 1:SGMII*/
- infra_base_virt = ioremap(INFRA_BASE, 0x10);
- reg_value = sys_reg_read(infra_base_virt);
- if (enable) {
- reg_value = reg_value | 0x02;
- sys_reg_write(infra_base_virt, reg_value);
-
- mac_to_gigaphy_mode_addr = 0;
- enable_auto_negotiate(ei_local);
-
- /*port5 enable*/
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x90, 0x00007f7f);
- /*port5 an mode, port6 fix*/
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0xc8, 0x20503bfa);
- } else {
- reg_value = reg_value & (~0x2);
- sys_reg_write(infra_base_virt, reg_value);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x84, 0);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x90, 0x10007f7f);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0xc8, 0x05503f38);
- }
- /*10000710 GEPHY_CTRL0[9:6] = 0 */
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x10);
- reg_value = sys_reg_read(gpio_base_virt);
- /*reg_value = reg_value & ~(0xfffff3cf);*/
- reg_value = 0x10000820;
- sys_reg_write(gpio_base_virt, reg_value);
- iounmap(gpio_base_virt);
- iounmap(infra_base_virt);
-}
-
-void fe_sw_init(void)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned int reg_value = 0;
- void __iomem *gpio_base_virt, *infra_base_virt, *ethsys_base_virt;
- //int i;
- //u16 r0_tmp;
-
- /* Case1: MT7623/MT7622 GE1 + GigaPhy */
- if (ei_local->architecture & GE1_RGMII_AN) {
- //enable_auto_negotiate(ei_local);
- if (is_marvell_gigaphy(1)) {
- if (ei_local->features & FE_FPGA_MODE) {
- mii_mgr_read(mac_to_gigaphy_mode_addr, 9,
- ®_value);
- /* turn off 1000Base-T Advertisement
- * (9.9=1000Full, 9.8=1000Half)
- */
- reg_value &= ~(3 << 8);
- mii_mgr_write(mac_to_gigaphy_mode_addr,
- 9, reg_value);
-
- /*10Mbps, debug */
- mii_mgr_write(mac_to_gigaphy_mode_addr,
- 4, 0x461);
-
- mii_mgr_read(mac_to_gigaphy_mode_addr, 0,
- ®_value);
- reg_value |= 1 << 9; /* restart AN */
- mii_mgr_write(mac_to_gigaphy_mode_addr,
- 0, reg_value);
- }
- }
- if (is_vtss_gigaphy(1)) {
- mii_mgr_write(mac_to_gigaphy_mode_addr, 31, 1);
- mii_mgr_read(mac_to_gigaphy_mode_addr, 28,
- ®_value);
- pr_info("Vitesse phy skew: %x --> ", reg_value);
- reg_value |= (0x3 << 12);
- reg_value &= ~(0x3 << 14);
- pr_info("%x\n", reg_value);
- mii_mgr_write(mac_to_gigaphy_mode_addr, 28,
- reg_value);
- mii_mgr_write(mac_to_gigaphy_mode_addr, 31, 0);
- }
- }
-
- /* Case2: RT3883/MT7621 GE2 + GigaPhy */
- if (ei_local->architecture & GE2_RGMII_AN) {
-#if(0)
- leopard_gmii_config(0);
- enable_auto_negotiate(ei_local);
- set_ge2_an();
- set_ge2_gmii();
- if (ei_local->chip_name == LEOPARD_FE) {
- for (i = 1; i < 5; i++)
- do_fe_phy_all_analog_cal(i);
-
- do_ge_phy_all_analog_cal(0);
- }
-#endif
- if (is_marvell_gigaphy(2)) {
- mii_mgr_read(mac_to_gigaphy_mode_addr2, 9,
- ®_value);
- /* turn off 1000Base-T Advertisement
- * (9.9=1000Full, 9.8=1000Half)
- */
- reg_value &= ~(3 << 8);
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 9,
- reg_value);
-
- mii_mgr_read(mac_to_gigaphy_mode_addr2, 20,
- ®_value);
- /* Add delay to RX_CLK for RXD Outputs */
- reg_value |= 1 << 7;
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 20,
- reg_value);
-
- mii_mgr_read(mac_to_gigaphy_mode_addr2, 0,
- ®_value);
- reg_value |= 1 << 15; /* PHY Software Reset */
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 0,
- reg_value);
- if (ei_local->features & FE_FPGA_MODE) {
- mii_mgr_read(mac_to_gigaphy_mode_addr2,
- 9, ®_value);
- /* turn off 1000Base-T Advertisement
- * (9.9=1000Full, 9.8=1000Half)
- */
- reg_value &= ~(3 << 8);
- mii_mgr_write(mac_to_gigaphy_mode_addr2,
- 9, reg_value);
-
- /*10Mbps, debug */
- mii_mgr_write(mac_to_gigaphy_mode_addr2,
- 4, 0x461);
-
- mii_mgr_read(mac_to_gigaphy_mode_addr2,
- 0, ®_value);
- reg_value |= 1 << 9; /* restart AN */
- mii_mgr_write(mac_to_gigaphy_mode_addr2,
- 0, reg_value);
- }
- }
- if (is_vtss_gigaphy(2)) {
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 31, 1);
- mii_mgr_read(mac_to_gigaphy_mode_addr2, 28,
- ®_value);
- pr_info("Vitesse phy skew: %x --> ", reg_value);
- reg_value |= (0x3 << 12);
- reg_value &= ~(0x3 << 14);
- pr_info("%x\n", reg_value);
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 28,
- reg_value);
- mii_mgr_write(mac_to_gigaphy_mode_addr2, 31, 0);
- }
- }
-
- /* Case3: MT7623 GE1 + Internal GigaSW */
- if (ei_local->architecture &
- (GE1_RGMII_FORCE_1000 | GE1_TRGMII_FORCE_2000 |
- GE1_TRGMII_FORCE_2600)) {
- if ((ei_local->chip_name == MT7623_FE) ||
- (ei_local->chip_name == MT7621_FE))
- setup_internal_gsw();
- /* TODO
- * else if (ei_local->features & FE_FPGA_MODE)
- * setup_fpga_gsw();
- * else
- * sys_reg_write(MDIO_CFG, INIT_VALUE_OF_FORCE_1000_FD);
- */
- }
-
- /* Case4: MT7623 GE2 + GigaSW */
- if (ei_local->architecture & GE2_RGMII_FORCE_1000) {
- set_ge2_force_1000();
- if (ei_local->chip_name == MT7623_FE)
- setup_external_gsw();
- }
- /*TODO
- * else
- * sys_reg_write(MDIO_CFG2, INIT_VALUE_OF_FORCE_1000_FD);
- */
-
- /* Case5: MT7622 embedded switch */
- if (ei_local->architecture & RAETH_ESW) {
- reg_value = sys_reg_read(ETHDMASYS_ETH_MAC_BASE + 0xC);
- reg_value = reg_value | 0x1;
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0xC, reg_value);
-
- if (ei_local->architecture & MT7622_EPHY) {
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x100);
- sys_reg_write(gpio_base_virt + 0xF0, 0xE0FFFFFF);
- iounmap(gpio_base_virt);
- gpio_base_virt = ioremap(GPIO_MODE_BASE, 0x100);
- reg_value = sys_reg_read(gpio_base_virt + 0x90);
- reg_value &= 0x0000ffff;
- reg_value |= 0x22220000;
- sys_reg_write(gpio_base_virt + 0x90, reg_value);
- iounmap(gpio_base_virt);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x84, 0);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x90, 0x10007f7f);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0xc8, 0x05503f38);
- } else if (ei_local->architecture & LEOPARD_EPHY) {
- set_ge1_an();
- /*port0 force link down*/
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x84, 0x8000000);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x8c, 0x02404040);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x98, 0x00007f7f);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x04, 0xfbffffff);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x9c, 0x0008a041);
-#if(0)
- if (ei_local->architecture & LEOPARD_EPHY_GMII) {
- leopard_gmii_config(1);
- set_ge0_gmii();
- } else {
- leopard_gmii_config(0);
- }
-#endif
- }
- }
-
- /* clear SGMII setting */
- if ((ei_local->chip_name == LEOPARD_FE) || (ei_local->chip_name == MT7622_FE)) {
- ethsys_base_virt = ioremap(ETHSYS_BASE, 0x20);
- reg_value = sys_reg_read(ethsys_base_virt + 0x14);
- reg_value &= ~(3 << 8);
- sys_reg_write(ethsys_base_virt + 0x14, reg_value);
- }
-
- if (ei_local->architecture & GE1_SGMII_FORCE_2500)
- set_sgmii_force_link(1, 1);
- else if (ei_local->architecture & GE1_SGMII_AN) {
- enable_auto_negotiate(ei_local);
- set_sgmii_an(1);
- }
- if (ei_local->chip_name == LEOPARD_FE) {
- if (ei_local->architecture & GE2_RAETH_SGMII) {
- /*bit[1]: gphy connect GMAC0 or GMAC2 1:GMAC0. 0:GMAC2*/
- /*bit[0]: Co-QPHY path selection 0:U3path, 1:SGMII*/
- infra_base_virt = ioremap(INFRA_BASE, 0x10);
- reg_value = sys_reg_read(infra_base_virt);
- reg_value = reg_value | 0x01;
- sys_reg_write(infra_base_virt, reg_value);
- iounmap(infra_base_virt);
- }
- }
-
- if (ei_local->architecture & GE2_SGMII_FORCE_2500)
- set_sgmii_force_link(2, 1);
- else if (ei_local->architecture & GE2_SGMII_AN) {
- enable_auto_negotiate(ei_local);
- set_sgmii_an(2);
- }
-
- if (ei_local->architecture & MT7622_EPHY) {
- //mt7622_ephy_cal();
- } else if (ei_local->architecture & LEOPARD_EPHY) {
-#if(0)
- leopard_ephy_cal();
- tc_phy_write_l_reg(2, 1, 18, 0x21f);
- tc_phy_write_l_reg(2, 1, 18, 0x22f);
- tc_phy_write_l_reg(2, 1, 18, 0x23f);
- tc_phy_write_l_reg(2, 1, 18, 0x24f);
- tc_phy_write_l_reg(2, 1, 18, 0x4f);
- tc_phy_write_l_reg(4, 1, 18, 0x21f);
- tc_phy_write_l_reg(4, 1, 18, 0x22f);
- tc_phy_write_l_reg(4, 1, 18, 0x2f);
- r0_tmp = tc_phy_read_l_reg(3, 0, 0);
- r0_tmp = r0_tmp | 0x200;
- tc_phy_write_l_reg(3, 0, 0, r0_tmp);
-#endif
- }
-
- if (ei_local->chip_name == MT7621_FE) {
- clk_prepare_enable(ei_local->clks[MTK_CLK_GP0]);
-
- /* switch to esw */
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0xC, 0x1);
-
- /* set agpio to 5-port ephy */
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x100);
- reg_value = sys_reg_read(gpio_base_virt + 0xF0);
- reg_value &= 0xE0FFFFFF;
- sys_reg_write(gpio_base_virt + 0xF0, reg_value);
- iounmap(gpio_base_virt);
-
- /* set ephy to 5-port gpio mode */
- mt7622_esw_5port_gpio();
-
- /* set agpio to 0-port ephy */
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x100);
- reg_value = sys_reg_read(gpio_base_virt + 0xF0);
- reg_value |= BITS(24, 28);
- sys_reg_write(gpio_base_virt + 0xF0, reg_value);
- iounmap(gpio_base_virt);
-
- /* switch back to gmac1 */
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0xC, 0x0);
-
- clk_disable_unprepare(ei_local->clks[MTK_CLK_GP0]);
- }
-
- if (ei_local->chip_name == MT7622_FE) {
- if (ei_local->features & FE_GE2_SUPPORT) {
- gpio_base_virt = ioremap(GPIO_GO_BASE + 0x100, 0x100);
- reg_value = sys_reg_read(gpio_base_virt + 0x70);
- reg_value = reg_value | (1 << 30);
- sys_reg_write(gpio_base_virt + 0x70, reg_value);
- reg_value = sys_reg_read(gpio_base_virt + 0x8c);
- reg_value = reg_value | (1 << 24);
- sys_reg_write(gpio_base_virt + 0x8c, reg_value);
- iounmap(gpio_base_virt);
- }
- }
-}
-
-void fe_sw_deinit(struct END_DEVICE *ei_local)
-{
- struct device_node *np = ei_local->switch_np;
- struct platform_device *pdev = of_find_device_by_node(np);
- void __iomem *gpio_base_virt;
- unsigned int reg_value;
- struct mtk_gsw *gsw;
- int ret;
-
- gsw = platform_get_drvdata(pdev);
- if (!gsw)
- return;
-
- ret = regulator_disable(gsw->supply);
- if (ret)
- dev_err(&pdev->dev, "Failed to disable mt7530 power: %d\n", ret);
-
- if (gsw->mcm) {
- ret = regulator_disable(gsw->b3v);
- if (ret)
- dev_err(&pdev->dev, "Failed to disable b3v: %d\n", ret);
- }
-
- if (ei_local->architecture & MT7622_EPHY) {
- /* set ephy to 5-port gpio mode */
- mt7622_esw_5port_gpio();
-
- /* set agpio to 0-port ephy */
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x100);
- reg_value = sys_reg_read(gpio_base_virt + 0xF0);
- reg_value |= BITS(24, 28);
- sys_reg_write(gpio_base_virt + 0xF0, reg_value);
- iounmap(gpio_base_virt);
- } else if (ei_local->architecture & LEOPARD_EPHY) {
- mt7622_esw_5port_gpio();
- /*10000710 GEPHY_CTRL0[9:6] = 1 */
- gpio_base_virt = ioremap(GPIO_GO_BASE, 0x10);
- reg_value = sys_reg_read(gpio_base_virt);
- reg_value = reg_value | 0x3c0;
- sys_reg_write(gpio_base_virt, reg_value);
- iounmap(gpio_base_virt);
-
- gpio_base_virt = ioremap(GPIO_MODE_BASE, 0x100);
- /*10217310 GPIO_MODE1 [31:16] = 0x0*/
- reg_value = sys_reg_read(gpio_base_virt + 0x10);
- reg_value &= 0x0000ffff;
- reg_value = reg_value & (~0xffff0000);
- sys_reg_write(gpio_base_virt + 0x10, reg_value);
-
- /*10217320 GPIO_MODE2(gpio17/18/21/22/23)*/
- reg_value = sys_reg_read(gpio_base_virt + 0x20);
- reg_value = reg_value & (~0xfff00fff);
- sys_reg_write(gpio_base_virt + 0x20, reg_value);
- iounmap(gpio_base_virt);
- }
-}
-
-static void esw_link_status_changed(int port_no, void *dev_id)
-{
- unsigned int reg_val;
-
- mii_mgr_read(31, (0x3008 + (port_no * 0x100)), ®_val);
- if (reg_val & 0x1)
- pr_info("ESW: Link Status Changed - Port%d Link UP\n", port_no);
- else
- pr_info("ESW: Link Status Changed - Port%d Link Down\n",
- port_no);
-}
-
-irqreturn_t gsw_interrupt(int irq, void *resv)
-{
- unsigned long flags;
- unsigned int reg_int_val;
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- void *dev_id = NULL;
-
- spin_lock_irqsave(&ei_local->page_lock, flags);
- mii_mgr_read(31, 0x700c, ®_int_val);
-
- if (reg_int_val & P4_LINK_CH)
- esw_link_status_changed(4, dev_id);
-
- if (reg_int_val & P3_LINK_CH)
- esw_link_status_changed(3, dev_id);
- if (reg_int_val & P2_LINK_CH)
- esw_link_status_changed(2, dev_id);
- if (reg_int_val & P1_LINK_CH)
- esw_link_status_changed(1, dev_id);
- if (reg_int_val & P0_LINK_CH)
- esw_link_status_changed(0, dev_id);
-
- mii_mgr_write(31, 0x700c, 0x1f); /* ack switch link change */
- spin_unlock_irqrestore(&ei_local->page_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-u32 phy_tr_dbg(u8 phyaddr, char *type, u32 data_addr, u8 ch_num)
-{
- u16 page_reg = 31;
- u32 token_ring_debug_reg = 0x52B5;
- u32 token_ring_control_reg = 0x10;
- u32 token_ring_low_data_reg = 0x11;
- u32 token_ring_high_data_reg = 0x12;
- u16 ch_addr = 0;
- u32 node_addr = 0;
- u32 value = 0;
- u32 value_high = 0;
- u32 value_low = 0;
-
- if (strncmp(type, "DSPF", 4) == 0) {
- /* DSP Filter Debug Node*/
- ch_addr = 0x02;
- node_addr = 0x0D;
- } else if (strncmp(type, "PMA", 3) == 0) {
- /*PMA Debug Node*/
- ch_addr = 0x01;
- node_addr = 0x0F;
- } else if (strncmp(type, "TR", 2) == 0) {
- /* Timing Recovery Debug Node */
- ch_addr = 0x01;
- node_addr = 0x0D;
- } else if (strncmp(type, "PCS", 3) == 0) {
- /* R1000PCS Debug Node */
- ch_addr = 0x02;
- node_addr = 0x0F;
- } else if (strncmp(type, "FFE", 3) == 0) {
- /* FFE Debug Node */
- ch_addr = ch_num;
- node_addr = 0x04;
- } else if (strncmp(type, "EC", 2) == 0) {
- /* ECC Debug Node */
- ch_addr = ch_num;
- node_addr = 0x00;
- } else if (strncmp(type, "ECT", 3) == 0) {
- /* EC/Tail Debug Node */
- ch_addr = ch_num;
- node_addr = 0x01;
- } else if (strncmp(type, "NC", 2) == 0) {
- /* EC/NC Debug Node */
- ch_addr = ch_num;
- node_addr = 0x01;
- } else if (strncmp(type, "DFEDC", 5) == 0) {
- /* DFETail/DC Debug Node */
- ch_addr = ch_num;
- node_addr = 0x05;
- } else if (strncmp(type, "DEC", 3) == 0) {
- /* R1000DEC Debug Node */
- ch_addr = 0x00;
- node_addr = 0x07;
- } else if (strncmp(type, "CRC", 3) == 0) {
- /* R1000CRC Debug Node */
- ch_addr = ch_num;
- node_addr = 0x06;
- } else if (strncmp(type, "AN", 2) == 0) {
- /* Autoneg Debug Node */
- ch_addr = 0x00;
- node_addr = 0x0F;
- } else if (strncmp(type, "CMI", 3) == 0) {
- /* CMI Debug Node */
- ch_addr = 0x03;
- node_addr = 0x0F;
- } else if (strncmp(type, "SUPV", 4) == 0) {
- /* SUPV PHY Debug Node */
- ch_addr = 0x00;
- node_addr = 0x0D;
- } else {
- pr_info("Wrong TR register Type !");
- return 0xFFFF;
- }
- data_addr = data_addr & 0x3F;
-
- tc_mii_write(phyaddr, page_reg, token_ring_debug_reg);
- tc_mii_write(phyaddr, token_ring_control_reg,
- (1 << 15) | (1 << 13) | (ch_addr << 11) | (node_addr << 7) | (data_addr << 1));
-
- value_low = tc_mii_read(phyaddr, token_ring_low_data_reg);
- value_high = tc_mii_read(phyaddr, token_ring_high_data_reg);
- value = value_low + ((value_high & 0x00FF) << 16);
- pr_info("*%s => Phyaddr=%d, ch_addr=%d, node_addr=0x%X, data_addr=0x%X , value=0x%X\r\n",
- type, phyaddr, ch_addr, node_addr, data_addr, value);
- tc_mii_write(phyaddr, page_reg, 0x00);/* V1.11 */
-
- return value;
-}
-
-void esw_show_debug_log(u32 phy_addr)
-{
- u32 val;
-
- val = phy_tr_dbg(phy_addr, "PMA", 0x38, 0);
- pr_info("VgaStateA =0x%x\n", ((val >> 4) & 0x1F));
- pr_info("VgaStateB =0x%x\n", ((val >> 9) & 0x1F));
- pr_info("VgaStateC =0x%x\n", ((val >> 14) & 0x1F));
- pr_info("VgaStateD =0x%x\n", ((val >> 19) & 0x1F));
-
- /* pairA */
- val = tc_phy_read_dev_reg_raeth(phy_addr, 0x1E, 0x9B);
- pr_info("XX0 0x1E,0x9B =0x%x\n", val);
- val = (val >> 8) & 0xFF;
- pr_info("AA0 lch_mse_mdcA =0x%x\r\n", val);
-
- /* Pair B */
- val = tc_phy_read_dev_reg_raeth(phy_addr, 0x1E, 0x9B);
- pr_info("XX1 0x1E,0x9B =0x%x\n", val);
- val = (val) & 0xFF; /* V1.16 */
- pr_info("AA1 lch_mse_mdcB =0x%x\r\n", val);
- /* Pair C */
- val = tc_phy_read_dev_reg_raeth(phy_addr, 0x1E, 0x9C);
- pr_info("XX2 0x1E,0x9C =0x%x\n", val);
- val = (val >> 8) & 0xFF;
- pr_info("AA2 lch_mse_mdcC =0x%x\r\n", val);
-
- /* Pair D */
- val = tc_phy_read_dev_reg_raeth(phy_addr, 0x1E, 0x9C);
- pr_info("XX3 0x1E,0x9C =0x%x\n", val);
- val = (val) & 0xFF; /* V1.16 */
- pr_info("AA3 lch_mse_mdcD =0x%x\r\n", val);
-}
-
-irqreturn_t esw_interrupt(int irq, void *resv)
-{
- unsigned long flags;
- u32 phy_val;
- int i;
- static unsigned int port_status[5] = {0, 0, 0, 0, 0};
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- spin_lock_irqsave(&ei_local->page_lock, flags);
- /* disable irq mask and ack irq status */
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x4, 0xffffffff);
- sys_reg_write(ETHDMASYS_ETH_SW_BASE, 0x04000000);
- spin_unlock_irqrestore(&ei_local->page_lock, flags);
- for (i = 0; i < 5; i++) {
- mii_mgr_read(i, 1, &phy_val);
- if (port_status[i] != ((phy_val & 0x4) >> 2)) {
- if (port_status[i] == 0) {
- port_status[i] = 1;
- pr_info("ESW: Link Status Changed - Port%d Link Up\n", i);
- } else {
- port_status[i] = 0;
- pr_info("ESW: Link Status Changed - Port%d Link Down\n", i);
- }
- if (ei_local->architecture & LEOPARD_EPHY) {
- if (i == 0)
- esw_show_debug_log(i);/*port0 giga port*/
- }
- }
- }
- /* enable irq mask */
- sys_reg_write(ETHDMASYS_ETH_SW_BASE + 0x4, 0xfbffffff);
- return IRQ_HANDLED;
-}
-
-int ephy_ioctl(struct net_device *dev, struct ifreq *ifr,
- struct ephy_ioctl_data *ioctl_data)
-{
- int ret = 0;
- unsigned int cmd;
- u8 cnt = 0;
- u8 port_num = 0;
-
- cmd = ioctl_data->cmd;
- pr_info("%s : cmd =%x\n", __func__, cmd);
- switch (cmd) {
- case RAETH_VBG_IEXT_CALIBRATION:
- cnt = 0;
- fe_cal_vbg_flag = 0; /*restart calibration*/
- for (port_num = 0; port_num < 5; port_num++) {
- while ((fe_cal_vbg_flag == 0) && (cnt < 0x3)) {
- fe_cal_vbg(port_num, 1);
- cnt++;
- if (fe_cal_vbg_flag == 0)
- pr_info(" VBG wait! (%d)\n", cnt);
- }
- }
- break;
-
- case RAETH_TXG_R50_CALIBRATION:
- cnt = 0;
- fe_cal_r50_flag = 0;
- for (port_num = 0; port_num < 5; port_num++) {
- while ((fe_cal_r50_flag == 0) && (cnt < 0x3)) {
- fe_cal_r50(port_num, 1);
- cnt++;
- if (fe_cal_r50_flag == 0)
- pr_info(" FE R50 wait! (%d)\n", cnt);
- }
- }
- break;
-
- case RAETH_TXG_OFFSET_CALIBRATION:
- for (port_num = 0; port_num < 5; port_num++) {
- cnt = 0;
- fe_cal_tx_offset_flag = 0;
- while ((fe_cal_tx_offset_flag == 0) && (cnt < 0x3)) {
- fe_cal_tx_offset(port_num, 100);
- cnt++;
- if (fe_cal_tx_offset_flag == 0)
- pr_info("FeTxOffsetAnaCal wait!(%d)\n",
- cnt);
- }
- cnt = 0;
- fe_cal_tx_offset_flag_mdix = 0;
- while ((fe_cal_tx_offset_flag_mdix == 0) && (cnt < 0x3)) {
- fe_cal_tx_offset_mdix(port_num, 100);
- cnt++;
- if (fe_cal_tx_offset_flag_mdix == 0)
- pr_info
- ("FeTxOffsetAnaCal mdix wait!(%d)\n",
- cnt);
- }
- }
- break;
-
- case RAETH_TXG_AMP_CALIBRATION:
- for (port_num = 0; port_num < 5; port_num++) {
- cnt = 0;
- fe_cal_flag = 0;
- while ((fe_cal_flag == 0) && (cnt < 0x3)) {
- fe_cal_tx_amp(port_num, 300);
- cnt++;
- if (fe_cal_flag == 0)
- pr_info("FETxAmpAnaCal wait!(%d)\n",
- cnt);
- }
- cnt = 0;
- fe_cal_flag_mdix = 0;
- while ((fe_cal_flag_mdix == 0) && (cnt < 0x3)) {
- fe_cal_tx_amp_mdix(port_num, 300);
- cnt++;
- if (fe_cal_flag_mdix == 0)
- pr_info
- ("FETxAmpAnaCal mdix wait!(%d)\n",
- cnt);
- }
- }
- break;
-
- case GE_TXG_R50_CALIBRATION:
- cnt = 0;
- ge_cal_r50_raeth_flag = 0;
- while ((ge_cal_r50_raeth_flag == 0) && (cnt < 0x3)) {
- ge_cal_r50_raeth(0, 20);
- cnt++;
- if (ge_cal_r50_raeth_flag == 0)
- pr_info(" GE R50 wait! (%d)\n", cnt);
- }
- break;
-
- case GE_TXG_OFFSET_CALIBRATION:
- cnt = 0;
- ge_cal_tx_offset_raeth_flag = 0;
- while ((ge_cal_tx_offset_raeth_flag == 0) && (cnt < 0x3)) {
- ge_cal_tx_offset_raeth(port_num, 20);
- cnt++;
- if (ge_cal_tx_offset_raeth_flag == 0)
- pr_info("GeTxOffsetAnaCal wait!(%d)\n",
- cnt);
- }
- break;
-
- case GE_TXG_AMP_CALIBRATION:
- cnt = 0;
- ge_cal_flag_raeth = 0;
- while ((ge_cal_flag_raeth == 0) && (cnt < 0x3)) {
- ge_cal_tx_amp_raeth(port_num, 20);
- cnt++;
- if (ge_cal_flag_raeth == 0)
- pr_info("GETxAmpAnaCal wait!(%d)\n",
- cnt);
- }
- break;
- default:
- ret = 1;
- break;
- }
-
- return ret;
-}
-
-static const struct of_device_id mediatek_gsw_match[] = {
- {.compatible = "mediatek,mt7623-gsw"},
- {.compatible = "mediatek,mt7621-gsw"},
- {},
-};
-
-MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
-
-static int mtk_gsw_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *pctl;
- struct mtk_gsw *gsw;
- int err;
- const char *pm;
-
- gsw = devm_kzalloc(&pdev->dev, sizeof(struct mtk_gsw), GFP_KERNEL);
- if (!gsw)
- return -ENOMEM;
-
- gsw->dev = &pdev->dev;
- gsw->trgmii_force = 2000;
- gsw->irq = irq_of_parse_and_map(np, 0);
- if (gsw->irq < 0)
- return -EINVAL;
-
- err = of_property_read_string(pdev->dev.of_node, "mcm", &pm);
- if (!err && !strcasecmp(pm, "enable")) {
- gsw->mcm = true;
- pr_info("== MT7530 MCM ==\n");
- }
-
- gsw->ethsys = syscon_regmap_lookup_by_phandle(np, "mediatek,ethsys");
- if (IS_ERR(gsw->ethsys)) {
- pr_err("fail at %s %d\n", __func__, __LINE__);
- return PTR_ERR(gsw->ethsys);
- }
-
- if (!gsw->mcm) {
- gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
- if (gsw->reset_pin < 0) {
- pr_err("fail at %s %d\n", __func__, __LINE__);
- return -1;
- }
- pr_debug("reset_pin_port= %d\n", gsw->reset_pin);
-
- pctl = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
- if (IS_ERR(pctl)) {
- pr_err("fail at %s %d\n", __func__, __LINE__);
- return PTR_ERR(pctl);
- }
-
- gsw->pctl = syscon_node_to_regmap(pctl);
- if (IS_ERR(pctl)) {
- pr_err("fail at %s %d\n", __func__, __LINE__);
- return PTR_ERR(pctl);
- }
-
- gsw->pins = pinctrl_get(&pdev->dev);
- if (gsw->pins) {
- gsw->ps_reset =
- pinctrl_lookup_state(gsw->pins, "reset");
-
- if (IS_ERR(gsw->ps_reset)) {
- dev_err(&pdev->dev,
- "failed to lookup the gsw_reset state\n");
- return PTR_ERR(gsw->ps_reset);
- }
- } else {
- dev_err(&pdev->dev, "gsw get pinctrl fail\n");
- return PTR_ERR(gsw->pins);
- }
- }
-
- gsw->supply = devm_regulator_get(&pdev->dev, "mt7530");
- if (IS_ERR(gsw->supply)) {
- pr_info("fail at %s %d\n", __func__, __LINE__);
- return PTR_ERR(gsw->supply);
- }
-
- if (gsw->mcm) {
- gsw->b3v = devm_regulator_get(&pdev->dev, "b3v");
- if (IS_ERR(gsw->b3v))
- return PTR_ERR(gsw->b3v);
- }
-
- gsw->wllll = of_property_read_bool(np, "mediatek,wllll");
-
- platform_set_drvdata(pdev, gsw);
-
- return 0;
-}
-
-static int mtk_gsw_remove(struct platform_device *pdev)
-{
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
-static struct platform_driver gsw_driver = {
- .probe = mtk_gsw_probe,
- .remove = mtk_gsw_remove,
- .driver = {
- .name = "mtk-gsw",
- .owner = THIS_MODULE,
- .of_match_table = mediatek_gsw_match,
- },
-};
-
-module_platform_driver(gsw_driver);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.h
deleted file mode 100644
index 7d3a9ee..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/ra_switch.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_SWITCH_H
-#define RA_SWITCH_H
-
-extern struct net_device *dev_raether;
-#define ANACAL_INIT 0x01
-#define ANACAL_ERROR 0xFD
-#define ANACAL_SATURATION 0xFE
-#define ANACAL_FINISH 0xFF
-#define ANACAL_PAIR_A 0
-#define ANACAL_PAIR_B 1
-#define ANACAL_PAIR_C 2
-#define ANACAL_PAIR_D 3
-#define DAC_IN_0V 0x000
-#define DAC_IN_2V 0x0f0
-#define TX_AMP_OFFSET_0MV 0x20
-#define TX_AMP_OFFSET_VALID_BITS 6
-#define FE_CAL_P0 0
-#define FE_CAL_P1 1
-#if defined(CONFIG_MACH_LEOPARD)
-#define FE_CAL_COMMON 1
-#else
-#define FE_CAL_COMMON 0
-#endif
-
-void fe_sw_init(void);
-void fe_sw_preinit(struct END_DEVICE *ei_local);
-void fe_sw_deinit(struct END_DEVICE *ei_local);
-void sw_ioctl(struct ra_switch_ioctl_data *ioctl_data);
-irqreturn_t esw_interrupt(int irq, void *resv);
-irqreturn_t gsw_interrupt(int irq, void *resv);
-
-/* struct mtk_gsw - the structure that holds the SoC specific data
- * @dev: The Device struct
- * @base: The base address
- * @piac_offset: The PIAC base may change depending on SoC
- * @irq: The IRQ we are using
- * @port4: The port4 mode on MT7620
- * @autopoll: Is MDIO autopolling enabled
- * @ethsys: The ethsys register map
- * @pctl: The pin control register map
- * @clk_trgpll: The trgmii pll clock
- */
-struct mtk_gsw {
- struct mtk_eth *eth;
- struct device *dev;
- void __iomem *base;
- u32 piac_offset;
- int irq;
- int port4;
- unsigned long int autopoll;
-
- struct regmap *ethsys;
- struct regmap *pctl;
-
- int trgmii_force;
- bool wllll;
- bool mcm;
- struct pinctrl *pins;
- struct pinctrl_state *ps_default;
- struct pinctrl_state *ps_reset;
- int reset_pin;
- struct regulator *supply;
- struct regulator *b3v;
-};
-
-extern u8 fe_cal_flag;
-extern u8 fe_cal_flag_mdix;
-extern u8 fe_cal_tx_offset_flag;
-extern u8 fe_cal_tx_offset_flag_mdix;
-extern u8 fe_cal_r50_flag;
-extern u8 fe_cal_vbg_flag;
-void fe_cal_r50(u8 port_num, u32 delay);
-void fe_cal_tx_amp(u8 port_num, u32 delay);
-void fe_cal_tx_amp_mdix(u8 port_num, u32 delay);
-void fe_cal_tx_offset(u8 port_num, u32 delay);
-void fe_cal_tx_offset_mdix(u8 port_num, u32 delay);
-void fe_cal_vbg(u8 port_num, u32 delay);
-/*giga port calibration*/
-void ge_cal_r50(u8 port_num, u32 delay);
-void ge_cal_tx_amp(u8 port_num, u32 delay);
-void ge_cal_tx_offset(u8 port_num, u32 delay);
-void do_ge_phy_all_analog_cal(u8 phyaddr);
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_config.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_config.h
deleted file mode 100644
index 428bbf7..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_config.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RAETH_CONFIG_H
-#define RAETH_CONFIG_H
-
-/* compile flag for features */
-#define DELAY_INT
-
-#define CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
-/*#define CONFIG_QDMA_QOS_WEB*/
-#define CONFIG_QDMA_QOS_MARK
-
-#if !defined(CONFIG_SOC_MT7621)
-#define CONFIG_RAETH_NAPI
-#define CONFIG_RAETH_TX_RX_INT_SEPARATION
-#define CONFIG_RAETH_NAPI_TX_RX
-//#define CONFIG_RAETH_NAPI_RX_ONLY
-#endif
-
-#if defined(CONFIG_SOC_MT7621)
-#define CONFIG_GE1_RGMII_FORCE_1000
-#define CONFIG_GE1_RGMII_FORCE_1200
-#define CONFIG_RA_NETWORK_TASKLET_BH
-#endif
-/*CONFIG_RA_NETWORK_TASKLET_BH*/
-/*CONFIG_RA_NETWORK_WORKQUEUE_BH*/
-/*CONFIG_RAETH_SPECIAL_TAG*/
-#define CONFIG_RAETH_CHECKSUM_OFFLOAD
-#if !defined(CONFIG_SOC_MT7621)
-//#define CONFIG_RAETH_HW_LRO
-#endif
-/* #define CONFIG_RAETH_HW_LRO_FORCE */
-/* #define CONFIG_RAETH_HW_LRO_DVT */
-//#define CONFIG_RAETH_HW_VLAN_TX
-/*CONFIG_RAETH_HW_VLAN_RX*/
-#define CONFIG_RAETH_TSO
-/*#define CONFIG_RAETH_ETHTOOL*/
-#define CONFIG_RAETH_QDMA
-/*CONFIG_RAETH_QDMATX_QDMARX*/
-/*CONFIG_HW_SFQ*/
-//#define CONFIG_RAETH_HW_IOCOHERENT
-#define CONFIG_RAETH_GMAC2
-/*#define CONFIG_RAETH_RSS_4RING*/
-/*#define CONFIG_RAETH_RSS_2RING*/
-/* definitions */
-#ifdef DELAY_INT
-#define FE_DLY_INT BIT(0)
-#else
-#define FE_DLY_INT (0)
-#endif
-#ifdef CONFIG_RAETH_HW_LRO
-#define FE_HW_LRO BIT(1)
-#else
-#define FE_HW_LRO (0)
-#endif
-#ifdef CONFIG_RAETH_HW_LRO_FORCE
-#define FE_HW_LRO_FPORT BIT(2)
-#else
-#define FE_HW_LRO_FPORT (0)
-#endif
-#ifdef CONFIG_RAETH_LRO
-#define FE_SW_LRO BIT(3)
-#else
-#define FE_SW_LRO (0)
-#endif
-#ifdef CONFIG_RAETH_QDMA
-#define FE_QDMA BIT(4)
-#else
-#define FE_QDMA (0)
-#endif
-#ifdef CONFIG_RAETH_NAPI
-#define FE_INT_NAPI BIT(5)
-#else
-#define FE_INT_NAPI (0)
-#endif
-#ifdef CONFIG_RA_NETWORK_WORKQUEUE_BH
-#define FE_INT_WORKQ BIT(6)
-#else
-#define FE_INT_WORKQ (0)
-#endif
-#ifdef CONFIG_RA_NETWORK_TASKLET_BH
-#define FE_INT_TASKLET BIT(7)
-#else
-#define FE_INT_TASKLET (0)
-#endif
-#ifdef CONFIG_RAETH_TX_RX_INT_SEPARATION
-#define FE_IRQ_SEPARATE BIT(8)
-#else
-#define FE_IRQ_SEPARATE (0)
-#endif
-#define FE_GE2_SUPPORT BIT(9)
-#ifdef CONFIG_RAETH_ETHTOOL
-#define FE_ETHTOOL BIT(10)
-#else
-#define FE_ETHTOOL (0)
-#endif
-#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
-#define FE_CSUM_OFFLOAD BIT(11)
-#else
-#define FE_CSUM_OFFLOAD (0)
-#endif
-#ifdef CONFIG_RAETH_TSO
-#define FE_TSO BIT(12)
-#else
-#define FE_TSO (0)
-#endif
-#ifdef CONFIG_RAETH_TSOV6
-#define FE_TSO_V6 BIT(13)
-#else
-#define FE_TSO_V6 (0)
-#endif
-#ifdef CONFIG_RAETH_HW_VLAN_TX
-#define FE_HW_VLAN_TX BIT(14)
-#else
-#define FE_HW_VLAN_TX (0)
-#endif
-#ifdef CONFIG_RAETH_HW_VLAN_RX
-#define FE_HW_VLAN_RX BIT(15)
-#else
-#define FE_HW_VLAN_RX (0)
-#endif
-#ifdef CONFIG_RAETH_QDMA
-#define FE_QDMA_TX BIT(16)
-#else
-#define FE_QDMA_TX (0)
-#endif
-#ifdef CONFIG_RAETH_QDMATX_QDMARX
-#define FE_QDMA_RX BIT(17)
-#else
-#define FE_QDMA_RX (0)
-#endif
-#ifdef CONFIG_HW_SFQ
-#define FE_HW_SFQ BIT(18)
-#else
-#define FE_HW_SFQ (0)
-#endif
-#define FE_HW_IOCOHERENT BIT(19)
-
-#ifdef CONFIG_MTK_FPGA
-#define FE_FPGA_MODE BIT(20)
-#else
-#define FE_FPGA_MODE (0)
-#endif
-
-#ifdef CONFIG_RAETH_RSS_4RING
-#define FE_RSS_4RING BIT(20)
-#else
-#define FE_RSS_4RING (0)
-#endif
-
-#ifdef CONFIG_RAETH_RSS_2RING
-#define FE_RSS_2RING BIT(2)
-#else
-#define FE_RSS_2RING (0)
-#endif
-
-#ifdef CONFIG_RAETH_HW_LRO_REASON_DBG
-#define FE_HW_LRO_DBG BIT(21)
-#else
-#define FE_HW_LRO_DBG (0)
-#endif
-#ifdef CONFIG_RAETH_INT_DBG
-#define FE_RAETH_INT_DBG BIT(22)
-#else
-#define FE_RAETH_INT_DBG (0)
-#endif
-#ifdef CONFIG_USER_SNMPD
-#define USER_SNMPD BIT(23)
-#else
-#define USER_SNMPD (0)
-#endif
-#ifdef CONFIG_TASKLET_WORKQUEUE_SW
-#define TASKLET_WORKQUEUE_SW BIT(24)
-#else
-#define TASKLET_WORKQUEUE_SW (0)
-#endif
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
-#define FE_HW_NAT BIT(25)
-#else
-#define FE_HW_NAT (0)
-#endif
-#ifdef CONFIG_RAETH_NAPI_TX_RX
-#define FE_INT_NAPI_TX_RX BIT(26)
-#else
-#define FE_INT_NAPI_TX_RX (0)
-#endif
-#ifdef CONFIG_QDMA_MQ
-#define QDMA_MQ BIT(27)
-#else
-#define QDMA_MQ (0)
-#endif
-#ifdef CONFIG_RAETH_NAPI_RX_ONLY
-#define FE_INT_NAPI_RX_ONLY BIT(28)
-#else
-#define FE_INT_NAPI_RX_ONLY (0)
-#endif
-#ifdef CONFIG_QDMA_SUPPORT_QOS
-#define FE_QDMA_FQOS BIT(29)
-#else
-#define FE_QDMA_FQOS (0)
-#endif
-
-#ifdef CONFIG_QDMA_QOS_WEB
-#define QDMA_QOS_WEB BIT(30)
-#else
-#define QDMA_QOS_WEB (0)
-#endif
-
-#ifdef CONFIG_QDMA_QOS_MARK
-#define QDMA_QOS_MARK BIT(31)
-#else
-#define QDMA_QOS_MARK (0)
-#endif
-
-#define MT7626_FE (7626)
-#define MT7623_FE (7623)
-#define MT7622_FE (7622)
-#define MT7621_FE (7621)
-#define LEOPARD_FE (1985)
-#define MT7986_FE (1985)
-
-#define GMAC2 BIT(0)
-#define LAN_WAN_SUPPORT BIT(1)
-#define WAN_AT_P0 BIT(2)
-#define WAN_AT_P4 BIT(3)
-#if defined(CONFIG_GE1_RGMII_FORCE_1000)
-#define GE1_RGMII_FORCE_1000 BIT(4)
-#define GE1_TRGMII_FORCE_2000 (0)
-#define GE1_TRGMII_FORCE_2600 (0)
-#define MT7530_TRGMII_PLL_25M (0x0A00)
-#define MT7530_TRGMII_PLL_40M (0x0640)
-#elif defined(CONFIG_GE1_TRGMII_FORCE_2000)
-#define GE1_TRGMII_FORCE_2000 BIT(5)
-#define GE1_RGMII_FORCE_1000 (0)
-#define GE1_TRGMII_FORCE_2600 (0)
-#define MT7530_TRGMII_PLL_25M (0x1400)
-#define MT7530_TRGMII_PLL_40M (0x0C80)
-#elif defined(CONFIG_GE1_TRGMII_FORCE_2600)
-#define GE1_TRGMII_FORCE_2600 BIT(6)
-#define GE1_RGMII_FORCE_1000 (0)
-#define GE1_TRGMII_FORCE_2000 (0)
-#define MT7530_TRGMII_PLL_25M (0x1A00)
-#define MT7530_TRGMII_PLL_40M (0x1040)
-#define TRGMII
-#else
-#define GE1_RGMII_FORCE_1000 (0)
-#define GE1_TRGMII_FORCE_2000 (0)
-#define GE1_TRGMII_FORCE_2600 (0)
-#define MT7530_TRGMII_PLL_25M (0)
-#define MT7530_TRGMII_PLL_40M (0)
-#endif
-
-#define GE1_RGMII_AN BIT(7)
-#define GE1_SGMII_AN BIT(8)
-#define GE1_SGMII_FORCE_2500 BIT(9)
-#define GE1_RGMII_ONE_EPHY BIT(10)
-#define RAETH_ESW BIT(11)
-#define GE1_RGMII_NONE BIT(12)
-#define GE2_RGMII_FORCE_1000 BIT(13)
-#define GE2_RGMII_AN BIT(14)
-#define GE2_INTERNAL_GPHY BIT(15)
-#define GE2_SGMII_AN BIT(16)
-#define GE2_SGMII_FORCE_2500 BIT(17)
-#define MT7622_EPHY BIT(18)
-#define RAETH_SGMII BIT(19)
-#define GE2_RAETH_SGMII BIT(20)
-#define LEOPARD_EPHY BIT(21)
-#define SGMII_SWITCH BIT(22)
-#define LEOPARD_EPHY_GMII BIT(23)
-/* /#ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR */
-/* #define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR (0) */
-/* #endif */
-/* #ifndef CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 */
-/* #define CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 (0) */
-/* #endif */
-
-/* macros */
-#define fe_features_config(end_device) \
-{ \
-end_device->features = 0; \
-end_device->features |= FE_DLY_INT; \
-end_device->features |= FE_HW_LRO; \
-end_device->features |= FE_HW_LRO_FPORT;\
-end_device->features |= FE_HW_LRO_DBG; \
-end_device->features |= FE_SW_LRO; \
-end_device->features |= FE_QDMA; \
-end_device->features |= FE_INT_NAPI; \
-end_device->features |= FE_INT_WORKQ; \
-end_device->features |= FE_INT_TASKLET; \
-end_device->features |= FE_IRQ_SEPARATE;\
-end_device->features |= FE_ETHTOOL; \
-end_device->features |= FE_CSUM_OFFLOAD;\
-end_device->features |= FE_TSO; \
-end_device->features |= FE_TSO_V6; \
-end_device->features |= FE_HW_VLAN_TX; \
-end_device->features |= FE_HW_VLAN_RX; \
-end_device->features |= FE_QDMA_TX; \
-end_device->features |= FE_QDMA_RX; \
-end_device->features |= FE_HW_SFQ; \
-end_device->features |= FE_FPGA_MODE; \
-end_device->features |= FE_HW_NAT; \
-end_device->features |= FE_INT_NAPI_TX_RX; \
-end_device->features |= FE_INT_NAPI_RX_ONLY; \
-end_device->features |= FE_QDMA_FQOS; \
-end_device->features |= QDMA_QOS_WEB; \
-end_device->features |= QDMA_QOS_MARK; \
-end_device->features |= FE_RSS_4RING; \
-end_device->features |= FE_RSS_2RING; \
-}
-
-#define fe_architecture_config(end_device) \
-{ \
-end_device->architecture = 0; \
-end_device->architecture |= GE1_TRGMII_FORCE_2000; \
-end_device->architecture |= GE1_TRGMII_FORCE_2600; \
-}
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_reg.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_reg.h
deleted file mode 100644
index 111d896..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raeth_reg.h
+++ /dev/null
@@ -1,1354 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RAETH_REG_H
-#define RAETH_REG_H
-
-#include <linux/mii.h> /* for struct mii_if_info in ra2882ethreg.h */
-#include <linux/version.h> /* check linux version */
-#include <linux/interrupt.h> /* for "struct tasklet_struct" */
-#include <linux/ip.h>
-#include <linux/ipv6.h>
-#include <linux/workqueue.h>
-#include <linux/netdevice.h>
-#include <linux/if_vlan.h>
-
-#include "raether.h"
-
-#define MAX_PACKET_SIZE 1514
-#define MIN_PACKET_SIZE 60
-#if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621)
-#define MAX_PTXD_LEN 0x3fff /* 16k */
-#define MAX_QTXD_LEN 0x3fff /* 16k */
-#else
-#define MAX_PTXD_LEN 0x3fff /* 16k */
-#define MAX_QTXD_LEN 0xffff
-#endif
-
-#define phys_to_bus(a) (a)
-
-extern void __iomem *ethdma_sysctl_base;
-extern void __iomem *ethdma_frame_engine_base;
-
-/* bits range: for example BITS(16,23) = 0xFF0000
- * ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000
- * ==> (BIT(n+1)-1) = 0x00FFFFFF
- */
-#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
-
-#define ETHER_ADDR_LEN 6
-
-/* Phy Vender ID list */
-
-#define EV_ICPLUS_PHY_ID0 0x0243
-#define EV_ICPLUS_PHY_ID1 0x0D90
-#define EV_MARVELL_PHY_ID0 0x0141
-#define EV_MARVELL_PHY_ID1 0x0CC2
-#define EV_VTSS_PHY_ID0 0x0007
-#define EV_VTSS_PHY_ID1 0x0421
-
-#define ETHSYS_BASE 0x1b000000
-#define SGMII_CONFIG_0 BIT(9) /*SGMII path enable of GMAC1*/
-#define SGMII_CONFIG_1 BIT(8) /*SGMII path enable of GMAC1*/
-
-#define SGMII_REG_BASE0 (0x10060000)
-#define SGMII_REG_PHYA_BASE0 (0x10060100)
-#define SGMII_REG_BASE1 (0x10070000)
-#define SGMII_REG_PHYA_BASE1 (0x10070100)
-#define ETHSYS_MAC_BASE (0x1b110000)
-
-#if defined(CONFIG_MACH_LEOPARD)
-#define FE_RSTCTL 0x1B000034
-#define INFRA_BASE 0x1000070C
-#define GEPHY_CTRL0 0x10000710
-#define GPIO_GO_BASE GEPHY_CTRL0
-#define GPIO_MODE_BASE 0x10217300
-#else
-#define INFRA_BASE 0
-#define FE_RSTCTL 0
-#define GPIO_GO_BASE 0x10211800
-#define GPIO_MODE_BASE 0x10211300
-#endif
-
-/* ETHDMASYS base address
- * for I2S/PCM/GDMA/HSDMA/FE/GMAC
- */
-#define ETHDMASYS_BASE ethdma_sysctl_base
-#define ETHDMASYS_FRAME_ENGINE_BASE ethdma_frame_engine_base
-
-#define ETHDMASYS_SYSCTL_BASE ETHDMASYS_BASE
-#define ETHDMASYS_PPE_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x0C00)
-#define ETHDMASYS_ETH_MAC_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000)
-#if defined(CONFIG_MACH_MT7623) || defined(CONFIG_SOC_MT7621)
-#define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x10000)
-#else
-#define ETHDMASYS_ETH_SW_BASE (ETHDMASYS_FRAME_ENGINE_BASE + 0x18000)
-#endif
-
-#define RALINK_FRAME_ENGINE_BASE ETHDMASYS_FRAME_ENGINE_BASE
-#define RALINK_PPE_BASE ETHDMASYS_PPE_BASE
-#define RALINK_SYSCTL_BASE ETHDMASYS_SYSCTL_BASE
-#define RALINK_ETH_MAC_BASE ETHDMASYS_ETH_MAC_BASE
-#define RALINK_ETH_SW_BASE ETHDMASYS_ETH_SW_BASE
-
-#define RSTCTL_FE_RST BIT(6)
-#define RALINK_FE_RST RSTCTL_FE_RST
-
-#define RSTCTL_ETH_RST BIT(23)
-#define RALINK_ETH_RST RSTCTL_ETH_RST
-
-/* FE_INT_STATUS */
-#define RX_COHERENT BIT(31)
-#define RX_DLY_INT BIT(30)
-#define TX_COHERENT BIT(29)
-#define TX_DLY_INT BIT(28)
-#define RING3_RX_DLY_INT BIT(27)
-#define RING2_RX_DLY_INT BIT(26)
-#define RING1_RX_DLY_INT BIT(25)
-#define RING0_RX_DLY_INT BIT(30)
-
-#define RSS_RX_INT0 (RX_DONE_INT0 | RX_DONE_INT1 | \
- RING0_RX_DLY_INT | RING1_RX_DLY_INT)
-
-#define RSS_RX_RING0 (RX_DONE_INT0 | RING0_RX_DLY_INT)
-#define RSS_RX_RING1 (RX_DONE_INT1 | RING1_RX_DLY_INT)
-#define RSS_RX_RING2 (RX_DONE_INT2 | RING2_RX_DLY_INT)
-#define RSS_RX_RING3 (RX_DONE_INT3 | RING3_RX_DLY_INT)
-
-#define RSS_RX_INT1 (RX_DONE_INT2 | RX_DONE_INT3 | \
- RING2_RX_DLY_INT | RING3_RX_DLY_INT)
-
-#define RSS_RX_DLY_INT0 (RING0_RX_DLY_INT | RING1_RX_DLY_INT)
-#define RSS_RX_DLY_INT1 (RING2_RX_DLY_INT | RING3_RX_DLY_INT)
-
-#define RSS_RX_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
- RING2_RX_DLY_INT | RING3_RX_DLY_INT)
-
-#define RXD_ERROR BIT(24)
-#define ALT_RPLC_INT3 BIT(23)
-#define ALT_RPLC_INT2 BIT(22)
-#define ALT_RPLC_INT1 BIT(21)
-
-#define RX_DONE_INT3 BIT(19)
-#define RX_DONE_INT2 BIT(18)
-#define RX_DONE_INT1 BIT(17)
-#define RX_DONE_INT0 BIT(16)
-
-#define TX_DONE_INT3 BIT(3)
-#define TX_DONE_INT2 BIT(2)
-#define TX_DONE_INT1 BIT(1)
-#define TX_DONE_INT0 BIT(0)
-
-#define RLS_COHERENT BIT(29)
-#define RLS_DLY_INT BIT(28)
-#define RLS_DONE_INT BIT(0)
-
-#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
- TX_DONE_INT1 | TX_DONE_INT0 | \
- RX_DONE_INT0 | RX_DONE_INT1 | \
- RX_DONE_INT2 | RX_DONE_INT3)
-
-#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | \
- RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)
-#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
-#define RX_INT_ALL (RX_DONE_INT0 | RX_DONE_INT1 | \
- RX_DONE_INT2 | RX_DONE_INT3 | \
- RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
- RING2_RX_DLY_INT | RING3_RX_DLY_INT | RX_DLY_INT)
-#define TX_INT_ALL (TX_DONE_INT0 | TX_DLY_INT)
-
-#define NUM_QDMA_PAGE 512
-#define QDMA_PAGE_SIZE 2048
-
-/* SW_INT_STATUS */
-#define ESW_PHY_POLLING (RALINK_ETH_MAC_BASE + 0x0000)
-#define MAC1_WOL (RALINK_ETH_SW_BASE + 0x0110)
-#define WOL_INT_CLR BIT(17)
-#define WOL_INT_EN BIT(1)
-#define WOL_EN BIT(0)
-
-#define P5_LINK_CH BIT(5)
-#define P4_LINK_CH BIT(4)
-#define P3_LINK_CH BIT(3)
-#define P2_LINK_CH BIT(2)
-#define P1_LINK_CH BIT(1)
-#define P0_LINK_CH BIT(0)
-
-#define RX_BUF_ALLOC_SIZE 2000
-#define FASTPATH_HEADROOM 64
-
-#define ETHER_BUFFER_ALIGN 32 /* /// Align on a cache line */
-
-#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
- ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
- ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
-
-struct PSEUDO_ADAPTER {
- struct net_device *raeth_dev;
- struct net_device *pseudo_dev;
- struct net_device_stats stat;
- struct mii_if_info mii_info;
-};
-
-#define MAX_PSEUDO_ENTRY 1
-
-/* Register Categories Definition */
-#if 0
-#define FE_PSE_OFFSET 0x0000
-#define CDMA_OFFSET 0x0400
-#define GDM1_OFFSET 0x0500
-#define ADMA_OFFSET 0x0800
-#define CDMQ_OFFSET 0x1400
-#define GDM2_OFFSET 0x1500
-#define CDM_OFFSET 0x1600
-#define QDMA_OFFSET 0x1800
-#define RSS_OFFSET 0x3000
-#define EDMA0_OFFSET 0x3800
-#define EDMA1_OFFSET 0x3C00
-#else
-#define FE_PSE_OFFSET 0x0000
-#define CDMA_OFFSET 0x0400
-#define GDM1_OFFSET 0x0500
-#define ADMA_OFFSET 0x4000
-#define CDMQ_OFFSET 0x1400
-#define GDM2_OFFSET 0x1500
-#define CDM_OFFSET 0x1600
-#define QDMA_OFFSET 0x4400
-#define RSS_OFFSET 0x2800
-#define EDMA0_OFFSET 0x3800
-#define EDMA1_OFFSET 0x3C00
-#endif
-
-/* Register Map Detail */
-/* FE/PSE */
-#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
-#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
-#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
-#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x00)
-#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x04)
-#define FE_INT_STATUS2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x08)
-#define FOE_TS_T (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x10)
-#define FE_INT_ENABLE2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0c)
-#define FE_INT_GRP (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x20)
-#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x40)
-#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x44)
-#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x48)
-#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x4C)
-#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x50)
-#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x54)
-#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x58)
-#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x5C)
-
-#define MAC1_LINK BIT(24)
-#define MAC2_LINK BIT(25)
-#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x100)
-#define FE_GLO_MISC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x124)
-#define PSE_IQ_REV1 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x140)
-#define PSE_IQ_REV2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x144)
-#define PSE_IQ_REV3 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x148)
-#define PSE_IQ_REV4 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x14C)
-#define PSE_IQ_REV5 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x150)
-#define PSE_IQ_REV6 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x154)
-#define PSE_IQ_REV7 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x158)
-#define PSE_IQ_REV8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x15C)
-#define PSE_OQ_TH1 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x160)
-#define PSE_OQ_TH2 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x164)
-#define PSE_OQ_TH3 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x168)
-#define PSE_OQ_TH4 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x16C)
-#define PSE_OQ_TH5 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x170)
-#define PSE_OQ_TH6 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x174)
-#define PSE_OQ_TH7 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x178)
-#define PSE_OQ_TH8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x17C)
-#define FE_PSE_FREE (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x240)
-#define FE_DROP_FQ (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x244)
-#define FE_DROP_FC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x248)
-#define FE_DROP_PPE (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x24c)
-/* GDM1 */
-#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x00)
-#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x04)
-#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x08)
-#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDM1_OFFSET + 0x0C)
-#define GDMA1_SCH_CFG GDMA1_SHPR_CFG
-/* CDMA */
-#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x000)
-#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x000)
-#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x004)
-#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x300)
-#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x304)
-#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x308)
-#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x30C)
-#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x320)
-#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x324)
-#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x328)
-#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x32C)
-#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x330)
-#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x334)
-#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x338)
-#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE + CDMA_OFFSET + 0x33C)
-/* ADMA */
-#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x000)
-#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x004)
-#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x008)
-#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x00C)
-#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x010)
-#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x014)
-#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x018)
-#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x01C)
-#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x020)
-#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x024)
-#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x028)
-#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x02C)
-#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x030)
-#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x034)
-#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x038)
-#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x03C)
-#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x100)
-#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x104)
-#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x108)
-#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x10C)
-#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x110)
-#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x114)
-#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x118)
-#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x11C)
-#define RX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x120)
-#define RX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x124)
-#define RX_CALC_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x128)
-#define RX_DRX_IDX2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x12C)
-#define RX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x130)
-#define RX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x134)
-#define RX_CALC_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x138)
-#define RX_DRX_IDX3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x13C)
-#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x200)
-#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x204)
-#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x208)
-#define PDMA_RST_CFG (PDMA_RST_IDX)
-#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x20C)
-#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x210)
-#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x220)
-#define FE_INT_STATUS (INT_STATUS)
-#define INT_MASK (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x228)
-#define FE_INT_ENABLE (INT_MASK)
-#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x280)
-#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x284)
-#define PDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x250)
-#define PDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x254)
-#define PDMA_INT_GRP3 (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x22c)
-/* GDM2 */
-#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x00)
-#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x04)
-#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x08)
-#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDM2_OFFSET + 0x0C)
-#define GDMA2_SCH_CFG GDMA2_SHPR_CFG
-/* QDMA */
-#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x000)
-#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x004)
-#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x008)
-#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x00C)
-#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x010)
-#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x014)
-#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x018)
-#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x01C)
-#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x020)
-#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x024)
-#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x028)
-#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C)
-#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x030)
-#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x034)
-#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x038)
-#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x03C)
-#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x040)
-#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x044)
-#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x048)
-#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x04C)
-#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x050)
-#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x054)
-#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x058)
-#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x05C)
-#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x060)
-#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x064)
-#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x068)
-#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x06C)
-#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x070)
-#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x074)
-#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x078)
-#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x07C)
-#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x080)
-#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x084)
-#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x088)
-#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x08C)
-#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x090)
-#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x094)
-#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x098)
-#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x09C)
-#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A0)
-#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A4)
-#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0A8)
-#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0AC)
-#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B0)
-#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B4)
-#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0B8)
-#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0BC)
-#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C0)
-#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C4)
-#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0C8)
-#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0CC)
-#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D0)
-#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D4)
-#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0D8)
-#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0DC)
-#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E0)
-#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E4)
-#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0E8)
-#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0EC)
-#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F0)
-#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F4)
-#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0F8)
-#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0FC)
-#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x100)
-#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x104)
-#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x108)
-#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x10C)
-#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x110)
-#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x114)
-#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x118)
-#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x11C)
-#define VQTX_TB_BASE_0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x180)
-#define VQTX_TB_BASE_1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x184)
-#define VQTX_TB_BASE_2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x188)
-#define VQTX_TB_BASE_3 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x18C)
-#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x200)
-#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x204)
-#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x208)
-#define QDMA_RST_CFG (QDMA_RST_IDX)
-#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x20C)
-#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x210)
-#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x214)
-#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x218)
-#define QFE_INT_STATUS (QDMA_INT_STS)
-#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x21C)
-#define QFE_INT_ENABLE (QDMA_INT_MASK)
-#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x220)
-#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x224)
-#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x228)
-#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x22C)
-#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x230)
-#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x234)
-#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x238)
-#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x240)
-#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x244)
-#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x248)
-#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x24C)
-#define QTX_MIB_IF (RALINK_FRAME_ENGINE_BASE + 0x1abc)
-#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x300)
-#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x304)
-#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x308)
-#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x310)
-#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x314)
-#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x318)
-#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x320)
-#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x324)
-#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x328)
-#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x32C)
-#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x350)
-#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x354)
-#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x358)
-#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x35C)
-#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x360)
-#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x364)
-#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x368)
-#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x36C)
-#define QDMA_INT_GRP1 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x220)
-#define QDMA_INT_GRP2 (RALINK_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x224)
-
-#define DELAY_INT_INIT 0x8f0f8f0f
-#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
-#define RSS_INT_DLY_INT_2RING (RING0_RX_DLY_INT | RING1_RX_DLY_INT)
-#define RSS_INT_DLY_INT (RING0_RX_DLY_INT | RING1_RX_DLY_INT | \
- RING2_RX_DLY_INT | RING3_RX_DLY_INT | TX_DLY_INT)
-
-/* LRO global control */
-/* Bits [15:0]:LRO_ALT_RFSH_TIMER, Bits [20:16]:LRO_ALT_TICK_TIMER */
-#define LRO_ALT_REFRESH_TIMER (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x001C)
-
-/* LRO auto-learn table info */
-#define PDMA_FE_ALT_CF8 (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0300)
-#define PDMA_FE_ALT_SGL_CFC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0304)
-#define PDMA_FE_ALT_SEQ_CFC (RALINK_FRAME_ENGINE_BASE + FE_PSE_OFFSET + 0x0308)
-
-/* LRO controls */
-#define ADMA_LRO_CTRL_OFFSET (ADMA_OFFSET + 0x180)
-/*Bit [0]:LRO_EN, Bit [1]:LRO_IPv6_EN, Bit [2]:MULTIPLE_NON_LRO_RX_RING_EN,
- * Bit [3]:MULTIPLE_RXD_PREFETCH_EN, Bit [4]:RXD_PREFETCH_EN,
- * Bit [5]:LRO_DLY_INT_EN, Bit [6]:LRO_CRSN_BNW, Bit [7]:L3_CKS_UPD_EN,
- * Bit [20]:first_ineligible_pkt_redirect_en, Bit [21]:cr_lro_alt_score_mode,
- * Bit [22]:cr_lro_alt_rplc_mode, Bit [23]:cr_lro_l4_ctrl_psh_en,
- * Bits [28:26]:LRO_RING_RELINGUISH_REQ, Bits [31:29]:LRO_RING_RELINGUISH_DONE
- */
-#define ADMA_LRO_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
- ADMA_LRO_CTRL_OFFSET + 0x00)
-/* Bits [31:0]:LRO_CPU_REASON */
-#define ADMA_LRO_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
- ADMA_LRO_CTRL_OFFSET + 0x04)
-/* Bits [31:0]:AUTO_LEARN_LRO_ELIGIBLE_THRESHOLD */
-#define ADMA_LRO_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
- ADMA_LRO_CTRL_OFFSET + 0x08)
-/*Bits [7:0]:LRO_MAX_AGGREGATED_CNT,
- * Bits [11:8]:LRO_VLAN_EN, Bits [13:12]:LRO_VLAN_VID_CMP_DEPTH,
- * Bit [14]:ADMA_FW_RSTN_REQ, Bit [15]:ADMA_MODE, Bits [31:16]:LRO_MIN_RXD_SDL0
- */
-#define ADMA_LRO_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
- ADMA_LRO_CTRL_OFFSET + 0x0C)
-
-/* LRO RX delay interrupt configurations */
-#define LRO_RX1_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0270)
-#define LRO_RX2_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0274)
-#define LRO_RX3_DLY_INT (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x0278)
-
-/* LRO auto-learn configurations */
-#define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET (ADMA_OFFSET + 0x190)
-#define PDMA_LRO_ATL_OVERFLOW_ADJ (RALINK_FRAME_ENGINE_BASE + \
- PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET)
-#define LRO_ALT_SCORE_DELTA (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x024c)
-
-/* LRO agg timer configurations */
-#define LRO_MAX_AGG_TIME (RALINK_FRAME_ENGINE_BASE + ADMA_OFFSET + 0x025c)
-
-/* LRO configurations of RX ring #0 */
-#define LRO_RXRING0_OFFSET (ADMA_OFFSET + 0x300)
-#define LRO_RX_RING0_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x04)
-#define LRO_RX_RING0_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x08)
-#define LRO_RX_RING0_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x0C)
-#define LRO_RX_RING0_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x10)
-#define LRO_RX_RING0_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x28)
-/* Bit [8]:RING0_VLD, Bit [9]:RING0_MYIP_VLD */
-#define LRO_RX_RING0_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x2C)
-#define LRO_RX_RING0_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING0_OFFSET + 0x30)
-/* LRO configurations of RX ring #1 */
-#define LRO_RXRING1_OFFSET (ADMA_OFFSET + 0x340)
-#define LRO_RX_RING1_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x00)
-#define LRO_RX_RING1_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x04)
-#define LRO_RX_RING1_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x08)
-#define LRO_RX_RING1_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x0C)
-#define LRO_RX_RING1_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x10)
-#define LRO_RX_RING1_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x14)
-#define LRO_RX_RING1_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x18)
-#define LRO_RX_RING1_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x1C)
-#define LRO_RX_RING1_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x20)
-#define LRO_RX_RING1_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x24)
-#define LRO_RX_RING1_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x28)
-#define LRO_RX_RING1_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x2C)
-#define LRO_RX_RING1_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING1_OFFSET + 0x30)
-#define LRO_RXRING2_OFFSET (ADMA_OFFSET + 0x380)
-#define LRO_RX_RING2_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x00)
-#define LRO_RX_RING2_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x04)
-#define LRO_RX_RING2_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x08)
-#define LRO_RX_RING2_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x0C)
-#define LRO_RX_RING2_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x10)
-#define LRO_RX_RING2_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x14)
-#define LRO_RX_RING2_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x18)
-#define LRO_RX_RING2_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x1C)
-#define LRO_RX_RING2_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x20)
-#define LRO_RX_RING2_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x24)
-#define LRO_RX_RING2_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x28)
-#define LRO_RX_RING2_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x2C)
-#define LRO_RX_RING2_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING2_OFFSET + 0x30)
-#define LRO_RXRING3_OFFSET (ADMA_OFFSET + 0x3C0)
-#define LRO_RX_RING3_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x00)
-#define LRO_RX_RING3_DIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x04)
-#define LRO_RX_RING3_DIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x08)
-#define LRO_RX_RING3_DIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x0C)
-#define LRO_RX_RING3_DIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x10)
-#define LRO_RX_RING3_SIP_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x14)
-#define LRO_RX_RING3_SIP_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x18)
-#define LRO_RX_RING3_SIP_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x1C)
-#define LRO_RX_RING3_SIP_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x20)
-#define LRO_RX_RING3_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x24)
-#define LRO_RX_RING3_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x28)
-#define LRO_RX_RING3_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x2C)
-#define LRO_RX_RING3_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE + \
- LRO_RXRING3_OFFSET + 0x30)
-
-#define ADMA_DBG_OFFSET (ADMA_OFFSET + 0x230)
-#define ADMA_TX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x00)
-#define ADMA_TX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x04)
-#define ADMA_RX_DBG0 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x08)
-#define ADMA_RX_DBG1 (RALINK_FRAME_ENGINE_BASE + ADMA_DBG_OFFSET + 0x0C)
-
-/********RSS CR ************/
-#define ADMA_RSS_GLO_CFG (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x00)
-#define ADMA_RSS_INDR_TABLE_DW0 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x50)
-#define ADMA_RSS_INDR_TABLE_DW1 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x54)
-#define ADMA_RSS_INDR_TABLE_DW2 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x58)
-#define ADMA_RSS_INDR_TABLE_DW3 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x5C)
-#define ADMA_RSS_INDR_TABLE_DW4 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x60)
-#define ADMA_RSS_INDR_TABLE_DW5 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x64)
-#define ADMA_RSS_INDR_TABLE_DW6 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x68)
-#define ADMA_RSS_INDR_TABLE_DW7 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x6C)
-
-#define ADMA_RSS_HASH_KEY_DW0 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x20)
-#define ADMA_RSS_HASH_KEY_DW1 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x24)
-#define ADMA_RSS_HASH_KEY_DW2 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x28)
-#define ADMA_RSS_HASH_KEY_DW3 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x2C)
-#define ADMA_RSS_HASH_KEY_DW4 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x30)
-#define ADMA_RSS_HASH_KEY_DW5 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x34)
-#define ADMA_RSS_HASH_KEY_DW6 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x38)
-#define ADMA_RSS_HASH_KEY_DW7 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x3C)
-#define ADMA_RSS_HASH_KEY_DW8 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x40)
-#define ADMA_RSS_HASH_KEY_DW9 (RALINK_FRAME_ENGINE_BASE + RSS_OFFSET + 0x44)
-/* LRO RX ring mode */
-#define PDMA_RX_NORMAL_MODE (0x0)
-#define PDMA_RX_PSE_MODE (0x1)
-#define PDMA_RX_FORCE_PORT (0x2)
-#define PDMA_RX_AUTO_LEARN (0x3)
-
-#define ADMA_RX_RING0 (0)
-#define ADMA_RX_RING1 (1)
-#define ADMA_RX_RING2 (2)
-#define ADMA_RX_RING3 (3)
-
-#define ADMA_RX_LEN0_MASK (0x3fff)
-#define ADMA_RX_LEN1_MASK (0x3)
-
-#define SET_ADMA_RX_LEN0(x) ((x) & ADMA_RX_LEN0_MASK)
-#define SET_ADMA_RX_LEN1(x) ((x) & ADMA_RX_LEN1_MASK)
-
-#define QDMA_PAGE (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x1F0)
-
-/*SFQ use*/
-#define VQTX_TB_BASE0 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0180)
-#define VQTX_TB_BASE1 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0184)
-#define VQTX_TB_BASE2 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0188)
-#define VQTX_TB_BASE3 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x018C)
-#define VQTX_GLO (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0280)
-#define VQTX_INVLD_PTR (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x028C)
-#define VQTX_NUM (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0290)
-#define VQTX_SCH (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0298)
-#define VQTX_HASH_CFG (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02A0)
-#define VQTX_HASH_SD (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02A4)
-#define VQTX_VLD_CFG (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02B0)
-#define VQTX_MIB_IF (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02BC)
-#define VQTX_MIB_PCNT (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C0)
-#define VQTX_MIB_BCNT0 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C4)
-#define VQTX_MIB_BCNT1 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x02C8)
-#define VQTX_0_BIND_QID (PQ0 << 0)
-#define VQTX_1_BIND_QID (PQ1 << 8)
-#define VQTX_2_BIND_QID (PQ2 << 16)
-#define VQTX_3_BIND_QID (PQ3 << 24)
-#define VQTX_4_BIND_QID (PQ4 << 0)
-#define VQTX_5_BIND_QID (PQ5 << 8)
-#define VQTX_6_BIND_QID (PQ6 << 16)
-#define VQTX_7_BIND_QID (PQ7 << 24)
-#define VQTX_TB_BASE4 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0190)
-#define VQTX_TB_BASE5 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0194)
-#define VQTX_TB_BASE6 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x0198)
-#define VQTX_TB_BASE7 (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0x019C)
-#define VQTX_0_3_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0xBC0)
-#define VQTX_4_7_BIND_QID (ETHDMASYS_FRAME_ENGINE_BASE + QDMA_OFFSET + 0xBC4)
-#define PQ0 0
-#define PQ1 1
-#define PQ2 15
-#define PQ3 16
-#define PQ4 30
-#define PQ5 31
-#define PQ6 43
-#define PQ7 63
-
-#if defined(CONFIG_MACH_MT7623)
-#define VQ_NUM0 256
-#define VQ_NUM1 256
-#define VQ_NUM2 256
-#define VQ_NUM3 256
-#define VQ_NUM4 0
-#define VQ_NUM5 0
-#define VQ_NUM6 0
-#define VQ_NUM7 0
-#define VQTX_NUM_0 (4 << 0)
-#define VQTX_NUM_1 (4 << 4)
-#define VQTX_NUM_2 (4 << 8)
-#define VQTX_NUM_3 (4 << 12)
-#define VQTX_NUM_4 0
-#define VQTX_NUM_5 0
-#define VQTX_NUM_6 0
-#define VQTX_NUM_7 0
-#else
-#define VQ_NUM0 128
-#define VQ_NUM1 128
-#define VQ_NUM2 128
-#define VQ_NUM3 128
-#define VQ_NUM4 128
-#define VQ_NUM5 128
-#define VQ_NUM6 128
-#define VQ_NUM7 128
-#define VQTX_NUM_0 (3 << 0)
-#define VQTX_NUM_1 (3 << 4)
-#define VQTX_NUM_2 (3 << 8)
-#define VQTX_NUM_3 (3 << 12)
-#define VQTX_NUM_4 (3 << 16)
-#define VQTX_NUM_5 (3 << 20)
-#define VQTX_NUM_6 (3 << 24)
-#define VQTX_NUM_7 (3 << 28)
-#endif
-
-#define VQTX_MIB_EN BIT(17)
-
-/*HW IO-COHERNET BASE address*/
-#if defined(CONFIG_MACH_LEOPARD)
-#define HW_IOC_BASE 0x1B000080
-#define IOC_OFFSET 4
-#else
-#define HW_IOC_BASE 0x1B000400
-#define IOC_OFFSET 8
-#endif
-
-/*=========================================
- * SFQ Table Format define
- *=========================================
- */
-struct SFQ_INFO1_T {
- unsigned int VQHPTR;
-};
-
-struct SFQ_INFO2_T {
- unsigned int VQTPTR;
-};
-
-struct SFQ_INFO3_T {
- unsigned int QUE_DEPTH:16;
- unsigned int DEFICIT_CNT:16;
-};
-
-struct SFQ_INFO4_T {
- unsigned int RESV;
-};
-
-struct SFQ_INFO5_T {
- unsigned int PKT_CNT;
-};
-
-struct SFQ_INFO6_T {
- unsigned int BYTE_CNT;
-};
-
-struct SFQ_INFO7_T {
- unsigned int BYTE_CNT;
-};
-
-struct SFQ_INFO8_T {
- unsigned int RESV;
-};
-
-struct SFQ_table {
- struct SFQ_INFO1_T sfq_info1;
- struct SFQ_INFO2_T sfq_info2;
- struct SFQ_INFO3_T sfq_info3;
- struct SFQ_INFO4_T sfq_info4;
- struct SFQ_INFO5_T sfq_info5;
- struct SFQ_INFO6_T sfq_info6;
- struct SFQ_INFO7_T sfq_info7;
- struct SFQ_INFO8_T sfq_info8;
-};
-
-#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
-#define FE_GDM_RXID1_OFFSET (0x0130)
-#define FE_GDM_RXID1 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID1_OFFSET)
-#define GDM_VLAN_PRI7_RXID_SEL BITS(30, 31)
-#define GDM_VLAN_PRI6_RXID_SEL BITS(28, 29)
-#define GDM_VLAN_PRI5_RXID_SEL BITS(26, 27)
-#define GDM_VLAN_PRI4_RXID_SEL BITS(24, 25)
-#define GDM_VLAN_PRI3_RXID_SEL BITS(22, 23)
-#define GDM_VLAN_PRI2_RXID_SEL BITS(20, 21)
-#define GDM_VLAN_PRI1_RXID_SEL BITS(18, 19)
-#define GDM_VLAN_PRI0_RXID_SEL BITS(16, 17)
-#define GDM_TCP_ACK_RXID_SEL BITS(4, 5)
-#define GDM_TCP_ACK_WZPC BIT(3)
-#define GDM_RXID_PRI_SEL BITS(0, 2)
-
-#define FE_GDM_RXID2_OFFSET (0x0134)
-#define FE_GDM_RXID2 (RALINK_FRAME_ENGINE_BASE + FE_GDM_RXID2_OFFSET)
-#define GDM_STAG7_RXID_SEL BITS(30, 31)
-#define GDM_STAG6_RXID_SEL BITS(28, 29)
-#define GDM_STAG5_RXID_SEL BITS(26, 27)
-#define GDM_STAG4_RXID_SEL BITS(24, 25)
-#define GDM_STAG3_RXID_SEL BITS(22, 23)
-#define GDM_STAG2_RXID_SEL BITS(20, 21)
-#define GDM_STAG1_RXID_SEL BITS(18, 19)
-#define GDM_STAG0_RXID_SEL BITS(16, 17)
-#define GDM_PID2_RXID_SEL BITS(2, 3)
-#define GDM_PID1_RXID_SEL BITS(0, 1)
-
-#define GDM_PRI_PID (0)
-#define GDM_PRI_VLAN_PID (1)
-#define GDM_PRI_ACK_PID (2)
-#define GDM_PRI_VLAN_ACK_PID (3)
-#define GDM_PRI_ACK_VLAN_PID (4)
-
-#define SET_GDM_VLAN_PRI_RXID_SEL(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
-reg_val &= ~(0x03 << (((x) << 1) + 16)); \
-reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \
-sys_reg_write(FE_GDM_RXID1, reg_val); \
-}
-
-#define SET_GDM_TCP_ACK_RXID_SEL(x) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
-reg_val &= ~(GDM_TCP_ACK_RXID_SEL); \
-reg_val |= ((x) & 0x3) << 4; \
-sys_reg_write(FE_GDM_RXID1, reg_val); \
-}
-
-#define SET_GDM_TCP_ACK_WZPC(x) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
-reg_val &= ~(GDM_TCP_ACK_WZPC); \
-reg_val |= ((x) & 0x1) << 3; \
-sys_reg_write(FE_GDM_RXID1, reg_val); \
-}
-
-#define SET_GDM_RXID_PRI_SEL(x) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID1); \
-reg_val &= ~(GDM_RXID_PRI_SEL); \
-reg_val |= (x) & 0x7; \
-sys_reg_write(FE_GDM_RXID1, reg_val); \
-}
-
-#define GDM_STAG_RXID_SEL(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
-reg_val &= ~(0x03 << (((x) << 1) + 16)); \
-reg_val |= ((y) & 0x3) << (((x) << 1) + 16); \
-sys_reg_write(FE_GDM_RXID2, reg_val); \
-}
-
-#define SET_GDM_PID2_RXID_SEL(x) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
-reg_val &= ~(GDM_PID2_RXID_SEL); \
-reg_val |= ((x) & 0x3) << 2; \
-sys_reg_write(FE_GDM_RXID2, reg_val); \
-}
-
-#define SET_GDM_PID1_RXID_SEL(x) \
-{ \
-unsigned int reg_val = sys_reg_read(FE_GDM_RXID2); \
-reg_val &= ~(GDM_PID1_RXID_SEL); \
-reg_val |= ((x) & 0x3); \
-sys_reg_write(FE_GDM_RXID2, reg_val); \
-}
-
-#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
-/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
-#define PORT0_PKCOUNT (0xb01100e8)
-#define PORT1_PKCOUNT (0xb01100ec)
-#define PORT2_PKCOUNT (0xb01100f0)
-#define PORT3_PKCOUNT (0xb01100f4)
-#define PORT4_PKCOUNT (0xb01100f8)
-#define PORT5_PKCOUNT (0xb01100fc)
-
-#define sys_reg_read(phys) (__raw_readl((void __iomem *)phys))
-#define sys_reg_write(phys, val) (__raw_writel(val, (void __iomem *)phys))
-
-/* ====================================== */
-#define GDM1_DISPAD BIT(18)
-#define GDM1_DISCRC BIT(17)
-
-/* GDMA1 uni-cast frames destination port */
-#define GDM1_ICS_EN (0x1 << 22)
-#define GDM1_TCS_EN (0x1 << 21)
-#define GDM1_UCS_EN (0x1 << 20)
-#define GDM1_JMB_EN (0x1 << 19)
-#define GDM1_STRPCRC (0x1 << 16)
-#define GDM1_UFRC_P_CPU (0 << 12)
-
-/* GDMA1 broad-cast MAC address frames */
-#define GDM1_BFRC_P_CPU (0 << 8)
-
-/* GDMA1 multi-cast MAC address frames */
-#define GDM1_MFRC_P_CPU (0 << 4)
-
-/* GDMA1 other MAC address frames destination port */
-#define GDM1_OFRC_P_CPU (0 << 0)
-
-/* checksum generator registers are removed */
-#define ICS_GEN_EN (0 << 2)
-#define UCS_GEN_EN (0 << 1)
-#define TCS_GEN_EN (0 << 0)
-
-/* MDIO_CFG bit */
-#define MDIO_CFG_GP1_FC_TX BIT(11)
-#define MDIO_CFG_GP1_FC_RX BIT(10)
-
-/* ====================================== */
-/* ====================================== */
-#define GP1_LNK_DWN BIT(9)
-#define GP1_AN_FAIL BIT(8)
-/* ====================================== */
-/* ====================================== */
-#define PSE_RESET BIT(0)
-/* ====================================== */
-#define PST_DRX_IDX3 BIT(19)
-#define PST_DRX_IDX2 BIT(18)
-#define PST_DRX_IDX1 BIT(17)
-#define PST_DRX_IDX0 BIT(16)
-#define PST_DTX_IDX3 BIT(3)
-#define PST_DTX_IDX2 BIT(2)
-#define PST_DTX_IDX1 BIT(1)
-#define PST_DTX_IDX0 BIT(0)
-
-#define RX_2B_OFFSET BIT(31)
-#define CSR_CLKGATE_BYP BIT(30)
-#define MULTI_EN BIT(10)
-#define DESC_32B_EN BIT(8)
-#define TX_WB_DDONE BIT(6)
-#define RX_DMA_BUSY BIT(3)
-#define TX_DMA_BUSY BIT(1)
-#define RX_DMA_EN BIT(2)
-#define TX_DMA_EN BIT(0)
-
-#define PDMA_BT_SIZE_4DWORDS (0 << 4)
-#define PDMA_BT_SIZE_8DWORDS BIT(4)
-#define PDMA_BT_SIZE_16DWORDS (2 << 4)
-#define PDMA_BT_SIZE_32DWORDS (3 << 4)
-#define PDMA_DESC_32B_E (1 << 8)
-
-#define ADMA_RX_BT_SIZE_4DWORDS (0 << 11)
-#define ADMA_RX_BT_SIZE_8DWORDS BIT(11)
-#define ADMA_RX_BT_SIZE_16DWORDS (2 << 11)
-#define ADMA_RX_BT_SIZE_32DWORDS (3 << 11)
-
-/* Register bits.
- */
-
-#define MACCFG_RXEN BIT(2)
-#define MACCFG_TXEN BIT(3)
-#define MACCFG_PROMISC BIT(18)
-#define MACCFG_RXMCAST BIT(19)
-#define MACCFG_FDUPLEX BIT(20)
-#define MACCFG_PORTSEL BIT(27)
-#define MACCFG_HBEATDIS BIT(28)
-
-#define DMACTL_SR BIT(1) /* Start/Stop Receive */
-#define DMACTL_ST BIT(13) /* Start/Stop Transmission Command */
-
-#define DMACFG_SWR BIT(0) /* Software Reset */
-#define DMACFG_BURST32 (32 << 8)
-
-#define DMASTAT_TS 0x00700000 /* Transmit Process State */
-#define DMASTAT_RS 0x000e0000 /* Receive Process State */
-
-#define MACCFG_INIT 0 /* (MACCFG_FDUPLEX) // | MACCFG_PORTSEL) */
-
-/* Descriptor bits.
- */
-#define R_OWN 0x80000000 /* Own Bit */
-#define RD_RER 0x02000000 /* Receive End Of Ring */
-#define RD_LS 0x00000100 /* Last Descriptor */
-#define RD_ES 0x00008000 /* Error Summary */
-#define RD_CHAIN 0x01000000 /* Chained */
-
-/* Word 0 */
-#define T_OWN 0x80000000 /* Own Bit */
-#define TD_ES 0x00008000 /* Error Summary */
-
-/* Word 1 */
-#define TD_LS 0x40000000 /* Last Segment */
-#define TD_FS 0x20000000 /* First Segment */
-#define TD_TER 0x08000000 /* Transmit End Of Ring */
-#define TD_CHAIN 0x01000000 /* Chained */
-
-#define TD_SET 0x08000000 /* Setup Packet */
-
-#define POLL_DEMAND 1
-
-#define RSTCTL (0x34)
-#define RSTCTL_RSTENET1 BIT(19)
-#define RSTCTL_RSTENET2 BIT(20)
-
-#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
-#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
-#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
-#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
-
-/* Define Whole FE Reset Register */
-#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
-#define RT2880_AGPIOCFG_REG (RALINK_SYSCTL_BASE + 0x3C)
-
-/*=========================================
- * PDMA RX Descriptor Format define
- *=========================================
- */
-
-struct PDMA_RXD_INFO1_T {
- unsigned int PDP0;
-};
-
-struct PDMA_RXD_INFO2_T {
- unsigned int PLEN1:2;
- unsigned int LRO_AGG_CNT:8;
- unsigned int REV:3;
- unsigned int FOE_ENTRY_32:1;
- unsigned int REV1:1;
- unsigned int TAG:1;
- unsigned int PLEN0:14;
- unsigned int LS0:1;
- unsigned int DDONE_bit:1;
-};
-
-struct PDMA_RXD_INFO3_T {
- unsigned int VID:16;
- unsigned int TPID:16;
-};
-
-struct PDMA_RXD_INFO4_T {
- unsigned int FOE_ENTRY:14;
- unsigned int CRSN:5;
- unsigned int SP:4;
- unsigned int L4F:1;
- unsigned int L4VLD:1;
- unsigned int TACK:1;
- unsigned int IP4F:1;
- unsigned int IP4:1;
- unsigned int IP6:1;
- unsigned int UN_USE1:3;
-};
-
-struct PDMA_rxdesc {
- struct PDMA_RXD_INFO1_T rxd_info1;
- struct PDMA_RXD_INFO2_T rxd_info2;
- struct PDMA_RXD_INFO3_T rxd_info3;
- struct PDMA_RXD_INFO4_T rxd_info4;
-#ifdef CONFIG_32B_DESC
- unsigned int rxd_info5;
- unsigned int rxd_info6;
- unsigned int rxd_info7;
- unsigned int rxd_info8;
-#endif
-};
-
-/*=========================================
- * PDMA TX Descriptor Format define
- *=========================================
- */
-struct PDMA_TXD_INFO1_T {
- unsigned int SDP0;
-};
-
-struct PDMA_TXD_INFO2_T {
- unsigned int SDL1:14;
- unsigned int LS1_bit:1;
- unsigned int BURST_bit:1;
- unsigned int SDL0:14;
- unsigned int LS0_bit:1;
- unsigned int DDONE_bit:1;
-};
-
-struct PDMA_TXD_INFO3_T {
- unsigned int SDP1;
-};
-
-struct PDMA_TXD_INFO4_T {
- unsigned int VLAN_TAG:17; /* INSV(1)+VPRI(3)+CFI(1)+VID(12) */
- unsigned int RESV:2;
- unsigned int UDF:5;
- unsigned int FPORT:4;
- unsigned int TSO:1;
- unsigned int TUI_CO:3;
-};
-
-struct PDMA_txdesc {
- struct PDMA_TXD_INFO1_T txd_info1;
- struct PDMA_TXD_INFO2_T txd_info2;
- struct PDMA_TXD_INFO3_T txd_info3;
- struct PDMA_TXD_INFO4_T txd_info4;
-#ifdef CONFIG_32B_DESC
- unsigned int txd_info5;
- unsigned int txd_info6;
- unsigned int txd_info7;
- unsigned int txd_info8;
-#endif
-};
-
-/*=========================================
- * QDMA TX Descriptor Format define
- *=========================================
- */
-struct QDMA_TXD_INFO1_T {
- unsigned int SDP;
-};
-
-struct QDMA_TXD_INFO2_T {
- unsigned int NDP;
-};
-
-struct QDMA_TXD_INFO3_T {
- unsigned int RSV0:6;
- unsigned int RSV1:2;
- unsigned int SDL:16;
- unsigned int RSV2:6;
- unsigned int LS:1;
- unsigned int DDONE:1;
-};
-
-struct QDMA_TXD_INFO4_T {
- unsigned int RSV0:6;
- unsigned int RSV1:2;
- unsigned int FPORT:4;
- unsigned int RSV2:2;
- unsigned int RSV3:2;
- unsigned int QID:7;
- unsigned int RSV4:1;
- unsigned int RSV5:6;
- unsigned int SWC:1;
- unsigned int BURST:1;
-};
-
-struct QDMA_TXD_INFO5_T {
- unsigned int PROT:3;
- unsigned int RSV0:2;
- unsigned int IPOFST:7;
- unsigned int RSV1:2;
- unsigned int VQID:10;
- unsigned int RSV2:2;
- unsigned int VQID0:1;
- unsigned int RSV3:1;
- unsigned int TUI_CO:3;
- unsigned int TSO:1;
-};
-
-struct QDMA_TXD_INFO6_T {
- unsigned int VLAN_TAG_1:16;
- unsigned int INSV_1:1;
- unsigned int RSV0:14;
- unsigned int INSV_0:1;
-};
-
-struct QDMA_TXD_INFO7_T {
- unsigned int VLAN_TAG_0:16;
- unsigned int VPID_0:16;
-};
-
-struct QDMA_TXD_INFO8_T {
- unsigned int RSV;
-};
-
-struct QDMA_txdesc {
- struct QDMA_TXD_INFO1_T txd_info1;
- struct QDMA_TXD_INFO2_T txd_info2;
- struct QDMA_TXD_INFO3_T txd_info3;
- struct QDMA_TXD_INFO4_T txd_info4;
- struct QDMA_TXD_INFO5_T txd_info5;
- struct QDMA_TXD_INFO6_T txd_info6;
- struct QDMA_TXD_INFO7_T txd_info7;
- struct QDMA_TXD_INFO8_T txd_info8;
-};
-
-#define QTXD_LEN (sizeof(struct QDMA_txdesc))
-#define PHY_ENABLE_AUTO_NEGO 0x1000
-#define PHY_RESTART_AUTO_NEGO 0x0200
-
-/* PHY_STAT_REG = 1; */
-#define PHY_AUTO_NEGO_COMP 0x0020
-#define PHY_LINK_STATUS 0x0004
-
-/* PHY_AUTO_NEGO_REG = 4; */
-#define PHY_CAP_10_HALF 0x0020
-#define PHY_CAP_10_FULL 0x0040
-#define PHY_CAP_100_HALF 0x0080
-#define PHY_CAP_100_FULL 0x0100
-
-/* proc definition */
-
-#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
-#if 0
-#if defined(CONFIG_MACH_MT7623)
-#define PROCREG_DIR "mt7623"
-#elif defined(CONFIG_MACH_LEOPARD)
-#define PROCREG_DIR "leopard"
-#elif defined(CONFIG_PINCTRL_MT7622)
-#define PROCREG_DIR "mt7622"
-#elif defined(CONFIG_SOC_MT7621)
-#define PROCREG_DIR "mt7621"
-#endif
-#endif
-#define PROCREG_DIR "panther"
-#define PROCREG_SKBFREE "skb_free"
-#define PROCREG_TXRING "tx_ring"
-#define PROCREG_RXRING "rx_ring"
-#define PROCREG_RXRING1 "rx_ring1"
-#define PROCREG_RXRING2 "rx_ring2"
-#define PROCREG_RXRING3 "rx_ring3"
-#define PROCREG_NUM_OF_TXD "num_of_txd"
-#define PROCREG_TSO_LEN "tso_len"
-#define PROCREG_LRO_STATS "lro_stats"
-#define PROCREG_HW_LRO_STATS "hw_lro_stats"
-#define PROCREG_HW_LRO_AUTO_TLB "hw_lro_auto_tlb"
-#define PROCREG_HW_IO_COHERENT "hw_iocoherent"
-#define PROCREG_GMAC "gmac"
-#define PROCREG_GMAC2 "gmac2"
-#define PROCREG_CP0 "cp0"
-#define PROCREG_RAQOS "qos"
-#define PROCREG_READ_VAL "regread_value"
-#define PROCREG_WRITE_VAL "regwrite_value"
-#define PROCREG_ADDR "reg_addr"
-#define PROCREG_CTL "procreg_control"
-#define PROCREG_RXDONE_INTR "rxdone_intr_count"
-#define PROCREG_ESW_INTR "esw_intr_count"
-#define PROCREG_ESW_CNT "esw_cnt"
-#define PROCREG_ETH_CNT "eth_cnt"
-#define PROCREG_SNMP "snmp"
-#define PROCREG_SET_LAN_IP "set_lan_ip"
-#if defined(TASKLET_WORKQUEUE_SW)
-#define PROCREG_SCHE "schedule"
-#endif
-#define PROCREG_QDMA "qdma"
-#define PROCREG_INT_DBG "int_dbg"
-struct rt2880_reg_op_data {
- char name[64];
- unsigned int reg_addr;
- unsigned int op;
- unsigned int reg_value;
-};
-
-struct lro_counters {
- u32 lro_aggregated;
- u32 lro_flushed;
- u32 lro_no_desc;
-};
-
-struct lro_para_struct {
- unsigned int lan_ip1;
-};
-
-struct parse_result {
- /* layer2 header */
- u8 dmac[6];
- u8 smac[6];
-
- /* vlan header */
- u16 vlan_tag;
- u16 vlan1_gap;
- u16 vlan1;
- u16 vlan2_gap;
- u16 vlan2;
- u16 vlan_layer;
-
- /* pppoe header */
- u32 pppoe_gap;
- u16 ppp_tag;
- u16 pppoe_sid;
-
- /* layer3 header */
- u16 eth_type;
- struct iphdr iph;
- struct ipv6hdr ip6h;
-
- /* layer4 header */
- struct tcphdr th;
- struct udphdr uh;
-
- u32 pkt_type;
- u8 is_mcast;
-};
-
-#define DMA_GLO_CFG PDMA_GLO_CFG
-
-#if defined(CONFIG_RAETH_QDMATX_QDMARX)
-#define GDMA1_FWD_PORT 0x5555
-#define GDMA2_FWD_PORT 0x5555
-#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
-#define GDMA1_FWD_PORT 0x5555
-#define GDMA2_FWD_PORT 0x5555
-#else
-#define GDMA1_FWD_PORT 0x0000
-#define GDMA2_FWD_PORT 0x0000
-#endif
-
-#if defined(CONFIG_RAETH_QDMATX_QDMARX)
-#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
-#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
-#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
-#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
-#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
-#else
-#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
-#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
-#endif
-#define RAETH_RX_CALC_IDX2 RX_CALC_IDX2
-#define RAETH_RX_CALC_IDX3 RX_CALC_IDX3
-#define RAETH_FE_INT_STATUS FE_INT_STATUS
-#define RAETH_FE_INT_ALL FE_INT_ALL
-#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
-#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
-#define RAETH_FE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \
- TX_DONE_INT0 | TX_DONE_INT1 | \
- TX_DONE_INT2 | TX_DONE_INT3)
-#define QFE_INT_SETTING (RX_DONE_INT0 | RX_DONE_INT1 | \
- TX_DONE_INT0 | TX_DONE_INT1 | \
- TX_DONE_INT2 | TX_DONE_INT3)
-#define RAETH_TX_DLY_INT TX_DLY_INT
-#define RAETH_TX_DONE_INT0 TX_DONE_INT0
-#define RAETH_DLY_INT_CFG DLY_INT_CFG
-
-/* io-coherent for ethdmasys */
-#define IOC_ETH_PDMA BIT(0)
-#define IOC_ETH_QDMA BIT(1)
-
-#endif /* RAETH_REG_H */
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.c
deleted file mode 100644
index 62f2c8c..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.c
+++ /dev/null
@@ -1,3426 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/phy.h>
-#include <linux/of_device.h>
-#include <linux/of_mdio.h>
-#include <linux/of_net.h>
-
-#include "raether.h"
-#include "ra_mac.h"
-#include "ra_ioctl.h"
-#include "ra_switch.h"
-#include "raether_hwlro.h"
-#include "ra_ethtool.h"
-
-void __iomem *ethdma_sysctl_base;
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
-EXPORT_SYMBOL(ethdma_sysctl_base);
-#endif
-void __iomem *ethdma_frame_engine_base;
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
-EXPORT_SYMBOL(ethdma_frame_engine_base);
-#endif
-struct net_device *dev_raether;
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
-EXPORT_SYMBOL(dev_raether);
-#endif
-void __iomem *ethdma_mac_base;
-
-static int pending_recv;
-
-/* LRO support */
-unsigned int lan_ip;
-struct lro_para_struct lro_para;
-u32 gmac1_txq_num;
-EXPORT_SYMBOL(gmac1_txq_num);
-u32 gmac1_txq_txd_num;
-EXPORT_SYMBOL(gmac1_txq_txd_num);
-u32 gmac1_txd_num;
-EXPORT_SYMBOL(gmac1_txd_num);
-u32 gmac2_txq_num;
-EXPORT_SYMBOL(gmac2_txq_num);
-u32 gmac2_txq_txd_num;
-EXPORT_SYMBOL(gmac2_txq_txd_num);
-u32 gmac2_txd_num;
-EXPORT_SYMBOL(gmac2_txd_num);
-u32 num_rx_desc;
-EXPORT_SYMBOL(num_rx_desc);
-u32 num_tx_max_process;
-EXPORT_SYMBOL(num_tx_max_process);
-u32 num_tx_desc;
-EXPORT_SYMBOL(num_tx_desc);
-u32 total_txq_num;
-EXPORT_SYMBOL(total_txq_num);
-
-static const char *const mtk_clks_source_name[] = {
- "ethif", "esw", "gp0", "gp1", "gp2",
- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
- "sgmii1_tx250m", "sgmii1_rx250m", "sgmii1_cdr_ref", "sgmii1_cdr_fb",
- "trgpll", "sgmipll", "eth1pll", "eth2pll", "eth", "sgmiitop"
-};
-
-/* reset frame engine */
-static void fe_reset(void)
-{
- u32 val;
-
- val = sys_reg_read(RSTCTRL);
- val = val | RALINK_FE_RST;
- sys_reg_write(RSTCTRL, val);
-
- val = val & ~(RALINK_FE_RST);
- sys_reg_write(RSTCTRL, val);
-}
-
-static void fe_gmac_reset(void)
-{
- u32 val;
- /*Reset GMAC */
- /* sys_reg_write(RALINK_SYSCTL_BASE + 0x34, 0x00800000); */
- /* sys_reg_write(RALINK_SYSCTL_BASE + 0x34, 0x00000000); */
- val = sys_reg_read(RALINK_SYSCTL_BASE + 0x34);
- val |= (1 << 23);
- sys_reg_write(RALINK_SYSCTL_BASE + 0x34, val);
- val &= ~(1 << 23);
- sys_reg_write(RALINK_SYSCTL_BASE + 0x34, val);
-}
-
-/* Set the hardware MAC address. */
-static int ei_set_mac_addr(struct net_device *dev, void *p)
-{
- struct sockaddr *addr = p;
-
- if (!is_valid_ether_addr(addr->sa_data))
- return -EADDRNOTAVAIL;
-
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- if (netif_running(dev))
- return -EBUSY;
-
- set_mac_address(dev->dev_addr);
-
- return 0;
-}
-
-static int ei_set_mac2_addr(struct net_device *dev, void *p)
-{
- struct sockaddr *addr = p;
-
- if (!is_valid_ether_addr(addr->sa_data))
- return -EADDRNOTAVAIL;
-
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- if (netif_running(dev))
- return -EBUSY;
-
- set_mac2_address(dev->dev_addr);
-
- return 0;
-}
-
-static void ei_reset_statistics(struct END_DEVICE *ei_local)
-{
- ei_local->stat.tx_packets = 0;
- ei_local->stat.tx_bytes = 0;
- ei_local->stat.tx_dropped = 0;
- ei_local->stat.tx_errors = 0;
- ei_local->stat.tx_aborted_errors = 0;
- ei_local->stat.tx_carrier_errors = 0;
- ei_local->stat.tx_fifo_errors = 0;
- ei_local->stat.tx_heartbeat_errors = 0;
- ei_local->stat.tx_window_errors = 0;
-
- ei_local->stat.rx_packets = 0;
- ei_local->stat.rx_bytes = 0;
- ei_local->stat.rx_dropped = 0;
- ei_local->stat.rx_errors = 0;
- ei_local->stat.rx_length_errors = 0;
- ei_local->stat.rx_over_errors = 0;
- ei_local->stat.rx_crc_errors = 0;
- ei_local->stat.rx_frame_errors = 0;
- ei_local->stat.rx_fifo_errors = 0;
- ei_local->stat.rx_missed_errors = 0;
-
- ei_local->stat.collisions = 0;
-}
-
-static inline void fe_rx_desc_init(struct PDMA_rxdesc *rx_ring,
- dma_addr_t dma_addr)
-{
- rx_ring->rxd_info1.PDP0 = dma_addr;
- rx_ring->rxd_info2.PLEN0 = MAX_RX_LENGTH;
- rx_ring->rxd_info2.LS0 = 0;
- rx_ring->rxd_info2.DDONE_bit = 0;
-}
-
-static int rt2880_eth_recv(struct net_device *dev,
- struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- unsigned int length = 0;
- int rx_processed = 0;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- unsigned int rx_dma_owner_idx, rx_next_idx;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int skb_size;
-
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- rx_dma_owner_idx = (ei_local->rx_calc_idx[0] + 1) % num_rx_desc;
-#else
- rx_dma_owner_idx = (sys_reg_read(RAETH_RX_CALC_IDX0) + 1) % num_rx_desc;
-#endif
- rx_ring = &ei_local->rx_ring[0][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[0][rx_dma_owner_idx];
-
- skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- rx_next_idx = (rx_dma_owner_idx + 1) % num_rx_desc;
- rx_ring_next = &ei_local->rx_ring[0][rx_next_idx];
- rx_data_next = ei_local->netrx_skb_data[0][rx_next_idx];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_err("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- MAX_RX_LENGTH, DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_err("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_err("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (likely(ei_local->pseudo_dev)) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_err("pseudo_dev is still not initialize ");
- pr_err("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (rx_ring->rxd_info4.L4VLD)
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- if (IS_SPACE_AVAILABLE_HEAD(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- }
- if (IS_SPACE_AVAILABLE_TAIL(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
- }
-#endif
-
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI)
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- else
- netif_rx(rx_skb);
-
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* init RX desc. */
- fe_rx_desc_init(rx_ring, dma_addr);
- ei_local->netrx_skb_data[0][rx_dma_owner_idx] = new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
-
- sys_reg_write(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- ei_local->rx_calc_idx[0] = rx_dma_owner_idx;
-#endif
-
- /* Update to Next packet point that was received.
- */
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- rx_dma_owner_idx = rx_next_idx;
-#else
- rx_dma_owner_idx =
- (sys_reg_read(RAETH_RX_CALC_IDX0) + 1) % num_rx_desc;
-#endif
-
- /* use prefetched variable */
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- fe_rx_desc_init(rx_ring, rx_ring->rxd_info1.PDP0);
-
- /* make sure that all changes to the dma ring
- * are flushed before we continue
- */
- wmb();
-
- sys_reg_write(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- ei_local->rx_calc_idx[0] = rx_dma_owner_idx;
-#endif
-
- return (budget + 1);
-}
-
-static int raeth_poll_full(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_val_rx, reg_int_val_tx;
- unsigned long reg_int_mask_rx, reg_int_mask_tx;
- unsigned long flags;
- int tx_done = 0, rx_done = 0;
-
- reg_int_val_tx = sys_reg_read(ei_local->fe_tx_int_status);
- reg_int_val_rx = sys_reg_read(ei_local->fe_rx_int_status);
-
- if (reg_int_val_tx & ei_local->tx_mask) {
- /* Clear TX interrupt status */
- sys_reg_write(ei_local->fe_tx_int_status, (TX_DLY_INT | TX_DONE_INT0));
- tx_done = ei_local->ei_xmit_housekeeping(netdev,
- num_tx_max_process);
- }
-
- if (reg_int_val_rx & ei_local->rx_mask) {
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RX_INT_ALL);
- rx_done = ei_local->ei_eth_recv(netdev, napi, budget);
- }
-
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable TX/RX interrupts */
- reg_int_mask_tx = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask_tx | ei_local->tx_mask);
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask_rx | ei_local->rx_mask);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_rx_rss0(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_rx_rss0);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_mask_rx;
- unsigned long flags;
- int rx_done = 0;
-
- rx_done = ei_local->ei_eth_recv_rss0(netdev, napi, budget);
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable RX interrupt */
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- (reg_int_mask_rx | RING0_RX_DLY_INT));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_rx_rss1(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_rx_rss1);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_mask_rx;
- unsigned long flags;
- int rx_done = 0;
-
- rx_done = ei_local->ei_eth_recv_rss1(netdev, napi, budget);
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable RX interrupt */
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- (reg_int_mask_rx | RING1_RX_DLY_INT));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_rx_rss2(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_rx_rss2);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_mask_rx;
- unsigned long flags;
- int rx_done = 0;
-
- rx_done = ei_local->ei_eth_recv_rss2(netdev, napi, budget);
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable RX interrupt */
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- (reg_int_mask_rx | RING2_RX_DLY_INT));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_rx_rss3(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_rx_rss3);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_mask_rx;
- unsigned long flags;
- int rx_done = 0;
-
- rx_done = ei_local->ei_eth_recv_rss3(netdev, napi, budget);
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable RX interrupt */
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- (reg_int_mask_rx | RING3_RX_DLY_INT));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_rx(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_rx);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_mask_rx;
- unsigned long flags;
- int rx_done = 0;
-
- rx_done = ei_local->ei_eth_recv(netdev, napi, budget);
- if (rx_done >= budget)
- return budget;
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Enable RX interrupt */
- reg_int_mask_rx = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- (reg_int_mask_rx | ei_local->rx_mask));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return rx_done;
-}
-
-static int raeth_poll_tx(struct napi_struct *napi, int budget)
-{
- struct END_DEVICE *ei_local =
- container_of(napi, struct END_DEVICE, napi_tx);
- struct net_device *netdev = ei_local->netdev;
- unsigned long reg_int_val_tx;
- unsigned long reg_int_mask_tx;
- unsigned long flags;
- int tx_done = 0;
-
- reg_int_val_tx = sys_reg_read(ei_local->fe_tx_int_status);
-
- if (reg_int_val_tx & ei_local->tx_mask) {
- /* Clear TX interrupt status */
- sys_reg_write(ei_local->fe_tx_int_status, TX_INT_ALL);
- tx_done = ei_local->ei_xmit_housekeeping(netdev,
- num_tx_max_process);
- }
-
- napi_complete(napi);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Enable TX interrupts */
- reg_int_mask_tx = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask_tx | ei_local->tx_mask);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return 1;
-}
-
-static void ei_func_register(struct END_DEVICE *ei_local)
-{
- /* TX handling */
- if (ei_local->features & FE_QDMA_TX) {
- ei_local->ei_start_xmit = ei_qdma_start_xmit;
- ei_local->ei_xmit_housekeeping = ei_qdma_xmit_housekeeping;
- ei_local->fe_tx_int_status = (void __iomem *)QFE_INT_STATUS;
- ei_local->fe_tx_int_enable = (void __iomem *)QFE_INT_ENABLE;
- } else {
- ei_local->ei_start_xmit = ei_pdma_start_xmit;
- ei_local->ei_xmit_housekeeping = ei_pdma_xmit_housekeeping;
- ei_local->fe_tx_int_status =
- (void __iomem *)RAETH_FE_INT_STATUS;
- ei_local->fe_tx_int_enable =
- (void __iomem *)RAETH_FE_INT_ENABLE;
- }
-
- /* RX handling */
- if (ei_local->features & FE_QDMA_RX) {
- ei_local->fe_rx_int_status = (void __iomem *)QFE_INT_STATUS;
- ei_local->fe_rx_int_enable = (void __iomem *)QFE_INT_ENABLE;
- } else {
- ei_local->fe_rx_int_status =
- (void __iomem *)RAETH_FE_INT_STATUS;
- ei_local->fe_rx_int_enable =
- (void __iomem *)RAETH_FE_INT_ENABLE;
- }
-
- /* HW LRO handling */
- if (ei_local->features & FE_HW_LRO) {
- ei_local->ei_eth_recv = fe_hw_lro_recv;
- } else if (ei_local->features & FE_RSS_4RING) {
- ei_local->ei_eth_recv_rss0 = fe_rss0_recv;
- ei_local->ei_eth_recv_rss1 = fe_rss1_recv;
- ei_local->ei_eth_recv_rss2 = fe_rss2_recv;
- ei_local->ei_eth_recv_rss3 = fe_rss3_recv;
- } else if (ei_local->features & FE_RSS_2RING) {
- ei_local->ei_eth_recv_rss0 = fe_rss0_recv;
- ei_local->ei_eth_recv_rss1 = fe_rss1_recv;
- } else {
- ei_local->ei_eth_recv = rt2880_eth_recv;
- }
-}
-
-static int __init ei_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- fe_reset();
-
- if (ei_local->features & FE_INT_NAPI) {
- /* we run 2 devices on the same DMA ring */
- /* so we need a dummy device for NAPI to work */
- init_dummy_netdev(&ei_local->dummy_dev);
-
- if (ei_local->features & FE_INT_NAPI_TX_RX) {
- netif_napi_add(&ei_local->dummy_dev, &ei_local->napi_rx,
- raeth_poll_rx, MTK_NAPI_WEIGHT);
- netif_napi_add(&ei_local->dummy_dev, &ei_local->napi_tx,
- raeth_poll_tx, MTK_NAPI_WEIGHT);
-
- } else if (ei_local->features & FE_INT_NAPI_RX_ONLY) {
- if (ei_local->features & FE_RSS_4RING) {
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss0,
- raeth_poll_rx_rss0, MTK_NAPI_WEIGHT);
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss1,
- raeth_poll_rx_rss1, MTK_NAPI_WEIGHT);
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss2,
- raeth_poll_rx_rss2, MTK_NAPI_WEIGHT);
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss3,
- raeth_poll_rx_rss3, MTK_NAPI_WEIGHT);
- } else if (ei_local->features & FE_RSS_2RING) {
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss0,
- raeth_poll_rx_rss0, MTK_NAPI_WEIGHT);
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx_rss1,
- raeth_poll_rx_rss1, MTK_NAPI_WEIGHT);
- } else {
- netif_napi_add(&ei_local->dummy_dev,
- &ei_local->napi_rx,
- raeth_poll_rx, MTK_NAPI_WEIGHT);
- }
- } else {
- netif_napi_add(&ei_local->dummy_dev, &ei_local->napi,
- raeth_poll_full, MTK_NAPI_WEIGHT);
- }
- }
-
- spin_lock_init(&ei_local->page_lock);
- spin_lock_init(&ei_local->irq_lock);
- spin_lock_init(&ei_local->mdio_lock);
- ether_setup(dev);
-
- ei_func_register(ei_local);
-
- /* init my IP */
- strncpy(ei_local->lan_ip4_addr, FE_DEFAULT_LAN_IP, IP4_ADDR_LEN);
-
- if (ei_local->chip_name == MT7621_FE) {
- fe_gmac_reset();
- fe_sw_init();
- }
-
- return 0;
-}
-
-static void ei_uninit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- unregister_netdev(dev);
- free_netdev(dev);
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- unregister_netdev(ei_local->pseudo_dev);
- free_netdev(ei_local->pseudo_dev);
- }
-
- pr_info("Free ei_local and unregister netdev...\n");
-
- debug_proc_exit();
-}
-static void ei_mac_addr_setting(struct net_device *dev)
-{
- /* If the mac address is invalid, use random mac address */
- if (!is_valid_ether_addr(dev->dev_addr)) {
- random_ether_addr(dev->dev_addr);
- dev->addr_assign_type = NET_ADDR_RANDOM;
- }
-
- ei_set_mac_addr(dev, dev->dev_addr);
-}
-
-static void ei_mac2_addr_setting(struct net_device *dev)
-{
- /* If the mac address is invalid, use random mac address */
- if (!is_valid_ether_addr(dev->dev_addr)) {
- random_ether_addr(dev->dev_addr);
- dev->addr_assign_type = NET_ADDR_RANDOM;
- }
-}
-
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
-static void fe_dma_rx_cal_idx_init(struct END_DEVICE *ei_local)
-{
- if (unlikely(ei_local->features & FE_QDMA_RX)) {
- ei_local->rx_calc_idx[0] = sys_reg_read(QRX_CRX_IDX_0);
- } else { /* PDMA RX */
- ei_local->rx_calc_idx[0] = sys_reg_read(RX_CALC_IDX0);
- if (ei_local->features & (FE_HW_LRO | FE_RSS_4RING)) {
- ei_local->rx_calc_idx[1] = sys_reg_read(RX_CALC_IDX1);
- ei_local->rx_calc_idx[2] = sys_reg_read(RX_CALC_IDX2);
- ei_local->rx_calc_idx[3] = sys_reg_read(RX_CALC_IDX3);
- } else if (ei_local->features & FE_RSS_2RING) {
- ei_local->rx_calc_idx[1] = sys_reg_read(RX_CALC_IDX1);
- }
- }
-}
-#endif
-
-static inline int ei_init_ptx_prx(struct net_device *dev)
-{
- int err;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- err = fe_pdma_wait_dma_idle();
- if (err)
- return err;
-
- err = fe_pdma_rx_dma_init(dev);
- if (err)
- return err;
-
- if (ei_local->features & FE_HW_LRO) {
- err = fe_hw_lro_init(dev);
- if (err)
- return err;
- } else if (ei_local->features & FE_RSS_4RING) {
- err = fe_rss_4ring_init(dev);
- if (err)
- return err;
- } else if (ei_local->features & FE_RSS_2RING) {
- err = fe_rss_2ring_init(dev);
- if (err)
- return err;
- }
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- fe_dma_rx_cal_idx_init(ei_local);
-#endif
-
- err = fe_pdma_tx_dma_init(dev);
- if (err)
- return err;
-
- set_fe_pdma_glo_cfg();
-
- /* enable RXD prefetch of ADMA */
- SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN |
- ADMA_MULTI_RXD_PREFETCH_EN);
-
- return 0;
-}
-
-static inline int ei_init_qtx_prx(struct net_device *dev)
-{
- int err;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- err = fe_pdma_wait_dma_idle();
- if (err)
- return err;
-
- err = fe_qdma_wait_dma_idle();
- if (err)
- return err;
-
- err = fe_qdma_rx_dma_init(dev);
- if (err)
- return err;
-
- err = fe_pdma_rx_dma_init(dev);
- if (err)
- return err;
-
- if (ei_local->features & FE_HW_LRO) {
- err = fe_hw_lro_init(dev);
- if (err)
- return err;
- } else if (ei_local->features & FE_RSS_4RING) {
- err = fe_rss_4ring_init(dev);
- if (err)
- return err;
- } else if (ei_local->features & FE_RSS_2RING) {
- err = fe_rss_2ring_init(dev);
- if (err)
- return err;
- }
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- fe_dma_rx_cal_idx_init(ei_local);
-#endif
-
- err = fe_qdma_tx_dma_init(dev);
- if (err)
- return err;
-
- set_fe_pdma_glo_cfg();
- set_fe_qdma_glo_cfg();
-
- /* enable RXD prefetch of ADMA */
- SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN |
- ADMA_MULTI_RXD_PREFETCH_EN);
-
- return 0;
-}
-
-static inline int ei_init_qtx_qrx(struct net_device *dev)
-{
- int err;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- err = fe_qdma_wait_dma_idle();
- if (err)
- return err;
-
- err = fe_qdma_rx_dma_init(dev);
- if (err)
- return err;
-
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- fe_dma_rx_cal_idx_init(ei_local);
-#endif
-
- err = fe_qdma_tx_dma_init(dev);
- if (err)
- return err;
-
- set_fe_qdma_glo_cfg();
-
- return 0;
-}
-
-static int ei_init_dma(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- if ((ei_local->features & FE_QDMA_TX) &&
- (ei_local->features & FE_QDMA_RX))
- return ei_init_qtx_qrx(dev);
-
- if (ei_local->features & FE_QDMA_TX)
- return ei_init_qtx_prx(dev);
- else
- return ei_init_ptx_prx(dev);
-}
-
-static void ei_deinit_dma(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- if (ei_local->features & FE_QDMA_TX) {
- fe_qdma_tx_dma_deinit(dev);
- fe_qdma_rx_dma_deinit(dev);
- } else {
- fe_pdma_tx_dma_deinit(dev);
- }
-
- if (!(ei_local->features & FE_QDMA_RX))
- fe_pdma_rx_dma_deinit(dev);
-
- if (ei_local->features & FE_HW_LRO)
- fe_hw_lro_deinit(dev);
- else if (ei_local->features & FE_RSS_4RING)
- fe_rss_4ring_deinit(dev);
- else if (ei_local->features & FE_RSS_2RING)
- fe_rss_2ring_deinit(dev);
-
- pr_info("Free TX/RX Ring Memory!\n");
-}
-
-/* MT7623 PSE reset workaround to do PSE reset */
-void fe_do_reset(void)
-{
- u32 adma_rx_dbg0_r = 0;
- u32 dbg_rx_curr_state, rx_fifo_wcnt;
- u32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty;
- u32 reg_tmp, loop_count;
- unsigned long flags;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- ei_local->fe_reset_times++;
- /* do CDM/PDMA reset */
- pr_crit("[%s] CDM/PDMA reset (%d times)!!!\n", __func__,
- ei_local->fe_reset_times);
- spin_lock_irqsave(&ei_local->page_lock, flags);
- reg_tmp = sys_reg_read(FE_GLO_MISC);
- reg_tmp |= 0x1;
- sys_reg_write(FE_GLO_MISC, reg_tmp);
- mdelay(10);
- reg_tmp = sys_reg_read(ADMA_LRO_CTRL_DW3);
- reg_tmp |= (0x1 << 14);
- sys_reg_write(ADMA_LRO_CTRL_DW3, reg_tmp);
- loop_count = 0;
- do {
- adma_rx_dbg0_r = sys_reg_read(ADMA_RX_DBG0);
- dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f;
- rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f;
- dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1;
- dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1;
- loop_count++;
- if (loop_count >= 100) {
- pr_err("[%s] loop_count timeout!!!\n", __func__);
- break;
- }
- mdelay(10);
- } while (((dbg_rx_curr_state != 0x17) && (dbg_rx_curr_state != 0x00)) ||
- (rx_fifo_wcnt != 0) ||
- (!dbg_cdm_lro_rinf_afifo_rempty) ||
- (!dbg_cdm_eof_rdy_afifo_empty));
- reg_tmp = sys_reg_read(ADMA_LRO_CTRL_DW3);
- reg_tmp &= 0xffffbfff;
- sys_reg_write(ADMA_LRO_CTRL_DW3, reg_tmp);
- reg_tmp = sys_reg_read(FE_GLO_MISC);
- reg_tmp &= 0xfffffffe;
- sys_reg_write(FE_GLO_MISC, reg_tmp);
- spin_unlock_irqrestore(&ei_local->page_lock, flags);
-}
-
-/* MT7623 PSE reset workaround to poll if PSE hang */
-static int fe_reset_thread(void *data)
-{
- u32 adma_rx_dbg0_r = 0;
- u32 dbg_rx_curr_state, rx_fifo_wcnt;
- u32 dbg_cdm_lro_rinf_afifo_rempty, dbg_cdm_eof_rdy_afifo_empty;
-
- pr_info("%s called\n", __func__);
-
- for (;;) {
- adma_rx_dbg0_r = sys_reg_read(ADMA_RX_DBG0);
- dbg_rx_curr_state = (adma_rx_dbg0_r >> 16) & 0x7f;
- rx_fifo_wcnt = (adma_rx_dbg0_r >> 8) & 0x3f;
- dbg_cdm_lro_rinf_afifo_rempty = (adma_rx_dbg0_r >> 7) & 0x1;
- dbg_cdm_eof_rdy_afifo_empty = (adma_rx_dbg0_r >> 6) & 0x1;
-
- /* check if PSE P0 hang */
- if (dbg_cdm_lro_rinf_afifo_rempty &&
- dbg_cdm_eof_rdy_afifo_empty &&
- (rx_fifo_wcnt & 0x20) &&
- ((dbg_rx_curr_state == 0x17) ||
- (dbg_rx_curr_state == 0x00))) {
- fe_do_reset();
- }
-
- msleep_interruptible(FE_RESET_POLLING_MS);
- if (kthread_should_stop())
- break;
- }
-
- pr_info("%s leaved\n", __func__);
- return 0;
-}
-
-static int phy_polling_thread(void *data)
-{
- unsigned int link_status, link_speed, duplex;
- unsigned int local_eee, lp_eee;
- unsigned int fc_phy, fc_lp;
- unsigned int val_tmp;
-
- pr_info("%s called\n", __func__);
- val_tmp = 1;
- for (;;) {
- mii_mgr_read(0x0, 0x1, &link_status);
- link_status = (link_status >> 2) & 0x1;
- if (link_status) {
- mii_mgr_read(0x0, 0x4, &fc_phy);
- mii_mgr_read(0x0, 0x5, &fc_lp);
- if ((fc_phy & 0xc00) == (fc_lp & 0xc00))
- val_tmp = val_tmp | 0x30;
- else
- val_tmp = val_tmp & (~0x30);
- mii_mgr_read_cl45(0, 0x1e, 0xa2, &link_speed);
- duplex = link_speed & 0x20;
- if (duplex)
- val_tmp = val_tmp | 0x2;
- else
- val_tmp = val_tmp & (~0x2);
- link_speed = link_speed & 0xe;
- val_tmp = val_tmp & (~0xc);
- if (link_speed == 0x04)
- val_tmp = val_tmp | (0x4);
- else if (link_speed == 0x08)
- val_tmp = val_tmp | (0x8);
- mii_mgr_read_cl45(0, 0x7, 0x3c, &local_eee);
- mii_mgr_read_cl45(0, 0x7, 0x3d, &lp_eee);
- if ((local_eee & 0x4) == 4 && (lp_eee & 0x4) == 4)/*1g eee*/
- val_tmp = val_tmp | 0x80;
- if ((local_eee & 0x2) == 2 && ((lp_eee & 0x2) == 2))/*100m eee*/
- val_tmp = val_tmp | 0x40;
- val_tmp = val_tmp & 0xff;
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x200, 0x2105e300 | val_tmp);
- } else {
- /*force link down*/
- set_ge2_force_link_down();
- }
-
- msleep_interruptible(PHY_POLLING_MS);
- if (kthread_should_stop())
- break;
- }
-
- pr_info("%s leaved\n", __func__);
- return 0;
-}
-
-#if 0
-static irqreturn_t ei_interrupt_napi_rx_only(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int reg_int_mask;
- unsigned long flags;
-
- if (likely(napi_schedule_prep(&ei_local->napi_rx))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RX_INT_ALL);
-
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask & ~(RX_INT_ALL));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi_rx);
- }
-
- return IRQ_HANDLED;
-}
-static irqreturn_t ei_interrupt_napi(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned long flags;
-
- if (likely(napi_schedule_prep(&ei_local->napi))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable TX interrupt */
- sys_reg_write(ei_local->fe_tx_int_enable, 0);
- /* Disable RX interrupt */
- sys_reg_write(ei_local->fe_rx_int_enable, 0);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi);
- }
-
- return IRQ_HANDLED;
-}
-#endif
-static irqreturn_t ei_interrupt_napi_sep(int irq, void *dev_id)
-{
- struct net_device *dev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int reg_int_mask;
- unsigned long flags;
-
- if (likely(napi_schedule_prep(&ei_local->napi_tx))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable TX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask & ~(TX_INT_ALL));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi_tx);
- }
-
- if (likely(napi_schedule_prep(&ei_local->napi_rx))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask & ~(RX_INT_ALL));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi_rx);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_interrupt(int irq, void *dev_id)
-{
- unsigned long reg_int_val = 0;
- unsigned long reg_int_val_p = 0;
- unsigned long reg_int_val_q = 0;
- unsigned long reg_int_mask = 0;
- unsigned int recv = 0;
-
- unsigned int transmit __maybe_unused = 0;
- unsigned long flags;
-
- struct net_device *dev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- if (!dev) {
- pr_err("net_interrupt(): irq %x for unknown device.\n",
- IRQ_ENET0);
- return IRQ_NONE;
- }
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- reg_int_val_p = sys_reg_read(RAETH_FE_INT_STATUS);
-
- if (ei_local->features & FE_QDMA)
- reg_int_val_q = sys_reg_read(QFE_INT_STATUS);
- reg_int_val = reg_int_val_p | reg_int_val_q;
-
- if (reg_int_val & ei_local->rx_mask)
- recv = 1;
- if (reg_int_val & ei_local->tx_mask)
- transmit = 1;
- if (ei_local->features & FE_QDMA)
- sys_reg_write(QFE_INT_STATUS, reg_int_val_q);
-
- ei_local->ei_xmit_housekeeping(dev, num_tx_max_process);
-
- /* QWERT */
- sys_reg_write(RAETH_FE_INT_STATUS, reg_int_val_p);
-
- if (((recv == 1) || (pending_recv == 1)) &&
- (ei_local->tx_ring_full == 0)) {
- reg_int_mask = sys_reg_read(RAETH_FE_INT_ENABLE);
-
- sys_reg_write(RAETH_FE_INT_ENABLE,
- reg_int_mask & ~(ei_local->rx_mask));
- /*QDMA RX*/
- if (ei_local->features & FE_QDMA) {
- reg_int_mask = sys_reg_read(QFE_INT_ENABLE);
- if (ei_local->features & FE_DLY_INT)
- sys_reg_write(QFE_INT_ENABLE,
- reg_int_mask & ~(RX_DLY_INT));
- else
- sys_reg_write(QFE_INT_ENABLE,
- reg_int_mask & ~(RX_DONE_INT0 |
- RX_DONE_INT1 |
- RX_DONE_INT2 |
- RX_DONE_INT3));
- }
-
- pending_recv = 0;
-
- if (ei_local->features & FE_INT_WORKQ)
- schedule_work(&ei_local->rx_wq);
- else
- tasklet_hi_schedule(&ei_local->rx_tasklet);
- } else if (recv == 1 && ei_local->tx_ring_full == 1) {
- pending_recv = 1;
- }
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val;
- unsigned long flags;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- if (likely(reg_int_val & RX_INT_ALL)) {
- if (likely(napi_schedule_prep(&ei_local->napi))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable RX interrupt */
- sys_reg_write(ei_local->fe_rx_int_enable, 0);
- /* Disable TX interrupt */
- sys_reg_write(ei_local->fe_tx_int_enable, 0);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi);
- }
- } else {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Ack other interrupt status except TX irqs */
- reg_int_val &= ~(TX_INT_ALL);
- sys_reg_write(ei_local->fe_rx_int_status, reg_int_val);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi_g0(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val, reg_int_val_0, reg_int_val_1, reg_int_mask;
- unsigned long flags;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- reg_int_val_0 = reg_int_val & RSS_RX_RING0;
- reg_int_val_1 = reg_int_val & RSS_RX_RING1;
- if (likely(reg_int_val_0)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING0));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING0);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- if (likely(reg_int_val_1)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING1));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING1);
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- if (likely(reg_int_val_0)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss0)))
- __napi_schedule(&ei_local->napi_rx_rss0);
- }
-
- if (likely(reg_int_val_1)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss1)))
- __napi_schedule(&ei_local->napi_rx_rss1);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi_rss0(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val, reg_int_val_0, reg_int_mask;
- unsigned long flags;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- reg_int_val_0 = reg_int_val & RSS_RX_RING0;
- if (likely(reg_int_val_0)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING0));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING0);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- if (likely(reg_int_val_0)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss0)))
- __napi_schedule(&ei_local->napi_rx_rss0);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi_rss1(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val, reg_int_val_1, reg_int_mask;
- unsigned long flags;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- reg_int_val_1 = reg_int_val & RSS_RX_RING1;
-
- if (likely(reg_int_val_1)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING1));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING1);
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
-
- if (likely(reg_int_val_1)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss1)))
- __napi_schedule(&ei_local->napi_rx_rss1);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi_g1(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val, reg_int_val_0, reg_int_val_1, reg_int_mask;
- unsigned long flags;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- reg_int_val_0 = reg_int_val & RSS_RX_RING2;
- reg_int_val_1 = reg_int_val & RSS_RX_RING3;
- if (likely(reg_int_val_0)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING2));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING2);
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- if (likely(reg_int_val_1)) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable, reg_int_mask & ~(RSS_RX_RING3));
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RSS_RX_RING3);
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- if (likely(reg_int_val_0)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss2)))
- __napi_schedule(&ei_local->napi_rx_rss2);
- }
-
- if (likely(reg_int_val_1)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx_rss3)))
- __napi_schedule(&ei_local->napi_rx_rss3);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt_napi_sep(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned int reg_int_val, reg_int_mask;
- unsigned long flags;
-
- //pr_info("enter ei_rx_interrupt_napi_sep\n");
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- if (likely(reg_int_val & RX_INT_ALL)) {
- if (likely(napi_schedule_prep(&ei_local->napi_rx))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RX_INT_ALL);
-
- /* Disable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask & ~(RX_INT_ALL));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi_rx);
- }
- } else {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Ack other interrupt status except TX irqs */
- reg_int_val &= ~(TX_INT_ALL);
- sys_reg_write(ei_local->fe_rx_int_status, reg_int_val);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
-
- //pr_info("leave ei_rx_interrupt_napi_sep\n");
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_rx_interrupt(int irq, void *dev_id)
-{
- unsigned long reg_int_val;
- unsigned long reg_int_mask;
- unsigned int recv = 0;
- unsigned long flags;
-
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- reg_int_val = sys_reg_read(ei_local->fe_rx_int_status);
- if (reg_int_val & RX_INT_ALL)
- recv = 1;
-
- /* Clear RX interrupt status */
- sys_reg_write(ei_local->fe_rx_int_status, RX_INT_ALL);
-
- if (likely(((recv == 1) || (pending_recv == 1)) &&
- (ei_local->tx_ring_full == 0))) {
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- /* Disable RX interrupt */
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask & ~(RX_INT_ALL));
- pending_recv = 0;
-
- if (likely(ei_local->features & FE_INT_TASKLET))
- tasklet_hi_schedule(&ei_local->rx_tasklet);
- else
- schedule_work(&ei_local->rx_wq);
- } else if (recv == 1 && ei_local->tx_ring_full == 1) {
- pending_recv = 1;
- }
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_tx_interrupt_napi(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned long flags;
- unsigned int reg_int_val;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_tx_int_status);
- if (likely(reg_int_val & TX_INT_ALL)) {
- if (likely(napi_schedule_prep(&ei_local->napi))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable TX interrupt */
- sys_reg_write(ei_local->fe_tx_int_enable, 0);
- /* Disable RX interrupt */
- sys_reg_write(ei_local->fe_rx_int_enable, 0);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi);
- }
- } else {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Ack other interrupt status except RX irqs */
- reg_int_val &= ~(RX_INT_ALL);
- sys_reg_write(ei_local->fe_tx_int_status, reg_int_val);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_tx_interrupt_napi_sep(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned long flags;
- unsigned int reg_int_val, reg_int_mask;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- reg_int_val = sys_reg_read(ei_local->fe_tx_int_status);
- if (likely(reg_int_val & TX_INT_ALL)) {
- if (likely(napi_schedule_prep(&ei_local->napi_tx))) {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Disable TX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask & ~(TX_INT_ALL));
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- __napi_schedule(&ei_local->napi_tx);
- }
- } else {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* Ack other interrupt status except RX irqs */
- reg_int_val &= ~(RX_INT_ALL);
- sys_reg_write(ei_local->fe_tx_int_status, reg_int_val);
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t ei_tx_interrupt(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned long flags;
- unsigned long reg_int_val, reg_int_mask;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- reg_int_val = sys_reg_read(ei_local->fe_tx_int_status);
-
- if (likely(reg_int_val & TX_INT_ALL)) {
- /* Disable TX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask & ~(TX_INT_ALL));
- /* Clear TX interrupt status */
- sys_reg_write(ei_local->fe_tx_int_status, TX_INT_ALL);
- ei_local->ei_xmit_housekeeping(netdev, num_tx_max_process);
-
- /* Enable TX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_tx_int_enable);
- sys_reg_write(ei_local->fe_tx_int_enable,
- reg_int_mask | ei_local->tx_mask);
- }
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-#if 0
-static irqreturn_t ei_fe_interrupt(int irq, void *dev_id)
-{
- struct net_device *netdev = (struct net_device *)dev_id;
- struct END_DEVICE *ei_local;
- unsigned long flags;
- unsigned int reg_val;
- unsigned int speed_mode;
-
- if (unlikely(!netdev)) {
- pr_info("net_interrupt(): irq %x for unknown device.\n", irq);
- return IRQ_NONE;
- }
- ei_local = netdev_priv(netdev);
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- /* not to apply SGMII FC ECO for 100/10 */
- if (ei_local->architecture & GE1_SGMII_AN) {
- /* disable fe int */
- sys_reg_write(FE_INT_ENABLE2, 0);
- sys_reg_write(FE_INT_STATUS2, MAC1_LINK);
- reg_val = sys_reg_read(ethdma_mac_base + 0x108);
- if (reg_val & 0x1) {
- speed_mode = (reg_val & 0x8) >> 3;
- /* speed_mode: 0 for 100/10; 1 for else */
- reg_val = sys_reg_read(ethdma_mac_base + 0x8);
- if (speed_mode == 0)
- reg_val |= 1 << 7;
- else if (speed_mode == 1)
- reg_val &= ~(1 << 7);
- sys_reg_write(ethdma_mac_base + 0x8, reg_val);
- }
- sys_reg_write(FE_INT_ENABLE2, MAC1_LINK);
- } else if (ei_local->architecture & GE2_SGMII_AN) {
- /* disable fe int */
- sys_reg_write(FE_INT_ENABLE2, 0);
- sys_reg_write(FE_INT_STATUS2, MAC2_LINK);
- reg_val = sys_reg_read(ethdma_mac_base + 0x208);
- if (reg_val & 0x1) {
- speed_mode = (reg_val & 0x8) >> 3;
- /* speed_mode: 0 for 100/10; 1 for else */
- reg_val = sys_reg_read(ethdma_mac_base + 0x8);
- if (speed_mode == 0)
- reg_val |= 1 << 7;
- else if (speed_mode == 1)
- reg_val &= ~(1 << 7);
- sys_reg_write(ethdma_mac_base + 0x8, reg_val);
- }
- sys_reg_write(FE_INT_ENABLE2, MAC2_LINK);
- }
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return IRQ_HANDLED;
-}
-#endif
-
-static inline void ei_receive(void)
-{
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned long reg_int_mask;
- int rx_processed;
- unsigned long flags;
-
- if (ei_local->tx_ring_full == 0) {
- rx_processed = ei_local->ei_eth_recv(dev, NULL,
- NUM_RX_MAX_PROCESS);
- if (rx_processed > NUM_RX_MAX_PROCESS) {
- if (likely(ei_local->features & FE_INT_TASKLET))
- tasklet_hi_schedule(&ei_local->rx_tasklet);
- else
- schedule_work(&ei_local->rx_wq);
- } else {
- spin_lock_irqsave(&ei_local->irq_lock, flags);
- /* Enable RX interrupt */
- reg_int_mask = sys_reg_read(ei_local->fe_rx_int_enable);
- sys_reg_write(ei_local->fe_rx_int_enable,
- reg_int_mask | ei_local->rx_mask);
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
- }
- } else {
- if (likely(ei_local->features & FE_INT_TASKLET))
- tasklet_schedule(&ei_local->rx_tasklet);
- else
- schedule_work(&ei_local->rx_wq);
- }
-}
-
-static void ei_receive_tasklet(unsigned long unused)
-{
- ei_receive();
-}
-
-static void ei_receive_workq(struct work_struct *work)
-{
- ei_receive();
-}
-
-static int fe_int_enable(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- //struct device_node *np = ei_local->switch_np;
- //struct platform_device *pdev = of_find_device_by_node(np);
- int err0 = 0, err1 = 0, err2 = 0, err3 = 0;
- //struct mtk_gsw *gsw;
- unsigned int reg_val = 0;
- unsigned long flags;
-
- pr_err("fe_int_enable\n");
- if (ei_local->architecture & (GE1_SGMII_AN | GE2_SGMII_AN)) {
- //err0 = request_irq(ei_local->irq0, ei_fe_interrupt,
- // IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, dev->name, dev);
- } else if (ei_local->features & FE_INT_NAPI) {
- if (ei_local->features & FE_INT_NAPI_TX_RX)
- err0 =
- request_irq(ei_local->irq0, ei_interrupt_napi_sep,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, dev->name, dev);
- } else
- err0 =
- request_irq(ei_local->irq0, ei_interrupt, IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- dev->name, dev);
-
- if (ei_local->features & FE_IRQ_SEPARATE) {
- if (ei_local->features & FE_INT_NAPI) {
- pr_err("FE_INT_NAPI\n");
- if (ei_local->features & FE_INT_NAPI_TX_RX) {
- pr_err("FE_INT_NAPI_TX_RX\n");
- err1 =
- request_irq(ei_local->irq1,
- ei_tx_interrupt_napi_sep,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_tx", dev);
- err2 =
- request_irq(ei_local->irq2,
- ei_rx_interrupt_napi_sep,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx", dev);
- } else if (ei_local->features & FE_INT_NAPI_RX_ONLY) {
- pr_err("FE_INT_NAPI_RX_ONLY\n");
-
-
- if (ei_local->features & FE_RSS_4RING) {
- err2 =
- request_irq(ei_local->irq2,
- ei_rx_interrupt_napi_g0,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx_g0", dev);
- err3 =
- request_irq(ei_local->irq3,
- ei_rx_interrupt_napi_g1,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx_g1", dev);
- } else if (ei_local->features & FE_RSS_2RING) {
- err2 =
- request_irq(ei_local->irq2,
- ei_rx_interrupt_napi_rss0,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx_0", dev);
- err3 =
- request_irq(ei_local->irq3,
- ei_rx_interrupt_napi_rss1,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx_1", dev);
- }
- } else {
- pr_err("else\n");
- err1 =
- request_irq(ei_local->irq1,
- ei_tx_interrupt_napi,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_tx", dev);
- err2 =
- request_irq(ei_local->irq2,
- ei_rx_interrupt_napi,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
- "eth_rx", dev);
- }
- } else {
- pr_err("not FE_INT_NAPI\n");
- err1 =
- request_irq(ei_local->irq1, ei_tx_interrupt,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, "eth_tx", dev);
- err2 =
- request_irq(ei_local->irq2, ei_rx_interrupt,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, "eth_rx", dev);
- }
- }
- pr_info("!!!!!! request done\n");
-
-
-
- spin_lock_irqsave(&ei_local->irq_lock, flags);
-
- if (ei_local->features & FE_DLY_INT) {
- ei_local->tx_mask = RLS_DLY_INT;
-
- if (ei_local->features & FE_RSS_4RING)
- ei_local->rx_mask = RSS_RX_DLY_INT;
- else if (ei_local->features & FE_RSS_2RING)
- ei_local->rx_mask = RSS_RX_DLY_INT0;
- else
- ei_local->rx_mask = RX_DLY_INT;
- } else {
- ei_local->tx_mask = TX_DONE_INT0;
- ei_local->rx_mask = RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3;
- }
-
- /* Enable PDMA interrupts */
- if (ei_local->features & FE_DLY_INT) {
- sys_reg_write(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
- if (ei_local->features & FE_RSS_4RING) {
- sys_reg_write(LRO_RX1_DLY_INT, DELAY_INT_INIT);
- sys_reg_write(LRO_RX2_DLY_INT, DELAY_INT_INIT);
- sys_reg_write(LRO_RX3_DLY_INT, DELAY_INT_INIT);
- sys_reg_write(RAETH_FE_INT_ENABLE, RSS_INT_DLY_INT);
- } else if (ei_local->features & FE_RSS_2RING) {
- sys_reg_write(LRO_RX1_DLY_INT, DELAY_INT_INIT);
- sys_reg_write(RAETH_FE_INT_ENABLE, RSS_INT_DLY_INT_2RING);
- } else {
- sys_reg_write(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
- }
- } else {
- sys_reg_write(RAETH_FE_INT_ENABLE, RAETH_FE_INT_ALL);
- }
-
- /* Enable QDMA interrupts */
- if (ei_local->features & FE_QDMA) {
- if (ei_local->features & FE_DLY_INT) {
- sys_reg_write(QDMA_DELAY_INT, DELAY_INT_INIT);
- sys_reg_write(QFE_INT_ENABLE, QFE_INT_DLY_INIT);
- } else {
- sys_reg_write(QFE_INT_ENABLE, QFE_INT_ALL);
- }
- }
-
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- if (ei_local->architecture & GE1_SGMII_AN)
- sys_reg_write(FE_INT_ENABLE2, MAC1_LINK);
- else if (ei_local->architecture & GE2_SGMII_AN)
- sys_reg_write(FE_INT_ENABLE2, MAC2_LINK);
- }
-
- /* IRQ separation settings */
- if (ei_local->features & FE_IRQ_SEPARATE) {
- if (ei_local->features & FE_DLY_INT) {
- /* PDMA setting */
- sys_reg_write(PDMA_INT_GRP1, TX_DLY_INT);
-
- if (ei_local->features & FE_RSS_4RING) {
- /* Enable multipe rx ring delay interrupt */
- reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0);
- reg_val |= PDMA_LRO_DLY_INT_EN;
- sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val);
- sys_reg_write(PDMA_INT_GRP2, (RING0_RX_DLY_INT | RING1_RX_DLY_INT));
- sys_reg_write(PDMA_INT_GRP3, (RING2_RX_DLY_INT | RING3_RX_DLY_INT));
-
- } else if (ei_local->features & FE_RSS_2RING) {
- reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0);
- reg_val |= PDMA_LRO_DLY_INT_EN;
- sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val);
- sys_reg_write(PDMA_INT_GRP2, RING0_RX_DLY_INT);
- sys_reg_write(PDMA_INT_GRP3, RING1_RX_DLY_INT);
- } else {
- sys_reg_write(PDMA_INT_GRP2, RX_DLY_INT);
- }
- /* QDMA setting */
- sys_reg_write(QDMA_INT_GRP1, RLS_DLY_INT);
- sys_reg_write(QDMA_INT_GRP2, RX_DLY_INT);
- } else {
- /* PDMA setting */
- sys_reg_write(PDMA_INT_GRP1, TX_DONE_INT0);
-
- /* QDMA setting */
- sys_reg_write(QDMA_INT_GRP1, RLS_DONE_INT);
- sys_reg_write(QDMA_INT_GRP2, RX_DONE_INT0 | RX_DONE_INT1);
-
- if (ei_local->features & FE_RSS_4RING) {
- sys_reg_write(PDMA_INT_GRP2, (RX_DONE_INT0 | RX_DONE_INT1));
- sys_reg_write(PDMA_INT_GRP3, (RX_DONE_INT2 | RX_DONE_INT3));
- } else if (ei_local->features & FE_RSS_2RING) {
- sys_reg_write(PDMA_INT_GRP2, RX_DONE_INT0);
- sys_reg_write(PDMA_INT_GRP3, RX_DONE_INT1);
- } else {
- sys_reg_write(PDMA_INT_GRP2, RX_DONE_INT0 | RX_DONE_INT1 |
- RX_DONE_INT2 | RX_DONE_INT3);
- }
- }
- /*leopard fe_int[0~3][223,224,225,219]*/
- if (ei_local->features & (FE_RSS_4RING | FE_RSS_2RING))
- sys_reg_write(FE_INT_GRP, 0x21021030);
- else
- sys_reg_write(FE_INT_GRP, 0x21021000);
- }
-
- if (ei_local->features & FE_INT_TASKLET) {
- tasklet_init(&ei_local->rx_tasklet, ei_receive_tasklet, 0);
- } else if (ei_local->features & FE_INT_WORKQ) {
- INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
- } else {
- if (ei_local->features & FE_INT_NAPI_TX_RX) {
- napi_enable(&ei_local->napi_tx);
- napi_enable(&ei_local->napi_rx);
- } else if (ei_local->features & FE_INT_NAPI_RX_ONLY) {
- if (ei_local->features & FE_RSS_4RING) {
- napi_enable(&ei_local->napi_rx_rss0);
- napi_enable(&ei_local->napi_rx_rss1);
- napi_enable(&ei_local->napi_rx_rss2);
- napi_enable(&ei_local->napi_rx_rss3);
- } else if (ei_local->features & FE_RSS_2RING) {
- napi_enable(&ei_local->napi_rx_rss0);
- napi_enable(&ei_local->napi_rx_rss1);
- } else {
- napi_enable(&ei_local->napi_rx);
- }
- } else {
- napi_enable(&ei_local->napi);
- }
- }
-
- spin_unlock_irqrestore(&ei_local->irq_lock, flags);
-
- return 0;
-}
-
-static int fe_int_disable(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- /*always request irq0*/
- free_irq(ei_local->irq0, dev);
-
- if (ei_local->features & FE_IRQ_SEPARATE) {
- free_irq(ei_local->irq1, dev);
- free_irq(ei_local->irq2, dev);
- }
-
- if (ei_local->architecture & RAETH_ESW)
- free_irq(ei_local->esw_irq, dev);
-
- if (ei_local->features & (FE_RSS_4RING | FE_RSS_2RING))
- free_irq(ei_local->irq3, dev);
-
- cancel_work_sync(&ei_local->reset_task);
-
- if (ei_local->features & FE_INT_WORKQ)
- cancel_work_sync(&ei_local->rx_wq);
- else if (ei_local->features & FE_INT_TASKLET)
- tasklet_kill(&ei_local->rx_tasklet);
-
- if (ei_local->features & FE_INT_NAPI) {
- if (ei_local->features & FE_INT_NAPI_TX_RX) {
- napi_disable(&ei_local->napi_tx);
- napi_disable(&ei_local->napi_rx);
- } else if (ei_local->features & FE_INT_NAPI_RX_ONLY) {
- if (ei_local->features & FE_RSS_4RING) {
- napi_disable(&ei_local->napi_rx_rss0);
- napi_disable(&ei_local->napi_rx_rss1);
- napi_disable(&ei_local->napi_rx_rss2);
- napi_disable(&ei_local->napi_rx_rss3);
- } else if (ei_local->features & FE_RSS_2RING) {
- napi_disable(&ei_local->napi_rx_rss0);
- napi_disable(&ei_local->napi_rx_rss1);
- } else {
- napi_disable(&ei_local->napi_rx);
- }
- } else {
- napi_disable(&ei_local->napi);
- }
- }
-
- return 0;
-}
-
-int forward_config(struct net_device *dev)
-{
- unsigned int reg_val, reg_csg;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int reg_val2 = 0;
-
- if (ei_local->features & FE_HW_VLAN_TX) {
- /*VLAN_IDX 0 = VLAN_ID 0
- * .........
- * VLAN_IDX 15 = VLAN ID 15
- *
- */
- /* frame engine will push VLAN tag
- * regarding to VIDX feild in Tx desc.
- */
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xa8, 0x00010000);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xac, 0x00030002);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xb0, 0x00050004);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xb4, 0x00070006);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xb8, 0x00090008);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xbc, 0x000b000a);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xc0, 0x000d000c);
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + 0xc4, 0x000f000e);
- }
-
- reg_val = sys_reg_read(GDMA1_FWD_CFG);
- reg_csg = sys_reg_read(CDMA_CSG_CFG);
-
- if (ei_local->features & FE_GE2_SUPPORT)
- reg_val2 = sys_reg_read(GDMA2_FWD_CFG);
-
- /* set unicast/multicast/broadcast frame to cpu */
- reg_val &= ~0xFFFF;
- reg_val |= GDMA1_FWD_PORT;
- reg_csg &= ~0x7;
-
- if (ei_local->features & FE_HW_VLAN_TX)
- dev->features |= NETIF_F_HW_VLAN_CTAG_TX;
-
- if (ei_local->features & FE_HW_VLAN_RX) {
- dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
- /* enable HW VLAN RX */
- sys_reg_write(CDMP_EG_CTRL, 1);
- }
- if (ei_local->features & FE_CSUM_OFFLOAD) {
- /* enable ipv4 header checksum check */
- reg_val |= GDM1_ICS_EN;
- reg_csg |= ICS_GEN_EN;
-
- /* enable tcp checksum check */
- reg_val |= GDM1_TCS_EN;
- reg_csg |= TCS_GEN_EN;
-
- /* enable udp checksum check */
- reg_val |= GDM1_UCS_EN;
- reg_csg |= UCS_GEN_EN;
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- reg_val2 &= ~0xFFFF;
- reg_val2 |= GDMA2_FWD_PORT;
- reg_val2 |= GDM1_ICS_EN;
- reg_val2 |= GDM1_TCS_EN;
- reg_val2 |= GDM1_UCS_EN;
- }
-
- if (ei_local->features & FE_HW_LRO)
- dev->features |= NETIF_F_HW_CSUM;
- else
- /* Can checksum TCP/UDP over IPv4 */
- dev->features |= NETIF_F_IP_CSUM;
-
- if (ei_local->features & FE_TSO) {
- dev->features |= NETIF_F_SG;
- dev->features |= NETIF_F_TSO;
- }
-
- if (ei_local->features & FE_TSO_V6) {
- dev->features |= NETIF_F_TSO6;
- /* Can checksum TCP/UDP over IPv6 */
- dev->features |= NETIF_F_IPV6_CSUM;
- }
- } else { /* Checksum offload disabled */
- /* disable ipv4 header checksum check */
- reg_val &= ~GDM1_ICS_EN;
- reg_csg &= ~ICS_GEN_EN;
-
- /* disable tcp checksum check */
- reg_val &= ~GDM1_TCS_EN;
- reg_csg &= ~TCS_GEN_EN;
-
- /* disable udp checksum check */
- reg_val &= ~GDM1_UCS_EN;
- reg_csg &= ~UCS_GEN_EN;
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- reg_val2 &= ~GDM1_ICS_EN;
- reg_val2 &= ~GDM1_TCS_EN;
- reg_val2 &= ~GDM1_UCS_EN;
- }
-
- /* disable checksum TCP/UDP over IPv4 */
- dev->features &= ~NETIF_F_IP_CSUM;
- }
-
- sys_reg_write(GDMA1_FWD_CFG, reg_val);
- sys_reg_write(CDMA_CSG_CFG, reg_csg);
- if (ei_local->features & FE_GE2_SUPPORT)
- sys_reg_write(GDMA2_FWD_CFG, reg_val2);
-
- dev->vlan_features = dev->features;
-
- /*FE_RST_GLO register definition -
- *Bit 0: PSE Rest
- *Reset PSE after re-programming PSE_FQ_CFG.
- */
- reg_val = 0x1;
- sys_reg_write(FE_RST_GL, reg_val);
- sys_reg_write(FE_RST_GL, 0); /* update for RSTCTL issue */
-
- reg_csg = sys_reg_read(CDMA_CSG_CFG);
- reg_val = sys_reg_read(GDMA1_FWD_CFG);
-
- if (ei_local->features & FE_GE2_SUPPORT)
- reg_val = sys_reg_read(GDMA2_FWD_CFG);
-
- return 1;
-}
-
-void virtif_setup_statistics(struct PSEUDO_ADAPTER *p_ad)
-{
- p_ad->stat.tx_packets = 0;
- p_ad->stat.tx_bytes = 0;
- p_ad->stat.tx_dropped = 0;
- p_ad->stat.tx_errors = 0;
- p_ad->stat.tx_aborted_errors = 0;
- p_ad->stat.tx_carrier_errors = 0;
- p_ad->stat.tx_fifo_errors = 0;
- p_ad->stat.tx_heartbeat_errors = 0;
- p_ad->stat.tx_window_errors = 0;
-
- p_ad->stat.rx_packets = 0;
- p_ad->stat.rx_bytes = 0;
- p_ad->stat.rx_dropped = 0;
- p_ad->stat.rx_errors = 0;
- p_ad->stat.rx_length_errors = 0;
- p_ad->stat.rx_over_errors = 0;
- p_ad->stat.rx_crc_errors = 0;
- p_ad->stat.rx_frame_errors = 0;
- p_ad->stat.rx_fifo_errors = 0;
- p_ad->stat.rx_missed_errors = 0;
-
- p_ad->stat.collisions = 0;
-}
-
-int virtualif_open(struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev);
- struct END_DEVICE *ei_local = netdev_priv(p_pseudo_ad->raeth_dev);
-
-
- virtif_setup_statistics(p_pseudo_ad);
-
- if (ei_local->features & FE_HW_VLAN_TX)
- dev->features |= NETIF_F_HW_VLAN_CTAG_TX;
-
- if (ei_local->features & FE_HW_VLAN_RX)
- dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
-
- netif_start_queue(p_pseudo_ad->pseudo_dev);
-
- return 0;
-}
-
-int virtualif_close(struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev);
-
- pr_info("%s: ===> virtualif_close\n", dev->name);
-
- netif_stop_queue(p_pseudo_ad->pseudo_dev);
-
- return 0;
-}
-
-int virtualif_send_packets(struct sk_buff *p_skb, struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *p_pseudo_ad = netdev_priv(dev);
- struct END_DEVICE *ei_local;
-
- if (!(p_pseudo_ad->raeth_dev->flags & IFF_UP)) {
- dev_kfree_skb_any(p_skb);
- return 0;
- }
- /* p_skb->cb[40]=0x5a; */
- p_skb->dev = p_pseudo_ad->pseudo_dev;
- ei_local = netdev_priv(p_pseudo_ad->raeth_dev);
- ei_local->ei_start_xmit(p_skb, p_pseudo_ad->raeth_dev, 2);
- return 0;
-}
-
-struct net_device_stats *virtualif_get_stats(struct net_device *dev)
-{
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(dev);
-
- return &p_ad->stat;
-}
-
-int virtualif_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
-{
- struct ra_mii_ioctl_data mii;
- unsigned long ret;
-
- switch (cmd) {
- case RAETH_MII_READ:
- ret = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
- ret = copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
- break;
-
- case RAETH_MII_WRITE:
- ret = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
- break;
- default:
- return -EOPNOTSUPP;
- }
-
- return 0;
-}
-
-static int ei_change_mtu(struct net_device *dev, int new_mtu)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- if (!ei_local) {
- pr_emerg
- ("%s: %s passed a non-existent private pointer from net_dev!\n",
- dev->name, __func__);
- return -ENXIO;
- }
-
- if ((new_mtu > 4096) || (new_mtu < 64))
- return -EINVAL;
-
- if (new_mtu > 1500)
- return -EINVAL;
-
- dev->mtu = new_mtu;
-
- return 0;
-}
-#if 0
-static int ei_clock_enable(struct END_DEVICE *ei_local)
-{
- unsigned long rate;
- int ret;
- void __iomem *clk_virt_base;
- unsigned int reg_value;
-
- pm_runtime_enable(ei_local->dev);
- pm_runtime_get_sync(ei_local->dev);
-
- clk_prepare_enable(ei_local->clks[MTK_CLK_ETH1PLL]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_ETH2PLL]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_ETHIF]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_ESW]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_GP1]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_GP2]);
- /*enable frame engine clock*/
- if (ei_local->chip_name == LEOPARD_FE)
- clk_prepare_enable(ei_local->clks[MTK_CLK_FE]);
-
- if (ei_local->architecture & RAETH_ESW)
- clk_prepare_enable(ei_local->clks[MTK_CLK_GP0]);
-
- if (ei_local->architecture &
- (GE1_TRGMII_FORCE_2000 | GE1_TRGMII_FORCE_2600)) {
- ret = clk_set_rate(ei_local->clks[MTK_CLK_TRGPLL], 500000000);
- if (ret)
- pr_err("Failed to set mt7530 trgmii pll: %d\n", ret);
- rate = clk_get_rate(ei_local->clks[MTK_CLK_TRGPLL]);
- pr_info("TRGMII_PLL rate = %ld\n", rate);
- clk_prepare_enable(ei_local->clks[MTK_CLK_TRGPLL]);
- }
-
- if (ei_local->architecture & RAETH_SGMII) {
- if (ei_local->chip_name == LEOPARD_FE)
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII_TOP]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMIPLL]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII_TX250M]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII_RX250M]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII_CDR_REF]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII_CDR_FB]);
- }
-
- if (ei_local->architecture & GE2_RAETH_SGMII) {
- clk_virt_base = ioremap(0x102100C0, 0x10);
- reg_value = sys_reg_read(clk_virt_base);
- reg_value = reg_value & (~0x8000); /*[bit15] = 0 */
- /*pdn_sgmii_re_1 1: Enable clock off */
- sys_reg_write(clk_virt_base, reg_value);
- iounmap(clk_virt_base);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMIPLL]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII1_TX250M]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII1_RX250M]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII1_CDR_REF]);
- clk_prepare_enable(ei_local->clks[MTK_CLK_SGMII1_CDR_FB]);
- }
-
- return 0;
-}
-#endif
-static int ei_clock_disable(struct END_DEVICE *ei_local)
-{
- if (ei_local->chip_name == LEOPARD_FE)
- clk_disable_unprepare(ei_local->clks[MTK_CLK_FE]);
- if (ei_local->architecture & RAETH_ESW)
- clk_disable_unprepare(ei_local->clks[MTK_CLK_GP0]);
-
- if (ei_local->architecture &
- (GE1_TRGMII_FORCE_2000 | GE1_TRGMII_FORCE_2600))
- clk_disable_unprepare(ei_local->clks[MTK_CLK_TRGPLL]);
-
- if (ei_local->architecture & RAETH_SGMII) {
- clk_disable_unprepare(ei_local->clks[MTK_CLK_SGMII_TX250M]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_SGMII_RX250M]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_SGMII_CDR_REF]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_SGMII_CDR_FB]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_SGMIPLL]);
- }
-
- clk_disable_unprepare(ei_local->clks[MTK_CLK_GP2]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_GP1]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_ESW]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_ETHIF]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_ETH2PLL]);
- clk_disable_unprepare(ei_local->clks[MTK_CLK_ETH1PLL]);
-
- pm_runtime_put_sync(ei_local->dev);
- pm_runtime_disable(ei_local->dev);
-
- return 0;
-}
-
-static struct ethtool_ops ra_ethtool_ops = {
- .get_link = et_get_link,
-};
-
-static struct ethtool_ops ra_virt_ethtool_ops = {
- .get_link = et_virt_get_link,
-};
-
-static const struct net_device_ops virtualif_netdev_ops = {
- .ndo_open = virtualif_open,
- .ndo_stop = virtualif_close,
- .ndo_start_xmit = virtualif_send_packets,
- .ndo_get_stats = virtualif_get_stats,
- .ndo_set_mac_address = ei_set_mac2_addr,
- .ndo_change_mtu = ei_change_mtu,
- .ndo_do_ioctl = virtualif_ioctl,
- .ndo_validate_addr = eth_validate_addr,
-};
-
-void raeth_init_pseudo(struct END_DEVICE *p_ad, struct net_device *net_dev)
-{
- int index;
- struct net_device *dev;
- struct PSEUDO_ADAPTER *p_pseudo_ad;
- struct END_DEVICE *ei_local = netdev_priv(net_dev);
-
- for (index = 0; index < MAX_PSEUDO_ENTRY; index++) {
- dev = alloc_etherdev_mqs(sizeof(struct PSEUDO_ADAPTER),
- gmac2_txq_num, 1);
- if (!dev) {
- pr_err("alloc_etherdev for PSEUDO_ADAPTER failed.\n");
- return;
- }
- strncpy(dev->name, DEV2_NAME, sizeof(dev->name) - 1);
- netif_set_real_num_tx_queues(dev, gmac2_txq_num);
- netif_set_real_num_rx_queues(dev, 1);
-
- ei_mac2_addr_setting(dev);
- /*set my mac*/
- set_mac2_address(dev->dev_addr);
- ether_setup(dev);
- p_pseudo_ad = netdev_priv(dev);
-
- p_pseudo_ad->pseudo_dev = dev;
- p_pseudo_ad->raeth_dev = net_dev;
- p_ad->pseudo_dev = dev;
-
- dev->netdev_ops = &virtualif_netdev_ops;
-
- if (ei_local->features & FE_HW_LRO)
- dev->features |= NETIF_F_HW_CSUM;
- else
- /* Can checksum TCP/UDP over IPv4 */
- dev->features |= NETIF_F_IP_CSUM;
-
- if (ei_local->features & FE_TSO) {
- dev->features |= NETIF_F_SG;
- dev->features |= NETIF_F_TSO;
- }
-
- if (ei_local->features & FE_TSO_V6) {
- dev->features |= NETIF_F_TSO6;
- /* Can checksum TCP/UDP over IPv6 */
- dev->features |= NETIF_F_IPV6_CSUM;
- }
-
- dev->vlan_features = dev->features;
-
- if (ei_local->features & FE_ETHTOOL) {
- dev->ethtool_ops = &ra_virt_ethtool_ops;
- ethtool_virt_init(dev);
- }
-
- /* Register this device */
- register_netdev(dev);
- }
-}
-
-
-/* PHY Indirect Access Control registers */
-#define MTK_PHY_IAC 0x10004
-#define PHY_IAC_ACCESS BIT(31)
-#define PHY_IAC_READ BIT(19)
-#define PHY_IAC_WRITE BIT(18)
-#define PHY_IAC_START BIT(16)
-#define PHY_IAC_ADDR_SHIFT 20
-#define PHY_IAC_REG_SHIFT 25
-#define PHY_IAC_TIMEOUT HZ
-#define dummy 1
-
-static int mtk_mdio_busy_wait(struct platform_device *pdev)
-{
- unsigned long t_start = jiffies;
-
- while (1) {
- if (!(sys_reg_read(RALINK_FRAME_ENGINE_BASE + MTK_PHY_IAC) & PHY_IAC_ACCESS))
- return 0;
- if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
- break;
- usleep_range(10, 20);
- }
-
- dev_err(&pdev->dev, "mdio: MDIO timeout\n");
- return -1;
-}
-
-static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, int phy_register, u16 write_data)
-{
- struct platform_device *pdev = (struct platform_device *)bus->priv;
- if (mtk_mdio_busy_wait(pdev))
- return -1;
-
-/*
- dev_info(&pdev->dev, "[%s] phy_addr=0x%08x, phy_reg=0x%08x, data=0x%08x!",
- __func__, phy_addr, phy_register, write_data);
-*/
- write_data &= 0xffff;
-
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + MTK_PHY_IAC,
- (PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
- (phy_register << PHY_IAC_REG_SHIFT) |
- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data));
-
- if (mtk_mdio_busy_wait(pdev))
- return -1;
-
- return 0;
-}
-
-static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
-{
- u32 d;
- struct platform_device *pdev = (struct platform_device *)bus->priv;
-/*
- dev_info(&pdev->dev, "[%s] phy_addr=0x%08x, phy_reg=0x%08x!",
- __func__, phy_addr, phy_reg);
- */
-
- if (mtk_mdio_busy_wait(pdev))
- return 0xffff;
-
- sys_reg_write(RALINK_FRAME_ENGINE_BASE + MTK_PHY_IAC,
- (PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
- (phy_reg << PHY_IAC_REG_SHIFT) |
- (phy_addr << PHY_IAC_ADDR_SHIFT)));
-
- if (mtk_mdio_busy_wait(pdev))
- return 0xffff;
-
- d = sys_reg_read(RALINK_FRAME_ENGINE_BASE + MTK_PHY_IAC) & 0xffff;
-
-/*
- dev_info(&pdev->dev, "[%s] phy_addr=0x%08x, phy_reg=0x%08x, val=0x%08x!",
- __func__, phy_addr, phy_reg, d);
-*/
- return d;
-}
-
-static int mtk_mdio_init(struct platform_device *pdev)
-{
- struct device_node *mii_np;
- struct mii_bus *mii_bus;
- int ret;
-
- dev_info(&pdev->dev, "[%s] in!", __func__);
-
- mii_np = of_get_child_by_name(pdev->dev.of_node, "mdio-bus");
- if (!mii_np) {
- dev_err(&pdev->dev, "no %s child node found", "mdio-bus");
- return -ENODEV;
- }
-
- if (!of_device_is_available(mii_np)) {
- ret = -ENODEV;
- goto err_put_node;
- }
-
- mii_bus = devm_mdiobus_alloc(&pdev->dev);
- if (!mii_bus) {
- ret = -ENOMEM;
- goto err_put_node;
- }
-
- mii_bus->name = "mdio";
- mii_bus->read = mtk_mdio_read;
- mii_bus->write = mtk_mdio_write;
- mii_bus->priv = pdev;
- mii_bus->parent = &pdev->dev;
-
- pr_info("mtk_mdio_init %s\n", mii_np->name);
-
- snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
- ret = of_mdiobus_register(mii_bus, mii_np);
-
- dev_info(&pdev->dev, "[%s] done!", __func__);
-
-err_put_node:
- of_node_put(mii_np);
- return ret;
-}
-
-void ei_set_pse_threshold(void)
-{
-
- sys_reg_write(PSE_IQ_REV1, 0x001a000e);
- sys_reg_write(PSE_IQ_REV2, 0x01ff001a);
- sys_reg_write(PSE_IQ_REV3, 0x000e01ff);
- sys_reg_write(PSE_IQ_REV4, 0x000e000e);
- sys_reg_write(PSE_IQ_REV5, 0x000e000e);
- sys_reg_write(PSE_IQ_REV6, 0x000e000e);
- sys_reg_write(PSE_IQ_REV7, 0x000e000e);
- sys_reg_write(PSE_IQ_REV8, 0x000e000e);
- sys_reg_write(PSE_OQ_TH1, 0x000f000a);
- sys_reg_write(PSE_OQ_TH2, 0x001a000f);
- sys_reg_write(PSE_OQ_TH3, 0x000f001a);
- sys_reg_write(PSE_OQ_TH4, 0x01ff000f);
- sys_reg_write(PSE_OQ_TH5, 0x000f000f);
- sys_reg_write(PSE_OQ_TH6, 0x0006000f);
- sys_reg_write(PSE_OQ_TH7, 0x00060006);
- sys_reg_write(PSE_OQ_TH8, 0x00060006);
-}
-
-int ei_open(struct net_device *dev)
-{
- int err;
- struct END_DEVICE *ei_local;
-
-
- ei_local = netdev_priv(dev);
-
- if (!ei_local) {
- pr_err("%s: ei_open passed a non-existent device!\n",
- dev->name);
- return -ENXIO;
- }
-
- if (!try_module_get(THIS_MODULE)) {
- pr_err("%s: Cannot reserve module\n", __func__);
- return -1;
- }
-
- pr_info("Raeth %s (", RAETH_VERSION);
- if (ei_local->features & FE_INT_NAPI)
- pr_info("NAPI\n");
- else if (ei_local->features & FE_INT_TASKLET)
- pr_info("Tasklet");
- else if (ei_local->features & FE_INT_WORKQ)
- pr_info("Workqueue");
- pr_info(")\n");
-
- ei_reset_statistics(ei_local);
-
- ei_set_pse_threshold();
-
- err = ei_init_dma(dev);
- if (err)
- return err;
-
- if (ei_local->chip_name != MT7621_FE) {
- fe_gmac_reset();
- fe_sw_init();
- }
-
- /* initialize fe and switch register */
- if (ei_local->chip_name != LEOPARD_FE)
- fe_sw_preinit(ei_local);
-
-
- forward_config(dev);
-
- if ((ei_local->chip_name == MT7623_FE) &&
- (ei_local->features & FE_HW_LRO)) {
- ei_local->kreset_task =
- kthread_create(fe_reset_thread, NULL, "FE_reset_kthread");
- if (IS_ERR(ei_local->kreset_task))
- return PTR_ERR(ei_local->kreset_task);
- wake_up_process(ei_local->kreset_task);
- }
-
- netif_start_queue(dev);
-
- fe_int_enable(dev);
-
- /*set hw my mac address*/
- set_mac_address(dev->dev_addr);
- if (ei_local->chip_name == LEOPARD_FE) {
- /*phy led enable*/
- mii_mgr_write_cl45(0, 0x1f, 0x21, 0x8008);
- mii_mgr_write_cl45(0, 0x1f, 0x24, 0x8007);
- mii_mgr_write_cl45(0, 0x1f, 0x25, 0x3f);
- if ((ei_local->architecture & GE2_RGMII_AN)) {
- mii_mgr_write(0, 9, 0x200);
- mii_mgr_write(0, 0, 0x1340);
- if (mac_to_gigaphy_mode_addr2 == 0) {
- ei_local->kphy_poll_task =
- kthread_create(phy_polling_thread, NULL, "phy_polling_kthread");
- if (IS_ERR(ei_local->kphy_poll_task))
- return PTR_ERR(ei_local->kphy_poll_task);
- wake_up_process(ei_local->kphy_poll_task);
- }
- } else if (ei_local->architecture & LEOPARD_EPHY_GMII) {
- mii_mgr_write(0, 9, 0x200);
- mii_mgr_write(0, 0, 0x1340);
- }
- }
- return 0;
-}
-
-int ei_close(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- fe_reset();
-
- if ((ei_local->chip_name == MT7623_FE) &&
- (ei_local->features & FE_HW_LRO))
- kthread_stop(ei_local->kreset_task);
-
- if (ei_local->chip_name == LEOPARD_FE) {
- if (ei_local->architecture & GE2_RGMII_AN)
- kthread_stop(ei_local->kphy_poll_task);
- }
-
- netif_stop_queue(dev);
- ra2880stop(ei_local);
-
- fe_int_disable(dev);
-
- if (ei_local->features & FE_GE2_SUPPORT)
- virtualif_close(ei_local->pseudo_dev);
-
- ei_deinit_dma(dev);
-
- if (ei_local->chip_name != LEOPARD_FE)
- fe_sw_deinit(ei_local);
-
- module_put(THIS_MODULE);
-
- return 0;
-}
-
-static int ei_start_xmit_fake(struct sk_buff *skb, struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- return ei_local->ei_start_xmit(skb, dev, 1);
-}
-
-struct net_device_stats *ra_get_stats(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- return &ei_local->stat;
-}
-
-void dump_phy_reg(int port_no, int from, int to, int is_local, int page_no)
-{
- u32 i = 0;
- u32 temp = 0;
- u32 r31 = 0;
-
- if (is_local == 0) {
- pr_info("\n\nGlobal Register Page %d\n", page_no);
- pr_info("===============");
- r31 |= 0 << 15; /* global */
- r31 |= ((page_no & 0x7) << 12); /* page no */
- mii_mgr_write(port_no, 31, r31); /* select global page x */
- for (i = 16; i < 32; i++) {
- if (i % 8 == 0)
- pr_info("\n");
- mii_mgr_read(port_no, i, &temp);
- pr_info("%02d: %04X ", i, temp);
- }
- } else {
- pr_info("\n\nLocal Register Port %d Page %d\n", port_no,
- page_no);
- pr_info("===============");
- r31 |= 1 << 15; /* local */
- r31 |= ((page_no & 0x7) << 12); /* page no */
- mii_mgr_write(port_no, 31, r31); /* select local page x */
- for (i = 16; i < 32; i++) {
- if (i % 8 == 0)
- pr_info("\n");
- mii_mgr_read(port_no, i, &temp);
- pr_info("%02d: %04X ", i, temp);
- }
- }
- pr_info("\n");
-}
-
-int ei_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
-{
- struct esw_reg reg;
- struct esw_rate ratelimit;
- struct qdma_ioctl_data qdma_data;
- struct ephy_ioctl_data ephy_data;
-
- unsigned int offset = 0;
- unsigned int value = 0;
- int ret = 0;
- unsigned long result;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct ra_mii_ioctl_data mii;
- char ip_tmp[IP4_ADDR_LEN];
-
- spin_lock_irq(&ei_local->page_lock);
-
- switch (cmd) {
- case RAETH_MII_READ:
- result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
- result = copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
- break;
-
- case RAETH_MII_WRITE:
- result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
- break;
- case RAETH_MII_READ_CL45:
- result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_read_cl45(mii.port_num, mii.dev_addr, mii.reg_addr,
- &mii.val_out);
- result = copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
- break;
- case RAETH_MII_WRITE_CL45:
- result = copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
- mii_mgr_write_cl45(mii.port_num, mii.dev_addr, mii.reg_addr,
- mii.val_in);
- break;
- case RAETH_ESW_REG_READ:
- result = copy_from_user(®, ifr->ifr_data, sizeof(reg));
- if (reg.off > REG_ESW_MAX) {
- ret = -EINVAL;
- break;
- }
- reg.val = sys_reg_read(RALINK_ETH_SW_BASE + reg.off);
- result = copy_to_user(ifr->ifr_data, ®, sizeof(reg));
- break;
- case RAETH_ESW_REG_WRITE:
- result = copy_from_user(®, ifr->ifr_data, sizeof(reg));
- if (reg.off > REG_ESW_MAX) {
- ret = -EINVAL;
- break;
- }
- sys_reg_write(RALINK_ETH_SW_BASE + reg.off, reg.val);
- break;
- case RAETH_ESW_PHY_DUMP:
- result = copy_from_user(®, ifr->ifr_data, sizeof(reg));
- /* SPEC defined Register 0~15
- * Global Register 16~31 for each page
- * Local Register 16~31 for each page
- */
- pr_info("SPEC defined Register");
- if (reg.val == 32) { /* dump all phy register */
- int i = 0;
-
- for (i = 0; i < 5; i++) {
- pr_info("\n[Port %d]===============", i);
- for (offset = 0; offset < 16; offset++) {
- if (offset % 8 == 0)
- pr_info("\n");
- mii_mgr_read(i, offset, &value);
- pr_info("%02d: %04X ", offset, value);
- }
- }
- } else {
- pr_info("\n[Port %d]===============", reg.val);
- for (offset = 0; offset < 16; offset++) {
- if (offset % 8 == 0)
- pr_info("\n");
- mii_mgr_read(reg.val, offset, &value);
- pr_info("%02d: %04X ", offset, value);
- }
- }
-
- /* global register page 0~4 */
- for (offset = 0; offset < 5; offset++) {
- if (reg.val == 32) /* dump all phy register */
- dump_phy_reg(0, 16, 31, 0, offset);
- else
- dump_phy_reg(reg.val, 16, 31, 0, offset);
- }
-
- if (reg.val == 32) { /* dump all phy register */
- /* local register port 0-port4 */
- for (offset = 0; offset < 5; offset++) {
- /* dump local page 0 */
- dump_phy_reg(offset, 16, 31, 1, 0);
- /* dump local page 1 */
- dump_phy_reg(offset, 16, 31, 1, 1);
- /* dump local page 2 */
- dump_phy_reg(offset, 16, 31, 1, 2);
- /* dump local page 3 */
- dump_phy_reg(offset, 16, 31, 1, 3);
- }
- } else {
- /* dump local page 0 */
- dump_phy_reg(reg.val, 16, 31, 1, 0);
- /* dump local page 1 */
- dump_phy_reg(reg.val, 16, 31, 1, 1);
- /* dump local page 2 */
- dump_phy_reg(reg.val, 16, 31, 1, 2);
- /* dump local page 3 */
- dump_phy_reg(reg.val, 16, 31, 1, 3);
- }
- break;
-
- case RAETH_ESW_INGRESS_RATE:
- result = copy_from_user(&ratelimit, ifr->ifr_data,
- sizeof(ratelimit));
- offset = 0x1800 + (0x100 * ratelimit.port);
- value = sys_reg_read(RALINK_ETH_SW_BASE + offset);
-
- value &= 0xffff0000;
- if (ratelimit.on_off == 1) {
- value |= (ratelimit.on_off << 15);
- if (ratelimit.bw < 100) {
- value |= (0x0 << 8);
- value |= ratelimit.bw;
- } else if (ratelimit.bw < 1000) {
- value |= (0x1 << 8);
- value |= ratelimit.bw / 10;
- } else if (ratelimit.bw < 10000) {
- value |= (0x2 << 8);
- value |= ratelimit.bw / 100;
- } else if (ratelimit.bw < 100000) {
- value |= (0x3 << 8);
- value |= ratelimit.bw / 1000;
- } else {
- value |= (0x4 << 8);
- value |= ratelimit.bw / 10000;
- }
- }
- pr_info("offset = 0x%4x value=0x%x\n\r", offset, value);
- mii_mgr_write(0x1f, offset, value);
- break;
-
- case RAETH_ESW_EGRESS_RATE:
- result = copy_from_user(&ratelimit, ifr->ifr_data,
- sizeof(ratelimit));
- offset = 0x1040 + (0x100 * ratelimit.port);
- value = sys_reg_read(RALINK_ETH_SW_BASE + offset);
-
- value &= 0xffff0000;
- if (ratelimit.on_off == 1) {
- value |= (ratelimit.on_off << 15);
- if (ratelimit.bw < 100) {
- value |= (0x0 << 8);
- value |= ratelimit.bw;
- } else if (ratelimit.bw < 1000) {
- value |= (0x1 << 8);
- value |= ratelimit.bw / 10;
- } else if (ratelimit.bw < 10000) {
- value |= (0x2 << 8);
- value |= ratelimit.bw / 100;
- } else if (ratelimit.bw < 100000) {
- value |= (0x3 << 8);
- value |= ratelimit.bw / 1000;
- } else {
- value |= (0x4 << 8);
- value |= ratelimit.bw / 10000;
- }
- }
- pr_info("offset = 0x%4x value=0x%x\n\r", offset, value);
- mii_mgr_write(0x1f, offset, value);
- break;
-
- case RAETH_SET_LAN_IP:
- result = copy_from_user(ip_tmp, ifr->ifr_data, IP4_ADDR_LEN);
- strncpy(ei_local->lan_ip4_addr, ip_tmp, IP4_ADDR_LEN);
- pr_info("RAETH_SET_LAN_IP: %s\n", ei_local->lan_ip4_addr);
-
-
- if (ei_local->features & FE_HW_LRO)
- fe_set_hw_lro_my_ip(ei_local->lan_ip4_addr);
- break;
-
- case RAETH_QDMA_IOCTL:
-
- ret =
- copy_from_user(&qdma_data, ifr->ifr_data,
- sizeof(qdma_data));
- ei_qdma_ioctl(dev, ifr, &qdma_data);
-
- break;
-
- case RAETH_EPHY_IOCTL:
-
- ret =
- copy_from_user(&ephy_data, ifr->ifr_data,
- sizeof(ephy_data));
- ephy_ioctl(dev, ifr, &ephy_data);
-
- break;
-
- default:
- ret = -EOPNOTSUPP;
- break;
- }
-
- spin_unlock_irq(&ei_local->page_lock);
- return ret;
-}
-
-static const struct net_device_ops ei_netdev_ops = {
- .ndo_init = ei_init,
- .ndo_uninit = ei_uninit,
- .ndo_open = ei_open,
- .ndo_stop = ei_close,
- .ndo_start_xmit = ei_start_xmit_fake,
- .ndo_get_stats = ra_get_stats,
- .ndo_set_mac_address = ei_set_mac_addr,
- .ndo_change_mtu = ei_change_mtu,
- .ndo_do_ioctl = ei_ioctl,
- .ndo_validate_addr = eth_validate_addr,
-#ifdef CONFIG_NET_POLL_CONTROLLER
- .ndo_poll_controller = raeth_poll_full,
-#endif
-};
-
-void raeth_setup_dev_fptable(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- dev->netdev_ops = &ei_netdev_ops;
-
- if (ei_local->features & FE_ETHTOOL)
- dev->ethtool_ops = &ra_ethtool_ops;
-
-#define TX_TIMEOUT (5 * HZ)
- dev->watchdog_timeo = TX_TIMEOUT;
-}
-
-void ei_ioc_setting(struct platform_device *pdev, struct END_DEVICE *ei_local)
-{
- void __iomem *reg_virt;
- /* unsigned int reg_val; */
-
- if (ei_local->features & FE_HW_IOCOHERENT) {
- pr_info("[Raether] HW IO coherent is enabled !\n");
- /* enable S4 coherence function */
- reg_virt = ioremap(0x10395000, 0x10);
- sys_reg_write(reg_virt, 0x00000003);
-
- /* Enable ETHSYS io coherence path */
- /*reg_virt = ioremap(HW_IOC_BASE, 0x10);*/
- /*reg_virt += IOC_OFFSET;*/
- /*reg_val = sys_reg_read(reg_virt);*/
-
- /*if (ei_local->features & FE_QDMA_FQOS)*/
- /* reg_val |= IOC_ETH_PDMA;*/
- /*else*/
- /* reg_val |= IOC_ETH_PDMA | IOC_ETH_QDMA;*/
-
- /*sys_reg_write(reg_virt, reg_val);*/
- /*reg_virt -= IOC_OFFSET;*/
- iounmap(reg_virt);
-
- arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, TRUE);
-
- if (ei_local->features & FE_QDMA_FQOS)
- arch_setup_dma_ops(&ei_local->qdma_pdev->dev,
- 0, 0, NULL, FALSE);
- else
- arch_setup_dma_ops(&ei_local->qdma_pdev->dev,
- 0, 0, NULL, TRUE);
- } else {
- pr_info("[Raether] HW IO coherent is disabled !\n");
- arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, FALSE);
- arch_setup_dma_ops(&ei_local->qdma_pdev->dev,
- 0, 0, NULL, FALSE);
- }
-}
-
-void fe_chip_name_config(struct END_DEVICE *ei_local, struct platform_device *pdev)
-{
- const char *pm;
- int ret;
-
- ret = of_property_read_string(pdev->dev.of_node, "compatible", &pm);
-
- if (!ret && !strcasecmp(pm, "mediatek,mt7621-eth")) {
- ei_local->chip_name = MT7621_FE;
- pr_info("CHIP_ID = MT7621\n");
- } else if (!strcasecmp(pm, "mediatek,mt7622-raeth")) {
- ei_local->chip_name = MT7622_FE;
- pr_info("CHIP_ID = MT7622\n");
- } else if (!strcasecmp(pm, "mediatek,mt7623-eth")) {
- ei_local->chip_name = MT7623_FE;
- pr_info("CHIP_ID = MT7623\n");
- } else if (!strcasecmp(pm, "mediatek,leopard-eth")) {
- ei_local->chip_name = LEOPARD_FE;
- pr_info("CHIP_ID = LEOPARD_FE\n");
- } else if (!strcasecmp(pm, "mediatek,mt7986-eth")) {
- ei_local->chip_name = MT7986_FE;
- pr_info("CHIP_ID = MT7986_FE\n");
- } else {
- pr_info("CHIP_ID error\n");
- }
-}
-
-void raeth_set_wol(bool enable)
-{
- unsigned int reg_value = 0;
-
- if (enable) {
- reg_value = sys_reg_read(MAC1_WOL);
- reg_value |= (WOL_INT_CLR | WOL_INT_EN | WOL_EN);
- sys_reg_write(MAC1_WOL, reg_value);
-
- } else {
- reg_value = sys_reg_read(MAC1_WOL);
- reg_value &= ~(WOL_INT_EN | WOL_EN);
- sys_reg_write(MAC1_WOL, reg_value);
- }
-}
-
-#if (0)
-static int raeth_resume(struct device *dev)
-{
- raeth_set_wol(false);
- return 0;
-}
-
-static int raeth_suspend(struct device *dev)
-{
- raeth_set_wol(true);
- return 0;
-}
-#endif
-u32 mac_to_gigaphy_mode_addr;
-u32 mac_to_gigaphy_mode_addr2;
-void raeth_arch_setting(struct END_DEVICE *ei_local, struct platform_device *pdev)
-{
- const char *pm;
- int ret;
- u32 val;
-
- ret = of_property_read_string(pdev->dev.of_node, "wan_at", &pm);
- if (!ret) {
- ei_local->architecture |= LAN_WAN_SUPPORT;
- if (!ret && !strcasecmp(pm, "p4")) {
- ei_local->architecture |= WAN_AT_P4;
- pr_info("WAN at P4\n");
- } else if (!strcasecmp(pm, "p0")) {
- ei_local->architecture |= WAN_AT_P0;
- pr_info("WAN at P0\n");
- }
- }
- ret = of_property_read_string(pdev->dev.of_node, "gmac1-support", &pm);
- if (!ret && !strcasecmp(pm, "sgmii-1")) {
- ei_local->architecture |= RAETH_SGMII;
- pr_info("GMAC1 support SGMII\n");
- ret = of_property_read_string(pdev->dev.of_node, "sgmii-mode-1", &pm);
- if (!ret && !strcasecmp(pm, "force-2500")) {
- pr_info("GE1_SGMII_FORCE_2500\n");
- ei_local->architecture |= GE1_SGMII_FORCE_2500;
- } else if (!strcasecmp(pm, "an")) {
- pr_info("GE1_SGMII_AN\n");
- ei_local->architecture |= GE1_SGMII_AN;
- of_property_read_u32(pdev->dev.of_node, "gmac1-phy-address", &val);
- mac_to_gigaphy_mode_addr = val;
- pr_info("mac_to_gigaphy_mode_addr = 0x%x\n", mac_to_gigaphy_mode_addr);
- }
- } else if (!strcasecmp(pm, "rgmii-1")) {
- pr_info("GMAC1 support rgmii\n");
- ret = of_property_read_string(pdev->dev.of_node, "rgmii-mode-1", &pm);
- if (!ret && !strcasecmp(pm, "force-1000")) {
- pr_info("GE1_RGMII_FORCE_1000\n");
- ei_local->architecture |= GE1_RGMII_FORCE_1000;
- } else if (!strcasecmp(pm, "an")) {
- pr_info("GE1_RGMII_AN\n");
- of_property_read_u32(pdev->dev.of_node, "gmac1-phy-address", &val);
- mac_to_gigaphy_mode_addr = val;
- ei_local->architecture |= GE1_RGMII_AN;
- pr_info("mac_to_gigaphy_mode_addr = 0x%x\n", mac_to_gigaphy_mode_addr);
- } else if (!strcasecmp(pm, "one-ephy")) {
- pr_info("GE1_RGMII_ONE_EPHY\n");
- ei_local->architecture |= GE1_RGMII_ONE_EPHY;
- }
-
- } else if (!strcasecmp(pm, "esw")) {
- pr_info("Embedded 5-Port Switch\n");
- ei_local->architecture |= RAETH_ESW;
- if (ei_local->chip_name == MT7622_FE) {
- ei_local->architecture |= MT7622_EPHY;
- } else if (ei_local->chip_name == LEOPARD_FE) {
- ret = of_property_read_string(pdev->dev.of_node, "gmac0", &pm);
- if (!ret && !strcasecmp(pm, "gmii"))
- ei_local->architecture |= LEOPARD_EPHY_GMII;
- ei_local->architecture |= LEOPARD_EPHY;
- }
- } else if (!strcasecmp(pm, "none")) {
- pr_info("GE1_RGMII_NONE\n");
- ei_local->architecture |= GE1_RGMII_NONE;
- } else {
- pr_info("GE1 dts parsing error\n");
- }
-
- ret = of_property_read_string(pdev->dev.of_node, "gmac2-support", &pm);
- if (!ret) {
- ei_local->architecture |= GMAC2;
- ei_local->features |= FE_GE2_SUPPORT;
- }
- if (!ret && !strcasecmp(pm, "sgmii-2")) {
- ei_local->architecture |= GE2_RAETH_SGMII;
- pr_info("GMAC2 support SGMII\n");
- ret = of_property_read_string(pdev->dev.of_node, "sgmii-mode-2", &pm);
- if (!ret && !strcasecmp(pm, "force-2500")) {
- pr_info("GE2_SGMII_FORCE_2500\n");
- ei_local->architecture |= GE2_SGMII_FORCE_2500;
- ret = of_property_read_string(pdev->dev.of_node, "gmac2-force", &pm);
- if (!ret && !strcasecmp(pm, "sgmii-switch")) {
- ei_local->architecture |= SGMII_SWITCH;
- pr_info("GE2_SGMII_FORCE LINK SWITCH\n");
- }
- } else if (!strcasecmp(pm, "an")) {
- pr_info("GE2_SGMII_AN\n");
- ei_local->architecture |= GE2_SGMII_AN;
- of_property_read_u32(pdev->dev.of_node, "gmac2-phy-address", &val);
- mac_to_gigaphy_mode_addr2 = val;
- }
- } else if (!strcasecmp(pm, "rgmii-2")) {
- pr_info("GMAC2 support rgmii\n");
- ret = of_property_read_string(pdev->dev.of_node, "rgmii-mode-2", &pm);
- if (!ret && !strcasecmp(pm, "force-1000")) {
- pr_info("GE2_RGMII_FORCE_1000\n");
- ei_local->architecture |= GE2_RGMII_FORCE_1000;
- } else if (!strcasecmp(pm, "an")) {
- pr_info("RGMII_AN (External GigaPhy)\n");
- of_property_read_u32(pdev->dev.of_node, "gmac2-phy-address", &val);
- mac_to_gigaphy_mode_addr2 = val;
- pr_info("mac_to_gigaphy_mode_addr2 = 0x%x\n", mac_to_gigaphy_mode_addr2);
- ei_local->architecture |= GE2_RGMII_AN;
- } else if (!strcasecmp(pm, "an-internal")) {
- pr_info("RGMII_AN (Internal GigaPhy)\n");
- ei_local->architecture |= GE2_INTERNAL_GPHY;
- }
- } else {
- pr_info("GE2 no connect\n");
- }
-}
-
-void fe_tx_rx_dec(struct END_DEVICE *ei_local, struct platform_device *pdev)
-{
- u32 val;
- u8 i;
-
- of_property_read_u32(pdev->dev.of_node, "gmac1_txq_num", &val);
- gmac1_txq_num = val;
- of_property_read_u32(pdev->dev.of_node, "gmac1_txq_txd_num", &val);
- gmac1_txq_txd_num = val;
- gmac1_txd_num = gmac1_txq_num * gmac1_txq_txd_num;
-
- of_property_read_u32(pdev->dev.of_node, "gmac2_txq_num", &val);
- gmac2_txq_num = val;
- of_property_read_u32(pdev->dev.of_node, "gmac2_txq_txd_num", &val);
- gmac2_txq_txd_num = val;
- gmac2_txd_num = gmac2_txq_num * gmac2_txq_txd_num;
-
- num_tx_desc = gmac1_txd_num + gmac2_txd_num;
- total_txq_num = gmac1_txq_num + gmac2_txq_num;
-
- of_property_read_u32(pdev->dev.of_node, "num_rx_desc", &val);
- num_rx_desc = val;
- num_tx_max_process = num_tx_desc;
-
- ei_local->free_skb = kmalloc_array(num_tx_desc, sizeof(struct sk_buff *), GFP_KERNEL);
-
- ei_local->free_txd_num = kmalloc_array(total_txq_num, sizeof(atomic_t), GFP_KERNEL);
- ei_local->free_txd_head = kmalloc_array(total_txq_num, sizeof(unsigned int), GFP_KERNEL);
- ei_local->free_txd_tail = kmalloc_array(total_txq_num, sizeof(unsigned int), GFP_KERNEL);
- ei_local->txd_pool_info = kmalloc_array(num_tx_desc, sizeof(unsigned int), GFP_KERNEL);
- ei_local->skb_free = kmalloc_array(num_tx_desc, sizeof(struct sk_buff *), GFP_KERNEL);
- ei_local->rls_cnt = kmalloc_array(total_txq_num, sizeof(unsigned int), GFP_KERNEL);
- for (i = 0; i < MAX_RX_RING_NUM; i++)
- ei_local->netrx_skb_data[i] =
- kmalloc_array(num_rx_desc, sizeof(void *), GFP_KERNEL);
- ei_local->netrx0_skb_data = kmalloc_array(num_rx_desc, sizeof(void *), GFP_KERNEL);
-}
-
-/* static struct wakeup_source eth_wake_lock; */
-
-static int rather_probe(struct platform_device *pdev)
-{
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- struct END_DEVICE *ei_local;
- struct net_device *netdev;
- struct device_node *node;
- const char *mac_addr;
- int ret;
- //int i;
-
- netdev = alloc_etherdev_mqs(sizeof(struct END_DEVICE),
- 1, 1);
- if (!netdev)
- return -ENOMEM;
-
- SET_NETDEV_DEV(netdev, &pdev->dev);
-
- dev_raether = netdev;
- ei_local = netdev_priv(netdev);
- ei_local->dev = &pdev->dev;
- ei_local->netdev = netdev;
- fe_features_config(ei_local);
- fe_architecture_config(ei_local);
- fe_chip_name_config(ei_local, pdev);
- raeth_arch_setting(ei_local, pdev);
- fe_tx_rx_dec(ei_local, pdev);
-
- ret = of_property_read_bool(pdev->dev.of_node, "dma-coherent");
- if (ret) {
- pr_err("HW_IOC supported\n");
- ei_local->features |= FE_HW_IOCOHERENT;
- }
-
- if ((ei_local->features & FE_HW_IOCOHERENT) &&
- (ei_local->features & FE_QDMA_FQOS)) {
- pr_err("HW_IOC supported\n");
- ei_local->qdma_pdev =
- platform_device_alloc("QDMA", PLATFORM_DEVID_AUTO);
- if (!ei_local->qdma_pdev) {
- dev_err(&pdev->dev,
- "QDMA platform device allocate fail!\n");
- ret = -ENOMEM;
- goto err_free_dev;
- }
-
- ei_local->qdma_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
- ei_local->qdma_pdev->dev.dma_mask =
- &ei_local->qdma_pdev->dev.coherent_dma_mask;
- } else {
- ei_local->qdma_pdev = pdev;
- }
-
- /* iomap registers */
- node = of_parse_phandle(pdev->dev.of_node, "mediatek,ethsys", 0);
- ethdma_sysctl_base = of_iomap(node, 0);
- if (IS_ERR(ethdma_sysctl_base)) {
- dev_err(&pdev->dev, "no ethdma_sysctl_base found\n");
- return PTR_ERR(ethdma_sysctl_base);
- }
-
- ethdma_frame_engine_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ethdma_frame_engine_base)) {
- dev_err(&pdev->dev, "no ethdma_frame_engine_base found\n");
- return PTR_ERR(ethdma_frame_engine_base);
- }
-
- ethdma_mac_base = ioremap(0x15110000, 0x300);
-
- /* get clock ctrl */
-#if (0)
- if (ei_local->chip_name != MT7621_FE) {
- for (i = 0; i < ARRAY_SIZE(ei_local->clks); i++) {
- ei_local->clks[i] = devm_clk_get(&pdev->dev,
- mtk_clks_source_name[i]);
- if (IS_ERR(ei_local->clks[i])) {
- if (PTR_ERR(ei_local->clks[i]) == -EPROBE_DEFER)
- pr_info("!!!!!EPROBE_DEFER!!!!!\n");
- pr_info("!!!!ENODEV!!!!! clks = %s\n", mtk_clks_source_name[i]);
- }
- }
- }
-#endif
-
- /* get gsw device node */
- ei_local->switch_np = of_parse_phandle(pdev->dev.of_node,
- "mediatek,switch", 0);
-
-#if 0
- /* get MAC address */
- mac_addr = of_get_mac_address(pdev->dev.of_node);
- if (mac_addr)
- ether_addr_copy(netdev->dev_addr, mac_addr);
-#endif
-
- /* get IRQs */
- ei_local->irq0 = platform_get_irq(pdev, 0);
- if (ei_local->chip_name != MT7621_FE) {
- ei_local->irq1 = platform_get_irq(pdev, 1);
- ei_local->irq2 = platform_get_irq(pdev, 2);
- }
- if (ei_local->features & (FE_RSS_4RING | FE_RSS_2RING)) {
- ei_local->irq3 = platform_get_irq(pdev, 3);
- }
-
- pr_err("ei_local->irq0 = %d; ei_local->irq1 = %d; ei_local->irq2 = %d\n", ei_local->irq0, ei_local->irq1, ei_local->irq2);
-#if (0)
- if (ei_local->architecture & RAETH_ESW) {
- if (ei_local->architecture & MT7622_EPHY)
- ei_local->esw_irq = platform_get_irq(pdev, 3);
- else if (ei_local->architecture & LEOPARD_EPHY)
- ei_local->esw_irq = platform_get_irq(pdev, 4);
- pr_info("ei_local->esw_irq = %d\n", ei_local->esw_irq);
- }
-
- if (0)
- ei_clock_enable(ei_local);
-
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE)
- ei_ioc_setting(pdev, ei_local);
-#endif
- raeth_setup_dev_fptable(netdev);
-//alive 01
- ei_mac_addr_setting(netdev);
-//dead 03
- strncpy(netdev->name, DEV_NAME, sizeof(netdev->name) - 1);
- netif_set_real_num_tx_queues(netdev, gmac1_txq_num);
- netif_set_real_num_rx_queues(netdev, 1);
-
- netdev->addr_len = 6;
-//dead 02
-
- mtk_mdio_init(pdev);
-
- netdev->base_addr = (unsigned long)RALINK_FRAME_ENGINE_BASE;
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x100, 0x2105e303);
- sys_reg_write(ETHDMASYS_ETH_MAC_BASE + 0x200, 0x2105e303);
- /* net_device structure Init */
- pr_info
- ("%s %d rx/%d tx descriptors allocated, mtu = %d!\n",
- RAETH_VERSION, num_rx_desc, num_tx_desc, netdev->mtu);
-//dead 01
- if (ei_local->features & FE_ETHTOOL)
- ethtool_init(netdev);
- ret = debug_proc_init();
- if (ret) {
- dev_err(&pdev->dev, "error set debug proc\n");
- goto err_free_dev;
- }
- /* Register net device for the driver */
- ret = register_netdev(netdev);
- if (ret) {
- dev_err(&pdev->dev, "error bringing up device\n");
- goto err_free_dev;
- }
- /*keep ethsys power domain on*/
- device_init_wakeup(&pdev->dev, true);
-
- pr_info("device_init_wakeup\n");
- if (ei_local->features & FE_GE2_SUPPORT) {
- if (!ei_local->pseudo_dev)
- raeth_init_pseudo(ei_local, netdev);
-
- if (!ei_local->pseudo_dev)
- pr_info("Open pseudo_dev failed.\n");
- else
- virtualif_open(ei_local->pseudo_dev);
- }
- return 0;
-
-err_free_dev:
- free_netdev(netdev);
- return ret;
-}
-
-static int raether_remove(struct platform_device *pdev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_QDMA_FQOS)
- if (ei_local->qdma_pdev)
- ei_local->qdma_pdev->dev.release
- (&ei_local->qdma_pdev->dev);
-
- ei_clock_disable(ei_local);
-
- return 0;
-}
-
-#if (0)
-static const struct dev_pm_ops raeth_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(raeth_suspend, raeth_resume)
-};
-#endif
-static const char raeth_string[] = "RAETH_DRV";
-
-static const struct of_device_id raether_of_ids[] = {
- {.compatible = "mediatek,mt7623-eth"},
- {.compatible = "mediatek,mt7622-raeth"},
- {.compatible = "mediatek,mt7621-eth"},
- {.compatible = "mediatek,leopard-eth"},
- {.compatible = "mediatek,mt7986-eth"},
- {},
-};
-
-static struct platform_driver raeth_driver = {
- .probe = rather_probe,
- .remove = raether_remove,
- .driver = {
- .name = raeth_string,
- .owner = THIS_MODULE,
- .of_match_table = raether_of_ids,
- /* .pm = &raeth_pm_ops, */
- },
-};
-
-module_platform_driver(raeth_driver);
-MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.h
deleted file mode 100644
index 5316905..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA2882ETHEND_H
-#define RA2882ETHEND_H
-
-#include "raeth_config.h"
-#include "raeth_reg.h"
-#include "ra_dbg_proc.h"
-#include "ra_ioctl.h"
-
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/skbuff.h>
-#include <linux/if_vlan.h>
-#include <linux/if_ether.h>
-#include <linux/fs.h>
-#include <linux/mii.h>
-#include <linux/uaccess.h>
-#if defined(CONFIG_RAETH_TSO)
-#include <linux/tcp.h>
-#include <net/ipv6.h>
-#include <linux/ip.h>
-#include <net/ip.h>
-#include <net/tcp.h>
-#include <linux/in.h>
-#include <linux/ppp_defs.h>
-#include <linux/if_pppox.h>
-#endif
-#include <linux/netdevice.h>
-#include <linux/if_vlan.h>
-#include <linux/ppp_defs.h>
-
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-#include <linux/of_device.h>
-#include <linux/of_address.h>
-#include <linux/of_net.h>
-#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/clk.h>
-#include <linux/regulator/consumer.h>
-
-#include <linux/dma-mapping.h>
-
-#if defined(CONFIG_MACH_MT7623)
-#include <linux/delay.h>
-#endif
-#include <linux/kthread.h>
-#include <linux/prefetch.h>
-
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
-#include <net/ra_nat.h>
-#endif
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#define ETH_GPIO_BASE 0x10005000
-
-#if defined(CONFIG_QDMA_MQ)
-#define GMAC1_TXQ_NUM 3
-#define GMAC1_TXQ_TXD_NUM 512
-#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM)
-#define GMAC2_TXQ_NUM 1
-#define GMAC2_TXQ_TXD_NUM 128
-#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM)
-#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM)
-#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM)
-#else
-#define TOTAL_TXQ_NUM 2
-#endif
-
-#if defined(CONFIG_MACH_MT7623)
-#define NUM_RX_DESC 2048
-#define NUM_QRX_DESC 16
-#define NUM_PQ_RESV 4
-#define FFA 2048
-#define QUEUE_OFFSET 0x10
-#else
-#define NUM_QRX_DESC 16
-#define NUM_PQ_RESV 4
-#define FFA 512
-#define QUEUE_OFFSET 0x10
-#endif
-
-#if defined(CONFIG_PINCTRL_MT7622)
-#define NUM_PQ 64
-#else
-#define NUM_PQ 16
-#endif
-/* #define NUM_TX_MAX_PROCESS NUM_TX_DESC */
-#define NUM_RX_MAX_PROCESS 16
-
-#define MAX_RX_RING_NUM 4
-#define NUM_LRO_RX_DESC 16
-
-#define MAX_RX_LENGTH 1536
-
-#if defined(CONFIG_SUPPORT_OPENWRT)
-#define DEV_NAME "eth0"
-#define DEV2_NAME "eth1"
-#else
-#define DEV_NAME "eth2"
-#define DEV2_NAME "eth3"
-#endif
-
-#if defined(CONFIG_MACH_MT7623)
-#define GMAC0_OFFSET 0xE000
-#define GMAC2_OFFSET 0xE006
-#else
-#define GMAC0_OFFSET 0x28
-#define GMAC2_OFFSET 0x22
-#endif
-
-#if defined(CONFIG_MACH_MT7623)
-#define IRQ_ENET0 232
-#define IRQ_ENET1 231
-#define IRQ_ENET2 230
-#else
-/* NOTE(Nelson): prom version started from 20150806 */
-#define IRQ_ENET0 255
-#define IRQ_ENET1 256
-#define IRQ_ENET2 257
-#endif
-#define MTK_NAPI_WEIGHT 64
-
-#define RAETH_VERSION "STD_v0.1"
-
-/* MT7623 PSE reset workaround */
-#define FE_RESET_POLLING_MS (5000)
-
-/*LEOPARD POLLING*/
-#define PHY_POLLING_MS (1000)
-#define FE_DEFAULT_LAN_IP "192.168.1.1"
-#define IP4_ADDR_LEN 16
-
-#if defined(CONFIG_SOC_MT7621)
-#define MT_TRIGGER_LOW 0
-#else
-#define MT_TRIGGER_LOW IRQF_TRIGGER_LOW
-#endif
-
-/* This enum allows us to identify how the clock is defined on the array of the
- * clock in the order
- */
-enum mtk_clks_map {
- MTK_CLK_ETHIF,
- MTK_CLK_ESW,
- MTK_CLK_GP0,
- MTK_CLK_GP1,
- MTK_CLK_GP2,
- MTK_CLK_SGMII_TX250M,
- MTK_CLK_SGMII_RX250M,
- MTK_CLK_SGMII_CDR_REF,
- MTK_CLK_SGMII_CDR_FB,
- MTK_CLK_SGMII1_TX250M,
- MTK_CLK_SGMII1_RX250M,
- MTK_CLK_SGMII1_CDR_REF,
- MTK_CLK_SGMII1_CDR_FB,
- MTK_CLK_TRGPLL,
- MTK_CLK_SGMIPLL,
- MTK_CLK_ETH1PLL,
- MTK_CLK_ETH2PLL,
- MTK_CLK_FE,
- MTK_CLK_SGMII_TOP,
- MTK_CLK_MAX
-};
-
-struct END_DEVICE {
- struct device *dev;
- unsigned int tx_cpu_owner_idx0;
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- unsigned int rx_calc_idx[MAX_RX_RING_NUM];
-#endif
- unsigned int tx_ring_full;
- unsigned int tx_full; /* NOTE(Nelso): unused, can remove */
-
- /* PDMA TX PTR */
- dma_addr_t phy_tx_ring0;
-
- /* QDMA TX PTR */
- struct platform_device *qdma_pdev;
- /* struct sk_buff *free_skb[NUM_TX_DESC]; */
- struct sk_buff **free_skb;
- unsigned int tx_dma_ptr;
- unsigned int tx_cpu_ptr;
- unsigned int tx_cpu_idx;
- unsigned int rls_cpu_idx;
- /* atomic_t free_txd_num[TOTAL_TXQ_NUM]; */
- atomic_t *free_txd_num;
- /* unsigned int free_txd_head[TOTAL_TXQ_NUM]; */
- /* unsigned int free_txd_tail[TOTAL_TXQ_NUM]; */
- unsigned int *free_txd_head;
- unsigned int *free_txd_tail;
- struct QDMA_txdesc *txd_pool;
- dma_addr_t phy_txd_pool;
- /* unsigned int txd_pool_info[NUM_TX_DESC]; */
- unsigned int *txd_pool_info;
- struct QDMA_txdesc *free_head;
- unsigned int phy_free_head;
- unsigned int *free_page_head;
- dma_addr_t phy_free_page_head;
- struct PDMA_rxdesc *qrx_ring;
- dma_addr_t phy_qrx_ring;
-
- /* TSO */
- unsigned int skb_txd_num;
-
- /* MT7623 workaround */
- struct work_struct reset_task;
-
- /* workqueue_bh */
- struct work_struct rx_wq;
-
- /* tasklet_bh */
- struct tasklet_struct rx_tasklet;
-
- /* struct sk_buff *skb_free[NUM_TX_DESC]; */
- struct sk_buff **skb_free;
- unsigned int free_idx;
-
- struct net_device_stats stat; /* The new statistics table. */
- spinlock_t page_lock; /* spin_lock for cr access critial section */
- spinlock_t irq_lock; /* spin_lock for isr critial section */
- spinlock_t mdio_lock; /* spin_lock for mdio reg access */
- struct PDMA_txdesc *tx_ring0;
- struct PDMA_rxdesc *rx_ring[MAX_RX_RING_NUM];
- dma_addr_t phy_rx_ring[MAX_RX_RING_NUM];
-
- /* void *netrx_skb_data[MAX_RX_RING_NUM][NUM_RX_DESC]; */
- void **netrx_skb_data[MAX_RX_RING_NUM];
-
- /* struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; */
- /*struct sk_buff **netrx0_skbuf;*/
- void **netrx0_skb_data;
- /* napi */
- struct napi_struct napi;
- struct napi_struct napi_rx;
- struct napi_struct napi_rx_rss0;
- struct napi_struct napi_rx_rss1;
- struct napi_struct napi_rx_rss2;
- struct napi_struct napi_rx_rss3;
- struct napi_struct napi_tx;
- struct net_device dummy_dev;
-
- /* clock control */
- struct clk *clks[MTK_CLK_MAX];
-
- /* gsw device node */
- struct device_node *switch_np;
-
- /* GE1 support */
- struct net_device *netdev;
- /* GE2 support */
- struct net_device *pseudo_dev;
- unsigned int is_pseudo;
-
- struct mii_if_info mii_info;
- struct lro_counters lro_counters;
- struct vlan_group *vlgrp;
-
- /* virtual base addr from device tree */
- void __iomem *ethdma_sysctl_base;
-
- unsigned int irq0;
- unsigned int irq1;
- unsigned int irq2;
- unsigned int irq3;
- unsigned int esw_irq;
- void __iomem *fe_tx_int_status;
- void __iomem *fe_tx_int_enable;
- void __iomem *fe_rx_int_status;
- void __iomem *fe_rx_int_enable;
-
- unsigned int features;
- unsigned int chip_name;
- unsigned int architecture;
-
- /* IP address */
- char lan_ip4_addr[IP4_ADDR_LEN];
-
- /* Function pointers */
- int (*ei_start_xmit)(struct sk_buff *skb, struct net_device *netdev,
- int gmac_no);
- int (*ei_xmit_housekeeping)(struct net_device *netdev, int budget);
- int (*ei_eth_recv)(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
- int (*ei_eth_recv_rss0)(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
- int (*ei_eth_recv_rss1)(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
- int (*ei_eth_recv_rss2)(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
- int (*ei_eth_recv_rss3)(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
- int (*ei_fill_tx_desc)(struct net_device *dev,
- unsigned long *tx_cpu_owner_idx,
- struct sk_buff *skb, int gmac_no);
-
- /* MT7623 PSE reset workaround */
- struct task_struct *kreset_task;
- struct task_struct *kphy_poll_task;
- unsigned int fe_reset_times;
- unsigned int tx_mask;
- unsigned int rx_mask;
- unsigned int *rls_cnt;
-};
-
-struct net_device_stats *ra_get_stats(struct net_device *dev);
-
-int ei_open(struct net_device *dev);
-int ei_close(struct net_device *dev);
-
-int ra2882eth_init(void);
-void ra2882eth_cleanup_module(void);
-
-u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
-u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
-u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr);
-u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
- u32 *read_data);
-u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
- u32 write_data);
-
-/* HNAT functions */
-#if defined(CONFIG_RA_NAT_NONE)
-static int (*ppe_hook_rx_eth)(struct sk_buff *skb);
-static int (*ppe_hook_tx_eth)(struct sk_buff *skb, int gmac_no);
-#else
-extern int (*ppe_hook_rx_eth)(struct sk_buff *skb);
-extern int (*ppe_hook_tx_eth)(struct sk_buff *skb, int gmac_no);
-#endif
-
-/* PDMA functions */
-int fe_pdma_wait_dma_idle(void);
-int fe_pdma_rx_dma_init(struct net_device *dev);
-int fe_pdma_tx_dma_init(struct net_device *dev);
-void fe_pdma_rx_dma_deinit(struct net_device *dev);
-void fe_pdma_tx_dma_deinit(struct net_device *dev);
-void set_fe_pdma_glo_cfg(void);
-int ei_pdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
- int gmac_no);
-int ei_pdma_xmit_housekeeping(struct net_device *netdev,
- int budget);
-int fe_fill_tx_desc(struct net_device *dev,
- unsigned long *tx_cpu_owner_idx,
- struct sk_buff *skb,
- int gmac_no);
-int fe_fill_tx_desc_tso(struct net_device *dev,
- unsigned long *tx_cpu_owner_idx,
- struct sk_buff *skb,
- int gmac_no);
-
-/* QDMA functions */
-int fe_qdma_wait_dma_idle(void);
-int fe_qdma_rx_dma_init(struct net_device *dev);
-int fe_qdma_tx_dma_init(struct net_device *dev);
-void fe_qdma_rx_dma_deinit(struct net_device *dev);
-void fe_qdma_tx_dma_deinit(struct net_device *dev);
-void set_fe_qdma_glo_cfg(void);
-int ei_qdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
- int gmac_no);
-int ei_qdma_xmit_housekeeping(struct net_device *netdev, int budget);
-int ei_qdma_ioctl(struct net_device *dev, struct ifreq *ifr,
- struct qdma_ioctl_data *ioctl_data);
-int ephy_ioctl(struct net_device *dev, struct ifreq *ifr,
- struct ephy_ioctl_data *ioctl_data);
-/* HW LRO functions */
-int fe_hw_lro_init(struct net_device *dev);
-void fe_hw_lro_deinit(struct net_device *dev);
-int fe_hw_lro_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
-void fe_set_hw_lro_my_ip(char *lan_ip_addr);
-
-int fe_rss_4ring_init(struct net_device *dev);
-void fe_rss_4ring_deinit(struct net_device *dev);
-int fe_rss_2ring_init(struct net_device *dev);
-void fe_rss_2ring_deinit(struct net_device *dev);
-int fe_rss0_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
-int fe_rss1_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
-int fe_rss2_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
-int fe_rss3_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget);
-static inline void *raeth_alloc_skb_data(size_t size, gfp_t flags)
-{
-#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
- return kmalloc(size, flags);
-#else
- return netdev_alloc_frag(size);
-#endif
-}
-
-static inline void raeth_free_skb_data(void *addr)
-{
-#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
- kfree(addr);
-#else
- skb_free_frag(addr);
-#endif
-}
-
-static inline struct sk_buff *raeth_build_skb(void *data,
- unsigned int frag_size)
-{
-#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
- return build_skb(data, 0);
-#else
- return build_skb(data, frag_size);
-#endif
-}
-
-extern u32 gmac1_txq_num;
-extern u32 gmac1_txq_txd_num;
-extern u32 gmac1_txd_num;
-extern u32 gmac2_txq_num;
-extern u32 gmac2_txq_txd_num;
-extern u32 gmac2_txd_num;
-extern u32 num_rx_desc;
-extern u32 num_tx_max_process;
-extern u32 num_tx_desc;
-extern u32 total_txq_num;
-extern u32 mac_to_gigaphy_mode_addr;
-extern u32 mac_to_gigaphy_mode_addr2;
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.c
deleted file mode 100644
index 9d76dd0..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.c
+++ /dev/null
@@ -1,619 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "raether_hwlro.h"
-#include "ra_mac.h"
-
-/* HW LRO Force port */
-int set_fe_lro_ring1_cfg(struct net_device *dev)
-{
- unsigned int ip;
-
- pr_debug("set_fe_lro_ring1_cfg()\n");
-
- /* 1. Set RX ring mode to force port */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
-
- /* 2. Configure lro ring */
- /* 2.1 set src/destination TCP ports */
- SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 1122);
- SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 3344);
- /* 2.2 set src/destination IPs */
- str_to_ip(&ip, "10.10.10.3");
- sys_reg_write(LRO_RX_RING1_SIP_DW0, ip);
- str_to_ip(&ip, "10.10.10.254");
- sys_reg_write(LRO_RX_RING1_DIP_DW0, ip);
- /* 2.3 IPv4 force port mode */
- SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1);
- /* 2.4 IPv6 force port mode */
- SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING1, 1);
-
- /* 3. Set Age timer: 10 msec. */
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
-
- /* 4. Valid LRO ring */
- SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
-
- return 0;
-}
-
-int set_fe_lro_ring2_cfg(struct net_device *dev)
-{
- unsigned int ip;
-
- pr_debug("set_fe_lro_ring2_cfg()\n");
-
- /* 1. Set RX ring mode to force port */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_FORCE_PORT);
-
- /* 2. Configure lro ring */
- /* 2.1 set src/destination TCP ports */
- SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 5566);
- SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 7788);
- /* 2.2 set src/destination IPs */
- str_to_ip(&ip, "10.10.10.3");
- sys_reg_write(LRO_RX_RING2_SIP_DW0, ip);
- str_to_ip(&ip, "10.10.10.254");
- sys_reg_write(LRO_RX_RING2_DIP_DW0, ip);
- /* 2.3 IPv4 force port mode */
- SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1);
- /* 2.4 IPv6 force port mode */
- SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING2, 1);
-
- /* 3. Set Age timer: 10 msec. */
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
-
- /* 4. Valid LRO ring */
- SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
-
- return 0;
-}
-
-int set_fe_lro_ring3_cfg(struct net_device *dev)
-{
- unsigned int ip;
-
- pr_debug("set_fe_lro_ring3_cfg()\n");
-
- /* 1. Set RX ring mode to force port */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_FORCE_PORT);
-
- /* 2. Configure lro ring */
- /* 2.1 set src/destination TCP ports */
- SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 9900);
- SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 99);
- /* 2.2 set src/destination IPs */
- str_to_ip(&ip, "10.10.10.3");
- sys_reg_write(LRO_RX_RING3_SIP_DW0, ip);
- str_to_ip(&ip, "10.10.10.254");
- sys_reg_write(LRO_RX_RING3_DIP_DW0, ip);
- /* 2.3 IPv4 force port mode */
- SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1);
- /* 2.4 IPv6 force port mode */
- SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING3, 1);
-
- /* 3. Set Age timer: 10 msec. */
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
-
- /* 4. Valid LRO ring */
- SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
-
- return 0;
-}
-
-int set_fe_lro_glo_cfg(struct net_device *dev)
-{
- unsigned int reg_val = 0;
-
- pr_debug("set_fe_lro_glo_cfg()\n");
-
- /* 1 Set max AGG timer: 10 msec. */
- SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
-
- /* 2. Set max LRO agg count */
- SET_PDMA_LRO_MAX_AGG_CNT(HW_LRO_MAX_AGG_CNT);
-
- /* PDMA prefetch enable setting */
- SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN |
- ADMA_MULTI_RXD_PREFETCH_EN);
-
- /* 2.1 IPv4 checksum update enable */
- SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
-
- /* 3. Polling relinguish */
- while (1) {
- if (sys_reg_read(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH)
- pr_warn("Polling HW LRO RELINGUISH...\n");
- else
- break;
- }
-
- /* 4. Enable LRO */
- reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0);
- reg_val |= PDMA_LRO_EN;
- sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val);
-
- return 0;
-}
-
-void fe_set_hw_lro_my_ip(char *lan_ip_addr)
-{
- unsigned int lan_ip;
-
- str_to_ip(&lan_ip, lan_ip_addr);
- pr_info("[%s]lan_ip_addr = %s (lan_ip = 0x%x)\n",
- __func__, lan_ip_addr, lan_ip);
-
- /* Set my IP_1: LAN IP */
- sys_reg_write(LRO_RX_RING0_DIP_DW0, lan_ip);
- sys_reg_write(LRO_RX_RING0_DIP_DW1, 0);
- sys_reg_write(LRO_RX_RING0_DIP_DW2, 0);
- sys_reg_write(LRO_RX_RING0_DIP_DW3, 0);
- SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
-}
-
-/* HW LRO Auto-learn */
-int set_fe_lro_auto_cfg(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int reg_val = 0;
-
- pr_debug("set_fe_lro_auto_cfg()\n");
-
- fe_set_hw_lro_my_ip(ei_local->lan_ip4_addr);
-
- /* Set RX ring1~3 to auto-learn modes */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
- SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
- SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
-
- /* Valid LRO ring */
- SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
- SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
-
- /* Set AGE timer */
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
- SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
-
- /* Set max AGG timer */
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, HW_LRO_AGG_TIME);
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, HW_LRO_AGG_TIME);
- SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, HW_LRO_AGG_TIME);
-
- /* Set max LRO agg count */
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT);
- SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT);
-
- /* IPv6 LRO enable */
- SET_PDMA_LRO_IPV6_EN(1);
-
- /* IPv4 checksum update enable */
- SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
-
- /* TCP push option check disable */
- /* SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(0); */
-
- /* PDMA prefetch enable setting */
- SET_PDMA_LRO_RXD_PREFETCH_EN(ADMA_RXD_PREFETCH_EN |
- ADMA_MULTI_RXD_PREFETCH_EN);
-
- /* switch priority comparison to packet count mode */
- SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_PKT_CNT_MODE);
-
- /* bandwidth threshold setting */
- SET_PDMA_LRO_BW_THRESHOLD(HW_LRO_BW_THRE);
-
- /* auto-learn score delta setting */
- sys_reg_write(LRO_ALT_SCORE_DELTA, HW_LRO_REPLACE_DELTA);
-
- /* Set ALT timer to 20us: (unit: 20us) */
- SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT);
- /* Set ALT refresh timer to 1 sec. (unit: 20us) */
- SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME);
-
- /* the least remaining room of SDL0 in RXD for lro aggregation */
- SET_PDMA_LRO_MIN_RXD_SDL(HW_LRO_SDL_REMAIN_ROOM);
-
- /* Polling relinguish */
- while (1) {
- if (sys_reg_read(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH)
- pr_warn("Polling HW LRO RELINGUISH...\n");
- else
- break;
- }
-
- /* Enable HW LRO */
- reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0);
- reg_val |= PDMA_LRO_EN;
-
- /*enable cpu reason black list*/
- reg_val |= PDMA_LRO_CRSN_BNW;
- sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val);
-
- /*no use PPE cpu reason 0xff*/
- sys_reg_write(ADMA_LRO_CTRL_DW1, 0xffffffff);
-
- return 0;
-}
-
-int fe_hw_lro_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int skb_size;
- int i, j;
-
- skb_size = SKB_DATA_ALIGN(MAX_LRO_RX_LENGTH + NET_IP_ALIGN) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- /* Initial RX Ring 1 ~ 3 */
- for (i = 1; i < MAX_RX_RING_NUM; i++) {
- ei_local->rx_ring[i] =
- dma_alloc_coherent(dev->dev.parent,
- NUM_LRO_RX_DESC *
- sizeof(struct PDMA_rxdesc),
- &ei_local->phy_rx_ring[i],
- GFP_ATOMIC | __GFP_ZERO);
- for (j = 0; j < NUM_LRO_RX_DESC; j++) {
- ei_local->netrx_skb_data[i][j] =
- raeth_alloc_skb_data(skb_size, GFP_KERNEL);
-
- if (!ei_local->netrx_skb_data[i][j]) {
- pr_err("rx skbuff buffer allocation failed!\n");
- goto no_rx_mem;
- }
-
- memset(&ei_local->rx_ring[i][j], 0,
- sizeof(struct PDMA_rxdesc));
- ei_local->rx_ring[i][j].rxd_info2.DDONE_bit = 0;
- ei_local->rx_ring[i][j].rxd_info2.LS0 = 0;
- ei_local->rx_ring[i][j].rxd_info2.PLEN0 =
- SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
- ei_local->rx_ring[i][j].rxd_info2.PLEN1 =
- SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
- ei_local->rx_ring[i][j].rxd_info1.PDP0 =
- dma_map_single(dev->dev.parent,
- ei_local->netrx_skb_data[i][j] +
- NET_SKB_PAD,
- MAX_LRO_RX_LENGTH, DMA_FROM_DEVICE);
- if (unlikely
- (dma_mapping_error
- (dev->dev.parent,
- ei_local->rx_ring[i][j].rxd_info1.PDP0))) {
- pr_err("[%s]dma_map_single() failed...\n",
- __func__);
- goto no_rx_mem;
- }
- }
- pr_info("\nphy_rx_ring[%d] = 0x%08x, rx_ring[%d] = 0x%p\n",
- i, (unsigned int)ei_local->phy_rx_ring[i],
- i, (void __iomem *)ei_local->rx_ring[i]);
- }
-
- sys_reg_write(RX_BASE_PTR3, phys_to_bus((u32)ei_local->phy_rx_ring[3]));
- sys_reg_write(RX_MAX_CNT3, cpu_to_le32((u32)NUM_LRO_RX_DESC));
- sys_reg_write(RX_CALC_IDX3, cpu_to_le32((u32)(NUM_LRO_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX3);
- sys_reg_write(RX_BASE_PTR2, phys_to_bus((u32)ei_local->phy_rx_ring[2]));
- sys_reg_write(RX_MAX_CNT2, cpu_to_le32((u32)NUM_LRO_RX_DESC));
- sys_reg_write(RX_CALC_IDX2, cpu_to_le32((u32)(NUM_LRO_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX2);
- sys_reg_write(RX_BASE_PTR1, phys_to_bus((u32)ei_local->phy_rx_ring[1]));
- sys_reg_write(RX_MAX_CNT1, cpu_to_le32((u32)NUM_LRO_RX_DESC));
- sys_reg_write(RX_CALC_IDX1, cpu_to_le32((u32)(NUM_LRO_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX1);
-
- if (ei_local->features & FE_HW_LRO_FPORT) {
- set_fe_lro_ring1_cfg(dev);
- set_fe_lro_ring2_cfg(dev);
- set_fe_lro_ring3_cfg(dev);
- set_fe_lro_glo_cfg(dev);
- } else {
- set_fe_lro_auto_cfg(dev);
- }
-
- return 0;
-
-no_rx_mem:
- return -ENOMEM;
-}
-
-void fe_hw_lro_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i, j;
-
- for (i = 1; i < MAX_RX_RING_NUM; i++) {
- /* free RX Ring */
- dma_free_coherent(dev->dev.parent,
- NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc),
- ei_local->rx_ring[i],
- ei_local->phy_rx_ring[i]);
- /* free RX data */
- for (j = 0; j < NUM_LRO_RX_DESC; j++) {
- raeth_free_skb_data(ei_local->netrx_skb_data[i][j]);
- ei_local->netrx_skb_data[i][j] = NULL;
- }
- }
-}
-
-static inline void hw_lro_rx_desc_init(struct END_DEVICE *ei_local,
- struct PDMA_rxdesc *rx_ring,
- unsigned int rx_ring_no,
- dma_addr_t dma_addr)
-{
- if (rx_ring_no != 0) {
- /* lro ring */
- rx_ring->rxd_info2.PLEN0 =
- SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
- rx_ring->rxd_info2.PLEN1 =
- SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
- } else
- /* normal ring */
- rx_ring->rxd_info2.PLEN0 = MAX_RX_LENGTH;
-
- rx_ring->rxd_info1.PDP0 = dma_addr;
- rx_ring->rxd_info2.LS0 = 0;
- rx_ring->rxd_info2.DDONE_bit = 0;
-}
-
-static int get_hw_lro_rx_ring(struct END_DEVICE *ei_local,
- unsigned int rx_idx[])
-{
- int i;
-
- for (i = 0; i < MAX_RX_RING_NUM; i++)
- if (ei_local->rx_ring[i][rx_idx[i]].rxd_info2.DDONE_bit == 1)
- return i;
-
- return 0;
-}
-
-static inline void __iomem *get_rx_cal_idx_reg(unsigned int rx_ring_no)
-{
- return (void __iomem *)(RAETH_RX_CALC_IDX0 + (rx_ring_no << 4));
-}
-
-int fe_hw_lro_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int length = 0;
- unsigned int rx_ring_no = 0, rx_ring_no_next = 0;
- unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next;
- unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM];
- unsigned int skb_size, map_size;
- void __iomem *rx_calc_idx_reg;
- int rx_processed = 0;
-
- /* get cpu owner indexes of rx rings */
- rx_dma_owner_lro[0] = (ei_local->rx_calc_idx[0] + 1) % num_rx_desc;
- rx_dma_owner_lro[1] = (ei_local->rx_calc_idx[1] + 1) % NUM_LRO_RX_DESC;
- rx_dma_owner_lro[2] = (ei_local->rx_calc_idx[2] + 1) % NUM_LRO_RX_DESC;
- rx_dma_owner_lro[3] = (ei_local->rx_calc_idx[3] + 1) % NUM_LRO_RX_DESC;
-
- rx_ring_no = get_hw_lro_rx_ring(ei_local, rx_dma_owner_lro);
- rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no];
- rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx];
- rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no);
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- /* prefetch the next handling RXD */
- if (rx_ring_no == 0) {
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % num_rx_desc;
- skb_size =
- SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_RX_LENGTH;
- } else {
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % NUM_LRO_RX_DESC;
- skb_size =
- SKB_DATA_ALIGN(MAX_LRO_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_LRO_RX_LENGTH;
- }
-
- rx_ring_no_next = get_hw_lro_rx_ring(ei_local,
- rx_dma_owner_lro);
- rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next];
- rx_ring_next =
- &ei_local->rx_ring
- [rx_ring_no_next][rx_dma_owner_idx_next];
- rx_data_next =
- ei_local->netrx_skb_data
- [rx_ring_no_next][rx_dma_owner_idx_next];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_err("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- map_size,
- DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_err("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_err("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = (rx_ring->rxd_info2.PLEN1 << 14) |
- rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (ei_local->pseudo_dev) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_err
- ("pseudo_dev is still not initialize ");
- pr_err
- ("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (likely(rx_ring->rxd_info4.L4VLD))
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- if (IS_SPACE_AVAILABLE_HEAD(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- }
- if (IS_SPACE_AVAILABLE_TAIL(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
- }
-#endif
-
- /* HW LRO aggregation statistics */
- if (ei_local->features & FE_HW_LRO_DBG) {
- hw_lro_stats_update(rx_ring_no, rx_ring);
- hw_lro_flush_stats_update(rx_ring_no, rx_ring);
- }
-
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI)
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- else
- netif_rx(rx_skb);
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* Init RX desc. */
- hw_lro_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- dma_addr);
- ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] =
- new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
-
- sys_reg_write(rx_calc_idx_reg, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- /* use prefetched variable */
- rx_dma_owner_idx = rx_dma_owner_idx_next;
- rx_ring_no = rx_ring_no_next;
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no);
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- hw_lro_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- rx_ring->rxd_info1.PDP0);
- sys_reg_write(rx_calc_idx_reg, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- return (budget + 1);
-}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.h
deleted file mode 100644
index c319aca..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_hwlro.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_HWLRO_H
-#define RA_HWLRO_H
-
-#include "raeth_reg.h"
-
-#define HW_LRO_TIMER_UNIT 1
-#define HW_LRO_REFRESH_TIME 50000
-#define HW_LRO_MAX_AGG_CNT 64
-#define HW_LRO_AGG_DELTA 1
-#define MAX_LRO_RX_LENGTH (PAGE_SIZE * 3)
-#define HW_LRO_AGG_TIME 10 /* 200us */
-#define HW_LRO_AGE_TIME 50 /* 1ms */
-#define HW_LRO_BW_THRE 3000
-#define HW_LRO_REPLACE_DELTA 1000
-#define HW_LRO_SDL_REMAIN_ROOM 1522
-
-struct PDMA_LRO_AUTO_TLB_INFO0_T {
- unsigned int DTP:16;
- unsigned int STP:16;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO1_T {
- unsigned int SIP0:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO2_T {
- unsigned int SIP1:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO3_T {
- unsigned int SIP2:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO4_T {
- unsigned int SIP3:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO5_T {
- unsigned int VLAN_VID0:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO6_T {
- unsigned int VLAN_VID1:16;
- unsigned int VLAN_VID_VLD:4;
- unsigned int CNT:12;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO7_T {
- unsigned int DW_LEN:32;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO8_T {
- unsigned int DIP_ID:2;
- unsigned int IPV6:1;
- unsigned int IPV4:1;
- unsigned int RESV:27;
- unsigned int VALID:1;
-};
-
-struct PDMA_LRO_AUTO_TLB_INFO {
- struct PDMA_LRO_AUTO_TLB_INFO0_T auto_tlb_info0;
- struct PDMA_LRO_AUTO_TLB_INFO1_T auto_tlb_info1;
- struct PDMA_LRO_AUTO_TLB_INFO2_T auto_tlb_info2;
- struct PDMA_LRO_AUTO_TLB_INFO3_T auto_tlb_info3;
- struct PDMA_LRO_AUTO_TLB_INFO4_T auto_tlb_info4;
- struct PDMA_LRO_AUTO_TLB_INFO5_T auto_tlb_info5;
- struct PDMA_LRO_AUTO_TLB_INFO6_T auto_tlb_info6;
- struct PDMA_LRO_AUTO_TLB_INFO7_T auto_tlb_info7;
- struct PDMA_LRO_AUTO_TLB_INFO8_T auto_tlb_info8;
-};
-
-#define PDMA_LRO_EN BIT(0)
-#define PDMA_LRO_IPV6_EN BIT(1)
-#define PDMA_LRO_CRSN_BNW BIT(6)
-#define PDMA_LRO_IPV4_CSUM_UPDATE_EN BIT(7)
-#define PDMA_LRO_IPV4_CTRL_PUSH_EN BIT(23)
-#define PDMA_LRO_RXD_PREFETCH_EN BITS(3, 4)
-#define PDMA_NON_LRO_MULTI_EN BIT(2)
-#define PDMA_LRO_DLY_INT_EN BIT(5)
-#define PDMA_LRO_FUSH_REQ BITS(26, 28)
-#define PDMA_LRO_RELINGUISH BITS(29, 31)
-#define PDMA_LRO_FREQ_PRI_ADJ BITS(16, 19)
-#define PDMA_LRO_TPUT_PRE_ADJ BITS(8, 11)
-#define PDMA_LRO_TPUT_PRI_ADJ BITS(12, 15)
-#define PDMA_LRO_ALT_SCORE_MODE BIT(21)
-#define PDMA_LRO_RING_AGE1 BITS(22, 31)
-#define PDMA_LRO_RING_AGE2 BITS(0, 5)
-#define PDMA_LRO_RING_AGG BITS(10, 25)
-#define PDMA_LRO_RING_AGG_CNT1 BITS(26, 31)
-#define PDMA_LRO_RING_AGG_CNT2 BITS(0, 1)
-#define PDMA_LRO_ALT_TICK_TIMER BITS(16, 20)
-#define PDMA_LRO_LRO_MIN_RXD_SDL0 BITS(16, 31)
-
-#define PDMA_LRO_DLY_INT_EN_OFFSET (5)
-#define PDMA_LRO_TPUT_PRE_ADJ_OFFSET (8)
-#define PDMA_LRO_FREQ_PRI_ADJ_OFFSET (16)
-#define PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET (16)
-#define PDMA_LRO_TPUT_PRI_ADJ_OFFSET (12)
-#define PDMA_LRO_ALT_SCORE_MODE_OFFSET (21)
-#define PDMA_LRO_FUSH_REQ_OFFSET (26)
-#define PDMA_NON_LRO_MULTI_EN_OFFSET (2)
-#define PDMA_LRO_IPV6_EN_OFFSET (1)
-#define PDMA_LRO_RXD_PREFETCH_EN_OFFSET (3)
-#define PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET (7)
-#define PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET (23)
-#define PDMA_LRO_ALT_TICK_TIMER_OFFSET (16)
-
-#define PDMA_LRO_TPUT_OVERFLOW_ADJ BITS(12, 31)
-#define PDMA_LRO_CNT_OVERFLOW_ADJ BITS(0, 11)
-
-#define PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET (12)
-#define PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET (0)
-
-#define PDMA_LRO_ALT_BYTE_CNT_MODE (0)
-#define PDMA_LRO_ALT_PKT_CNT_MODE (1)
-
-/* LRO_RX_RING1_CTRL_DW1 offsets */
-#define PDMA_LRO_AGE_H_OFFSET (10)
-#define PDMA_LRO_RING_AGE1_OFFSET (22)
-#define PDMA_LRO_RING_AGG_CNT1_OFFSET (26)
-/* LRO_RX_RING1_CTRL_DW2 offsets */
-#define PDMA_RX_MODE_OFFSET (6)
-#define PDMA_RX_PORT_VALID_OFFSET (8)
-#define PDMA_RX_MYIP_VALID_OFFSET (9)
-#define PDMA_LRO_RING_AGE2_OFFSET (0)
-#define PDMA_LRO_RING_AGG_OFFSET (10)
-#define PDMA_LRO_RING_AGG_CNT2_OFFSET (0)
-/* LRO_RX_RING1_CTRL_DW3 offsets */
-#define PDMA_LRO_AGG_CNT_H_OFFSET (6)
-/* LRO_RX_RING1_STP_DTP_DW offsets */
-#define PDMA_RX_TCP_SRC_PORT_OFFSET (16)
-#define PDMA_RX_TCP_DEST_PORT_OFFSET (0)
-/* LRO_RX_RING1_CTRL_DW0 offsets */
-#define PDMA_RX_IPV4_FORCE_OFFSET (1)
-#define PDMA_RX_IPV6_FORCE_OFFSET (0)
-
-#define ADMA_MULTI_RXD_PREFETCH_EN BIT(3)
-#define ADMA_RXD_PREFETCH_EN BIT(4)
-
-#define SET_PDMA_LRO_MAX_AGG_CNT(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW3); \
-reg_val &= ~0xff; \
-reg_val |= ((x) & 0xff); \
-sys_reg_write(ADMA_LRO_CTRL_DW3, reg_val); \
-}
-
-#define SET_PDMA_LRO_FLUSH_REQ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_FUSH_REQ; \
-reg_val |= ((x) & 0x7) << PDMA_LRO_FUSH_REQ_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_IPV6_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_IPV6_EN; \
-reg_val |= ((x) & 0x1) << PDMA_LRO_IPV6_EN_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_RXD_PREFETCH_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_RXD_PREFETCH_EN; \
-reg_val |= (x); \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_IPV4_CSUM_UPDATE_EN; \
-reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_IPV4_CTRL_PUSH_EN; \
-reg_val |= ((x) & 0x1) << PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_NON_LRO_MULTI_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~(PDMA_NON_LRO_MULTI_EN); \
-reg_val |= ((x) & 0x1) << PDMA_NON_LRO_MULTI_EN_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_FREQ_PRI_ADJ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_FREQ_PRI_ADJ; \
-reg_val |= ((x) & 0xf) << PDMA_LRO_FREQ_PRI_ADJ_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_TPUT_PRE_ADJ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_TPUT_PRE_ADJ; \
-reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRE_ADJ_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_TPUT_PRI_ADJ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_TPUT_PRI_ADJ; \
-reg_val |= ((x) & 0xf) << PDMA_LRO_TPUT_PRI_ADJ_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_ALT_SCORE_MODE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_ALT_SCORE_MODE; \
-reg_val |= ((x) & 0x1) << PDMA_LRO_ALT_SCORE_MODE_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_DLY_INT_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW0); \
-reg_val &= ~PDMA_LRO_DLY_INT_EN; \
-reg_val |= ((x) & 0x1) << PDMA_LRO_DLY_INT_EN_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW0, reg_val); \
-}
-
-#define SET_PDMA_LRO_BW_THRESHOLD(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW2); \
-reg_val = (x); \
-sys_reg_write(ADMA_LRO_CTRL_DW2, reg_val); \
-}
-
-#define SET_PDMA_LRO_MIN_RXD_SDL(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_LRO_CTRL_DW3); \
-reg_val &= ~PDMA_LRO_LRO_MIN_RXD_SDL0; \
-reg_val |= ((x) & 0xffff) << PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET; \
-sys_reg_write(ADMA_LRO_CTRL_DW3, reg_val); \
-}
-
-#define SET_PDMA_LRO_TPUT_OVERFLOW_ADJ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(PDMA_LRO_ATL_OVERFLOW_ADJ); \
-reg_val &= ~PDMA_LRO_TPUT_OVERFLOW_ADJ; \
-reg_val |= ((x) & 0xfffff) << PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET; \
-sys_reg_write(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \
-}
-
-#define SET_PDMA_LRO_CNT_OVERFLOW_ADJ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(PDMA_LRO_ATL_OVERFLOW_ADJ); \
-reg_val &= ~PDMA_LRO_CNT_OVERFLOW_ADJ; \
-reg_val |= ((x) & 0xfff) << PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET; \
-sys_reg_write(PDMA_LRO_ATL_OVERFLOW_ADJ, reg_val); \
-}
-
-#define SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(x) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_ALT_REFRESH_TIMER); \
-reg_val &= ~PDMA_LRO_ALT_TICK_TIMER; \
-reg_val |= ((x) & 0x1f) << PDMA_LRO_ALT_TICK_TIMER_OFFSET; \
-sys_reg_write(LRO_ALT_REFRESH_TIMER, reg_val); \
-}
-
-#define SET_PDMA_LRO_ALT_REFRESH_TIMER(x) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_ALT_REFRESH_TIMER); \
-reg_val &= ~0xffff; \
-reg_val |= ((x) & 0xffff); \
-sys_reg_write(LRO_ALT_REFRESH_TIMER, reg_val); \
-}
-
-#define SET_PDMA_LRO_MAX_AGG_TIME(x) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_MAX_AGG_TIME); \
-reg_val &= ~0xffff; \
-reg_val |= ((x) & 0xffff); \
-sys_reg_write(LRO_MAX_AGG_TIME, reg_val); \
-}
-
-#define SET_PDMA_RXRING_MODE(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
-reg_val &= ~(0x3 << PDMA_RX_MODE_OFFSET); \
-reg_val |= (y) << PDMA_RX_MODE_OFFSET; \
-sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_MYIP_VALID(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
-reg_val &= ~(0x1 << PDMA_RX_MYIP_VALID_OFFSET); \
-reg_val |= ((y) & 0x1) << PDMA_RX_MYIP_VALID_OFFSET; \
-sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_VALID(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
-reg_val &= ~(0x1 << PDMA_RX_PORT_VALID_OFFSET); \
-reg_val |= ((y) & 0x1) << PDMA_RX_PORT_VALID_OFFSET; \
-sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_TCP_SRC_PORT(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING1_STP_DTP_DW + \
- (((x) - 1) << 6)); \
-reg_val &= ~(0xffff << PDMA_RX_TCP_SRC_PORT_OFFSET); \
-reg_val |= (y) << PDMA_RX_TCP_SRC_PORT_OFFSET; \
-sys_reg_write(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_TCP_DEST_PORT(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING1_STP_DTP_DW + \
- (((x) - 1) << 6)); \
-reg_val &= ~(0xffff << PDMA_RX_TCP_DEST_PORT_OFFSET); \
-reg_val |= (y) << PDMA_RX_TCP_DEST_PORT_OFFSET; \
-sys_reg_write(LRO_RX_RING1_STP_DTP_DW + (((x) - 1) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_IPV4_FORCE_MODE(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \
-reg_val &= ~(0x1 << PDMA_RX_IPV4_FORCE_OFFSET); \
-reg_val |= (y) << PDMA_RX_IPV4_FORCE_OFFSET; \
-sys_reg_write(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_IPV6_FORCE_MODE(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6)); \
-reg_val &= ~(0x1 << PDMA_RX_IPV6_FORCE_OFFSET); \
-reg_val |= (y) << PDMA_RX_IPV6_FORCE_OFFSET; \
-sys_reg_write(LRO_RX_RING1_CTRL_DW0 + (((x) - 1) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_AGE_TIME(x, y) \
-{ \
-unsigned int reg_val1 = sys_reg_read(LRO_RX_RING0_CTRL_DW1 + ((x) << 6)); \
-unsigned int reg_val2 = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
-reg_val1 &= ~PDMA_LRO_RING_AGE1; \
-reg_val2 &= ~PDMA_LRO_RING_AGE2; \
-reg_val1 |= ((y) & 0x3ff) << PDMA_LRO_RING_AGE1_OFFSET; \
-reg_val2 |= (((y) >> PDMA_LRO_AGE_H_OFFSET) & 0x03f) << \
- PDMA_LRO_RING_AGE2_OFFSET;\
-sys_reg_write(LRO_RX_RING0_CTRL_DW1 + ((x) << 6), reg_val1); \
-sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val2); \
-}
-
-#define SET_PDMA_RXRING_AGG_TIME(x, y) \
-{ \
-unsigned int reg_val = sys_reg_read(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
-reg_val &= ~PDMA_LRO_RING_AGG; \
-reg_val |= ((y) & 0xffff) << PDMA_LRO_RING_AGG_OFFSET; \
-sys_reg_write(LRO_RX_RING0_CTRL_DW2 + ((x) << 6), reg_val); \
-}
-
-#define SET_PDMA_RXRING_MAX_AGG_CNT(x, y) \
-{ \
-unsigned int reg_val1 = sys_reg_read(LRO_RX_RING1_CTRL_DW2 + \
- (((x) - 1) << 6)); \
-unsigned int reg_val2 = sys_reg_read(LRO_RX_RING1_CTRL_DW3 + \
- (((x) - 1) << 6)); \
-reg_val1 &= ~PDMA_LRO_RING_AGG_CNT1; \
-reg_val2 &= ~PDMA_LRO_RING_AGG_CNT2; \
-reg_val1 |= ((y) & 0x3f) << PDMA_LRO_RING_AGG_CNT1_OFFSET; \
-reg_val2 |= (((y) >> PDMA_LRO_AGG_CNT_H_OFFSET) & 0x03) << \
- PDMA_LRO_RING_AGG_CNT2_OFFSET; \
-sys_reg_write(LRO_RX_RING1_CTRL_DW2 + (((x) - 1) << 6), reg_val1); \
-sys_reg_write(LRO_RX_RING1_CTRL_DW3 + (((x) - 1) << 6), reg_val2); \
-}
-
-/* HW LRO debug functions */
-void hw_lro_stats_update(unsigned int ring_num,
- struct PDMA_rxdesc *rx_ring);
-void hw_lro_flush_stats_update(unsigned int ring_num,
- struct PDMA_rxdesc *rx_ring);
-
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_pdma.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_pdma.c
deleted file mode 100644
index 344f3d5..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_pdma.c
+++ /dev/null
@@ -1,770 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-
-int fe_pdma_wait_dma_idle(void)
-{
- unsigned int reg_val;
- unsigned int loop_cnt = 0;
-
- while (1) {
- if (loop_cnt++ > 1000)
- break;
- reg_val = sys_reg_read(PDMA_GLO_CFG);
- if ((reg_val & RX_DMA_BUSY)) {
- pr_warn("\n RX_DMA_BUSY !!! ");
- continue;
- }
- if ((reg_val & TX_DMA_BUSY)) {
- pr_warn("\n TX_DMA_BUSY !!! ");
- continue;
- }
- return 0;
- }
-
- return -1;
-}
-
-int fe_pdma_rx_dma_init(struct net_device *dev)
-{
- int i;
- unsigned int skb_size;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- dma_addr_t dma_addr;
-
- skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- /* Initial RX Ring 0 */
- ei_local->rx_ring[0] = dma_alloc_coherent(dev->dev.parent,
- num_rx_desc *
- sizeof(struct PDMA_rxdesc),
- &ei_local->phy_rx_ring[0],
- GFP_ATOMIC | __GFP_ZERO);
- pr_debug("\nphy_rx_ring[0] = 0x%08x, rx_ring[0] = 0x%p\n",
- (unsigned int)ei_local->phy_rx_ring[0],
- (void *)ei_local->rx_ring[0]);
-
- for (i = 0; i < num_rx_desc; i++) {
- ei_local->netrx_skb_data[0][i] =
- raeth_alloc_skb_data(skb_size, GFP_KERNEL);
- if (!ei_local->netrx_skb_data[0][i]) {
- pr_err("rx skbuff buffer allocation failed!");
- goto no_rx_mem;
- }
-
- memset(&ei_local->rx_ring[0][i], 0, sizeof(struct PDMA_rxdesc));
- ei_local->rx_ring[0][i].rxd_info2.DDONE_bit = 0;
- ei_local->rx_ring[0][i].rxd_info2.LS0 = 0;
- ei_local->rx_ring[0][i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
- dma_addr = dma_map_single(dev->dev.parent,
- ei_local->netrx_skb_data[0][i] +
- NET_SKB_PAD,
- MAX_RX_LENGTH,
- DMA_FROM_DEVICE);
- ei_local->rx_ring[0][i].rxd_info1.PDP0 = dma_addr;
- if (unlikely
- (dma_mapping_error
- (dev->dev.parent,
- ei_local->rx_ring[0][i].rxd_info1.PDP0))) {
- pr_err("[%s]dma_map_single() failed...\n", __func__);
- goto no_rx_mem;
- }
- }
-
- /* Tell the adapter where the RX rings are located. */
- sys_reg_write(RX_BASE_PTR0, phys_to_bus((u32)ei_local->phy_rx_ring[0]));
- sys_reg_write(RX_MAX_CNT0, cpu_to_le32((u32)num_rx_desc));
- sys_reg_write(RX_CALC_IDX0, cpu_to_le32((u32)(num_rx_desc - 1)));
-
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX0);
-
- return 0;
-
-no_rx_mem:
- return -ENOMEM;
-}
-
-int fe_pdma_tx_dma_init(struct net_device *dev)
-{
- int i;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-
- for (i = 0; i < num_tx_desc; i++)
- ei_local->skb_free[i] = 0;
-
- ei_local->tx_ring_full = 0;
- ei_local->free_idx = 0;
- ei_local->tx_ring0 =
- dma_alloc_coherent(dev->dev.parent,
- num_tx_desc * sizeof(struct PDMA_txdesc),
- &ei_local->phy_tx_ring0,
- GFP_ATOMIC | __GFP_ZERO);
- pr_debug("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n",
- (unsigned int)ei_local->phy_tx_ring0,
- (void *)ei_local->tx_ring0);
-
- for (i = 0; i < num_tx_desc; i++) {
- memset(&ei_local->tx_ring0[i], 0, sizeof(struct PDMA_txdesc));
- ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
- ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
- }
-
- /* Tell the adapter where the TX rings are located. */
- sys_reg_write(TX_BASE_PTR0, phys_to_bus((u32)ei_local->phy_tx_ring0));
- sys_reg_write(TX_MAX_CNT0, cpu_to_le32((u32)num_tx_desc));
- sys_reg_write(TX_CTX_IDX0, 0);
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- ei_local->tx_cpu_owner_idx0 = 0;
-#endif
- sys_reg_write(PDMA_RST_CFG, PST_DTX_IDX0);
-
- return 0;
-}
-
-void fe_pdma_rx_dma_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i;
-
- /* free RX Ring */
- dma_free_coherent(dev->dev.parent,
- num_rx_desc * sizeof(struct PDMA_rxdesc),
- ei_local->rx_ring[0], ei_local->phy_rx_ring[0]);
-
- /* free RX data */
- for (i = 0; i < num_rx_desc; i++) {
- raeth_free_skb_data(ei_local->netrx_skb_data[0][i]);
- ei_local->netrx_skb_data[0][i] = NULL;
- }
-}
-
-void fe_pdma_tx_dma_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i;
-
- /* free TX Ring */
- if (ei_local->tx_ring0)
- dma_free_coherent(dev->dev.parent,
- num_tx_desc *
- sizeof(struct PDMA_txdesc),
- ei_local->tx_ring0,
- ei_local->phy_tx_ring0);
-
- /* free TX data */
- for (i = 0; i < num_tx_desc; i++) {
- if ((ei_local->skb_free[i] != 0) &&
- (ei_local->skb_free[i] != (struct sk_buff *)0xFFFFFFFF))
- dev_kfree_skb_any(ei_local->skb_free[i]);
- }
-}
-
-void set_fe_pdma_glo_cfg(void)
-{
- unsigned int dma_glo_cfg = 0;
-
- dma_glo_cfg =
- (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS |
- MULTI_EN | ADMA_RX_BT_SIZE_32DWORDS);
-// dma_glo_cfg |= (RX_2B_OFFSET);
-
- sys_reg_write(PDMA_GLO_CFG, dma_glo_cfg);
-}
-
-/* @brief cal txd number for a page
- *
- * @parm size
- *
- * @return frag_txd_num
- */
-static inline unsigned int pdma_cal_frag_txd_num(unsigned int size)
-{
- unsigned int frag_txd_num = 0;
-
- if (size == 0)
- return 0;
- while (size > 0) {
- if (size > MAX_PTXD_LEN) {
- frag_txd_num++;
- size -= MAX_PTXD_LEN;
- } else {
- frag_txd_num++;
- size = 0;
- }
- }
- return frag_txd_num;
-}
-
-int fe_fill_tx_desc(struct net_device *dev,
- unsigned long *tx_cpu_owner_idx,
- struct sk_buff *skb,
- int gmac_no)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PDMA_txdesc *tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx];
- struct PDMA_TXD_INFO2_T txd_info2_tmp;
- struct PDMA_TXD_INFO4_T txd_info4_tmp;
-
- tx_ring->txd_info1.SDP0 = virt_to_phys(skb->data);
- txd_info2_tmp.SDL0 = skb->len;
- txd_info4_tmp.FPORT = gmac_no;
- txd_info4_tmp.TSO = 0;
-
- if (ei_local->features & FE_CSUM_OFFLOAD) {
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- txd_info4_tmp.TUI_CO = 7;
- else
- txd_info4_tmp.TUI_CO = 0;
- }
-
- if (ei_local->features & FE_HW_VLAN_TX) {
- if (skb_vlan_tag_present(skb))
- txd_info4_tmp.VLAN_TAG =
- 0x10000 | skb_vlan_tag_get(skb);
- else
- txd_info4_tmp.VLAN_TAG = 0;
- }
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) {
- if (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- /* PPE */
- txd_info4_tmp.FPORT = 4;
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- } else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) {
- if (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- /* PPE */
- txd_info4_tmp.FPORT = 4;
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- }
-#endif
-
- txd_info2_tmp.LS0_bit = 1;
- txd_info2_tmp.DDONE_bit = 0;
-
- tx_ring->txd_info4 = txd_info4_tmp;
- tx_ring->txd_info2 = txd_info2_tmp;
-
- return 0;
-}
-
-static int fe_fill_tx_tso_data(struct END_DEVICE *ei_local,
- unsigned int frag_offset,
- unsigned int frag_size,
- unsigned long *tx_cpu_owner_idx,
- unsigned int nr_frags,
- int gmac_no)
-{
- struct PSEUDO_ADAPTER *p_ad;
- unsigned int size;
- unsigned int frag_txd_num;
- struct PDMA_txdesc *tx_ring;
-
- frag_txd_num = pdma_cal_frag_txd_num(frag_size);
- tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx];
-
- while (frag_txd_num > 0) {
- if (frag_size < MAX_PTXD_LEN)
- size = frag_size;
- else
- size = MAX_PTXD_LEN;
-
- if (ei_local->skb_txd_num % 2 == 0) {
- *tx_cpu_owner_idx =
- (*tx_cpu_owner_idx + 1) % num_tx_desc;
- tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx];
-
- while (tx_ring->txd_info2.DDONE_bit == 0) {
- if (gmac_no == 2) {
- p_ad =
- netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_errors++;
- } else {
- ei_local->stat.tx_errors++;
- }
- }
- tx_ring->txd_info1.SDP0 = frag_offset;
- tx_ring->txd_info2.SDL0 = size;
- if (((nr_frags == 0)) && (frag_txd_num == 1))
- tx_ring->txd_info2.LS0_bit = 1;
- else
- tx_ring->txd_info2.LS0_bit = 0;
- tx_ring->txd_info2.DDONE_bit = 0;
- tx_ring->txd_info4.FPORT = gmac_no;
- } else {
- tx_ring->txd_info3.SDP1 = frag_offset;
- tx_ring->txd_info2.SDL1 = size;
- if (((nr_frags == 0)) && (frag_txd_num == 1))
- tx_ring->txd_info2.LS1_bit = 1;
- else
- tx_ring->txd_info2.LS1_bit = 0;
- }
- frag_offset += size;
- frag_size -= size;
- frag_txd_num--;
- ei_local->skb_txd_num++;
- }
-
- return 0;
-}
-
-static int fe_fill_tx_tso_frag(struct net_device *netdev,
- struct sk_buff *skb,
- unsigned long *tx_cpu_owner_idx,
- int gmac_no)
-{
- struct END_DEVICE *ei_local = netdev_priv(netdev);
- struct PSEUDO_ADAPTER *p_ad;
- unsigned int size;
- unsigned int frag_txd_num;
- skb_frag_t * frag;
- unsigned int nr_frags;
- unsigned int frag_offset, frag_size;
- struct PDMA_txdesc *tx_ring;
- int i = 0, j = 0, unmap_idx = 0;
-
- nr_frags = skb_shinfo(skb)->nr_frags;
- tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx];
-
- for (i = 0; i < nr_frags; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- frag_offset = 0;
- frag_size = skb_frag_size(frag);
- frag_txd_num = pdma_cal_frag_txd_num(frag_size);
-
- while (frag_txd_num > 0) {
- if (frag_size < MAX_PTXD_LEN)
- size = frag_size;
- else
- size = MAX_PTXD_LEN;
-
- if (ei_local->skb_txd_num % 2 == 0) {
- *tx_cpu_owner_idx =
- (*tx_cpu_owner_idx + 1) % num_tx_desc;
- tx_ring =
- &ei_local->tx_ring0[*tx_cpu_owner_idx];
-
- while (tx_ring->txd_info2.DDONE_bit == 0) {
- if (gmac_no == 2) {
- p_ad =
- netdev_priv
- (ei_local->pseudo_dev);
- p_ad->stat.tx_errors++;
- } else {
- ei_local->stat.tx_errors++;
- }
- }
-
- tx_ring->txd_info1.SDP0 = skb_frag_dma_map(netdev->dev.parent, frag, frag_offset, size, DMA_TO_DEVICE);
-
- if (unlikely
- (dma_mapping_error
- (netdev->dev.parent,
- tx_ring->txd_info1.SDP0))) {
- pr_err
- ("[%s]dma_map_page() failed\n",
- __func__);
- goto err_dma;
- }
-
- tx_ring->txd_info2.SDL0 = size;
-
- if ((frag_txd_num == 1) &&
- (i == (nr_frags - 1)))
- tx_ring->txd_info2.LS0_bit = 1;
- else
- tx_ring->txd_info2.LS0_bit = 0;
- tx_ring->txd_info2.DDONE_bit = 0;
- tx_ring->txd_info4.FPORT = gmac_no;
- } else {
- tx_ring->txd_info3.SDP1 = skb_frag_dma_map(netdev->dev.parent, frag, frag_offset, size, DMA_TO_DEVICE);
-
- if (unlikely
- (dma_mapping_error
- (netdev->dev.parent,
- tx_ring->txd_info3.SDP1))) {
- pr_err
- ("[%s]dma_map_page() failed\n",
- __func__);
- goto err_dma;
- }
- tx_ring->txd_info2.SDL1 = size;
- if ((frag_txd_num == 1) &&
- (i == (nr_frags - 1)))
- tx_ring->txd_info2.LS1_bit = 1;
- else
- tx_ring->txd_info2.LS1_bit = 0;
- }
- frag_offset += size;
- frag_size -= size;
- frag_txd_num--;
- ei_local->skb_txd_num++;
- }
- }
-
- return 0;
-
-err_dma:
- /* unmap dma */
- j = *tx_cpu_owner_idx;
- unmap_idx = i;
- for (i = 0; i < unmap_idx; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- frag_size = skb_frag_size(frag);
- frag_txd_num = pdma_cal_frag_txd_num(frag_size);
-
- while (frag_txd_num > 0) {
- if (frag_size < MAX_PTXD_LEN)
- size = frag_size;
- else
- size = MAX_PTXD_LEN;
- if (ei_local->skb_txd_num % 2 == 0) {
- j = (j + 1) % num_tx_desc;
- dma_unmap_page(netdev->dev.parent,
- ei_local->tx_ring0[j].
- txd_info1.SDP0,
- ei_local->tx_ring0[j].
- txd_info2.SDL0, DMA_TO_DEVICE);
- /* reinit txd */
- ei_local->tx_ring0[j].txd_info2.LS0_bit = 1;
- ei_local->tx_ring0[j].txd_info2.DDONE_bit = 1;
- } else {
- dma_unmap_page(netdev->dev.parent,
- ei_local->tx_ring0[j].
- txd_info3.SDP1,
- ei_local->tx_ring0[j].
- txd_info2.SDL1, DMA_TO_DEVICE);
- /* reinit txd */
- ei_local->tx_ring0[j].txd_info2.LS1_bit = 1;
- }
- frag_size -= size;
- frag_txd_num--;
- ei_local->skb_txd_num++;
- }
- }
-
- return -1;
-}
-
-int fe_fill_tx_desc_tso(struct net_device *dev,
- unsigned long *tx_cpu_owner_idx,
- struct sk_buff *skb,
- int gmac_no)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct iphdr *iph = NULL;
- struct ipv6hdr *ip6h = NULL;
- struct tcphdr *th = NULL;
- unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
- unsigned int len, offset;
- int err;
- struct PDMA_txdesc *tx_ring = &ei_local->tx_ring0[*tx_cpu_owner_idx];
-
- tx_ring->txd_info4.FPORT = gmac_no;
- tx_ring->txd_info4.TSO = 0;
-
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- tx_ring->txd_info4.TUI_CO = 7;
- else
- tx_ring->txd_info4.TUI_CO = 0;
-
- if (ei_local->features & FE_HW_VLAN_TX) {
- if (skb_vlan_tag_present(skb))
- tx_ring->txd_info4.VLAN_TAG =
- 0x10000 | skb_vlan_tag_get(skb);
- else
- tx_ring->txd_info4.VLAN_TAG = 0;
- }
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) {
- if (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- /* PPE */
- tx_ring->txd_info4.FPORT = 4;
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- } else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) {
- if (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- /* PPE */
- tx_ring->txd_info4.FPORT = 4;
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- }
-#endif
- ei_local->skb_txd_num = 1;
-
- /* skb data handle */
- len = skb->len - skb->data_len;
- offset = virt_to_phys(skb->data);
- tx_ring->txd_info1.SDP0 = offset;
- if (len < MAX_PTXD_LEN) {
- tx_ring->txd_info2.SDL0 = len;
- tx_ring->txd_info2.LS0_bit = nr_frags ? 0 : 1;
- len = 0;
- } else {
- tx_ring->txd_info2.SDL0 = MAX_PTXD_LEN;
- tx_ring->txd_info2.LS0_bit = 0;
- len -= MAX_PTXD_LEN;
- offset += MAX_PTXD_LEN;
- }
-
- if (len > 0)
- fe_fill_tx_tso_data(ei_local, offset, len,
- tx_cpu_owner_idx, nr_frags, gmac_no);
-
- /* skb fragments handle */
- if (nr_frags > 0) {
- err = fe_fill_tx_tso_frag(dev, skb, tx_cpu_owner_idx, gmac_no);
- if (unlikely(err))
- return err;
- }
-
- /* fill in MSS info in tcp checksum field */
- if (skb_shinfo(skb)->gso_segs > 1) {
- /* TCP over IPv4 */
- iph = (struct iphdr *)skb_network_header(skb);
- if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
- th = (struct tcphdr *)skb_transport_header(skb);
- tx_ring->txd_info4.TSO = 1;
- th->check = htons(skb_shinfo(skb)->gso_size);
- dma_sync_single_for_device(dev->dev.parent,
- virt_to_phys(th),
- sizeof(struct tcphdr),
- DMA_TO_DEVICE);
- }
-
- /* TCP over IPv6 */
- if (ei_local->features & FE_TSO_V6) {
- ip6h = (struct ipv6hdr *)skb_network_header(skb);
- if ((ip6h->nexthdr == NEXTHDR_TCP) &&
- (ip6h->version == 6)) {
- th = (struct tcphdr *)skb_transport_header(skb);
- tx_ring->txd_info4.TSO = 1;
- th->check = htons(skb_shinfo(skb)->gso_size);
- dma_sync_single_for_device(dev->dev.parent,
- virt_to_phys(th),
- sizeof(struct
- tcphdr),
- DMA_TO_DEVICE);
- }
- }
- }
- tx_ring->txd_info2.DDONE_bit = 0;
-
- return 0;
-}
-
-static inline int rt2880_pdma_eth_send(struct net_device *dev,
- struct sk_buff *skb, int gmac_no,
- unsigned int num_of_frag)
-{
- unsigned int length = skb->len;
- struct END_DEVICE *ei_local = netdev_priv(dev);
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- unsigned long tx_cpu_owner_idx0 = ei_local->tx_cpu_owner_idx0;
-#else
- unsigned long tx_cpu_owner_idx0 = sys_reg_read(TX_CTX_IDX0);
-#endif
- struct PSEUDO_ADAPTER *p_ad;
- int err;
-
- while (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) {
- if (gmac_no == 2) {
- if (ei_local->pseudo_dev) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_errors++;
- } else {
- pr_err
- ("pseudo_dev is still not initialize ");
- pr_err
- ("but receive packet from GMAC2\n");
- }
- } else {
- ei_local->stat.tx_errors++;
- }
- }
-
- if (num_of_frag > 1)
- err = fe_fill_tx_desc_tso(dev, &tx_cpu_owner_idx0,
- skb, gmac_no);
- else
- err = fe_fill_tx_desc(dev, &tx_cpu_owner_idx0, skb, gmac_no);
- if (err)
- return err;
-
- tx_cpu_owner_idx0 = (tx_cpu_owner_idx0 + 1) % num_tx_desc;
- while (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) {
- if (gmac_no == 2) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_errors++;
- } else {
- ei_local->stat.tx_errors++;
- }
- }
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- ei_local->tx_cpu_owner_idx0 = tx_cpu_owner_idx0;
-#endif
- /* make sure that all changes to the dma ring are flushed before we
- * continue
- */
- wmb();
-
- sys_reg_write(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
-
- if (gmac_no == 2) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_packets++;
- p_ad->stat.tx_bytes += length;
- } else {
- ei_local->stat.tx_packets++;
- ei_local->stat.tx_bytes += length;
- }
-
- return length;
-}
-
-int ei_pdma_start_xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned long tx_cpu_owner_idx;
- unsigned int tx_cpu_owner_idx_next, tx_cpu_owner_idx_next2;
- unsigned int num_of_txd, num_of_frag;
- unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i;
- skb_frag_t * frag;
- struct PSEUDO_ADAPTER *p_ad;
- unsigned int tx_cpu_cal_idx;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_tx_eth) {
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (FOE_MAGIC_TAG(skb) != FOE_MAGIC_PPE)
-#endif
- if (ppe_hook_tx_eth(skb, gmac_no) != 1) {
- dev_kfree_skb_any(skb);
- return 0;
- }
- }
-#endif
-
-// dev->trans_start = jiffies; /* save the timestamp */
- netif_trans_update(dev);
- spin_lock(&ei_local->page_lock);
- dma_sync_single_for_device(dev->dev.parent, virt_to_phys(skb->data),
- skb->len, DMA_TO_DEVICE);
-
-#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
- tx_cpu_owner_idx = ei_local->tx_cpu_owner_idx0;
-#else
- tx_cpu_owner_idx = sys_reg_read(TX_CTX_IDX0);
-#endif
-
- if (ei_local->features & FE_TSO) {
- num_of_txd = pdma_cal_frag_txd_num(skb->len - skb->data_len);
- if (nr_frags != 0) {
- for (i = 0; i < nr_frags; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- num_of_txd += pdma_cal_frag_txd_num(skb_frag_size(frag));
-
- }
- }
- num_of_frag = num_of_txd;
- num_of_txd = (num_of_txd + 1) >> 1;
- } else {
- num_of_frag = 1;
- num_of_txd = 1;
- }
-
- tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % num_tx_desc;
-
- if ((ei_local->skb_free[tx_cpu_owner_idx_next] == 0) &&
- (ei_local->skb_free[tx_cpu_owner_idx] == 0)) {
- if (rt2880_pdma_eth_send(dev, skb, gmac_no, num_of_frag) < 0) {
- dev_kfree_skb_any(skb);
- if (gmac_no == 2) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_dropped++;
- } else {
- ei_local->stat.tx_dropped++;
- }
- goto tx_err;
- }
-
- tx_cpu_owner_idx_next2 =
- (tx_cpu_owner_idx_next + 1) % num_tx_desc;
-
- if (ei_local->skb_free[tx_cpu_owner_idx_next2] != 0)
- ei_local->tx_ring_full = 1;
- } else {
- if (gmac_no == 2) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_dropped++;
- } else {
- ei_local->stat.tx_dropped++;
- }
-
- dev_kfree_skb_any(skb);
- spin_unlock(&ei_local->page_lock);
- return NETDEV_TX_OK;
- }
-
- /* SG: use multiple TXD to send the packet (only have one skb) */
- tx_cpu_cal_idx = (tx_cpu_owner_idx + num_of_txd - 1) % num_tx_desc;
- ei_local->skb_free[tx_cpu_cal_idx] = skb;
- while (--num_of_txd)
- /* MAGIC ID */
- ei_local->skb_free[(--tx_cpu_cal_idx) % num_tx_desc] =
- (struct sk_buff *)0xFFFFFFFF;
-
-tx_err:
- spin_unlock(&ei_local->page_lock);
- return NETDEV_TX_OK;
-}
-
-int ei_pdma_xmit_housekeeping(struct net_device *netdev, int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(netdev);
- struct PDMA_txdesc *tx_desc;
- unsigned long skb_free_idx;
- int tx_processed = 0;
-
- tx_desc = ei_local->tx_ring0;
- skb_free_idx = ei_local->free_idx;
-
- while (budget &&
- (ei_local->skb_free[skb_free_idx] != 0) &&
- (tx_desc[skb_free_idx].txd_info2.DDONE_bit == 1)) {
- if (ei_local->skb_free[skb_free_idx] !=
- (struct sk_buff *)0xFFFFFFFF)
- dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
-
- ei_local->skb_free[skb_free_idx] = 0;
- skb_free_idx = (skb_free_idx + 1) % num_tx_desc;
- budget--;
- tx_processed++;
- }
-
- ei_local->tx_ring_full = 0;
- ei_local->free_idx = skb_free_idx;
-
- return tx_processed;
-}
-
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.c
deleted file mode 100644
index a2414c4..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.c
+++ /dev/null
@@ -1,1509 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "ra_ioctl.h"
-#include "raether_qdma.h"
-
-/* skb->mark to queue mapping table */
-struct QDMA_txdesc *free_head;
-
-/* ioctl */
-unsigned int M2Q_table[64] = { 0 };
-EXPORT_SYMBOL(M2Q_table);
-unsigned int lan_wan_separate;
-EXPORT_SYMBOL(lan_wan_separate);
-struct sk_buff *magic_id = (struct sk_buff *)0xFFFFFFFF;
-
-/* CONFIG_HW_SFQ */
-unsigned int web_sfq_enable;
-#define HW_SFQ_UP 3
-#define HW_SFQ_DL 1
-
-#define sfq_debug 0
-struct SFQ_table *sfq0;
-struct SFQ_table *sfq1;
-struct SFQ_table *sfq2;
-struct SFQ_table *sfq3;
-
-#define KSEG1 0xa0000000
-#define PHYS_TO_VIRT(x) phys_to_virt(x)
-#define VIRT_TO_PHYS(x) virt_to_phys(x)
-/* extern void set_fe_dma_glo_cfg(void); */
-struct parse_result sfq_parse_result;
-
-/**
- *
- * @brief: get the TXD index from its address
- *
- * @param: cpu_ptr
- *
- * @return: TXD index
-*/
-
-/**
- * @brief cal txd number for a page
- *
- * @parm size
- *
- * @return frag_txd_num
- */
-
-static inline unsigned int cal_frag_txd_num(unsigned int size)
-{
- unsigned int frag_txd_num = 0;
-
- if (size == 0)
- return 0;
- while (size > 0) {
- if (size > MAX_QTXD_LEN) {
- frag_txd_num++;
- size -= MAX_QTXD_LEN;
- } else {
- frag_txd_num++;
- size = 0;
- }
- }
- return frag_txd_num;
-}
-
-/**
- * @brief get free TXD from TXD queue
- *
- * @param free_txd
- *
- * @return
- */
-static inline int get_free_txd(struct END_DEVICE *ei_local, int ring_no)
-{
- unsigned int tmp_idx;
-
- tmp_idx = ei_local->free_txd_head[ring_no];
- ei_local->free_txd_head[ring_no] = ei_local->txd_pool_info[tmp_idx];
- atomic_sub(1, &ei_local->free_txd_num[ring_no]);
- return tmp_idx;
-}
-
-static inline unsigned int get_phy_addr(struct END_DEVICE *ei_local,
- unsigned int idx)
-{
- return ei_local->phy_txd_pool + (idx * QTXD_LEN);
-}
-
-/**
- * @brief add free TXD into TXD queue
- *
- * @param free_txd
- *
- * @return
- */
-static inline void put_free_txd(struct END_DEVICE *ei_local, int free_txd_idx)
-{
- ei_local->txd_pool_info[ei_local->free_txd_tail[0]] = free_txd_idx;
- ei_local->free_txd_tail[0] = free_txd_idx;
-}
-
-void init_pseudo_link_list(struct END_DEVICE *ei_local)
-{
- int i;
-
- for (i = 0; i < gmac1_txq_num; i++) {
- atomic_set(&ei_local->free_txd_num[i], gmac1_txq_txd_num);
- ei_local->free_txd_head[i] = gmac1_txq_txd_num * i;
- ei_local->free_txd_tail[i] = gmac1_txq_txd_num * (i + 1) - 1;
- }
- for (i = 0; i < gmac2_txq_num; i++) {
- atomic_set(&ei_local->free_txd_num[i + gmac1_txq_num],
- gmac2_txq_txd_num);
- ei_local->free_txd_head[i + gmac1_txq_num] =
- gmac1_txd_num + gmac2_txq_txd_num * i;
- ei_local->free_txd_tail[i + gmac1_txq_num] =
- gmac1_txd_num + gmac2_txq_txd_num * (i + 1) - 1;
- }
-}
-
-static inline int ring_no_mapping(int txd_idx)
-{
- int i;
-
- if (txd_idx < gmac1_txd_num) {
- for (i = 0; i < gmac1_txq_num; i++) {
- if (txd_idx < (gmac1_txq_txd_num * (i + 1)))
- return i;
- }
- }
-
- txd_idx -= gmac1_txd_num;
- for (i = 0; i < gmac2_txq_num; i++) {
- if (txd_idx < (gmac2_txq_txd_num * (i + 1)))
- return (i + gmac1_txq_num);
- }
- pr_err("txd index out of range\n");
- return 0;
-}
-
-/*define qdma initial alloc*/
-/**
- * @brief
- *
- * @param net_dev
- *
- * @return 0: fail
- * 1: success
- */
-bool qdma_tx_desc_alloc(void)
-{
- struct net_device *dev = dev_raether;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int txd_idx;
- int i = 0;
-
- ei_local->txd_pool =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- QTXD_LEN * num_tx_desc,
- &ei_local->phy_txd_pool, GFP_KERNEL);
- pr_err("txd_pool=%p phy_txd_pool=%p\n", ei_local->txd_pool,
- (void *)ei_local->phy_txd_pool);
-
- if (!ei_local->txd_pool) {
- pr_err("adapter->txd_pool allocation failed!\n");
- return 0;
- }
- pr_err("ei_local->skb_free start address is 0x%p.\n",
- ei_local->skb_free);
- /* set all txd_pool_info to 0. */
- for (i = 0; i < num_tx_desc; i++) {
- ei_local->skb_free[i] = 0;
- ei_local->txd_pool_info[i] = i + 1;
- ei_local->txd_pool[i].txd_info3.LS = 1;
- ei_local->txd_pool[i].txd_info3.DDONE = 1;
- }
-
- init_pseudo_link_list(ei_local);
-
- /* get free txd from txd pool */
- txd_idx = get_free_txd(ei_local, 0);
- ei_local->tx_cpu_idx = txd_idx;
- /* add null TXD for transmit */
- sys_reg_write(QTX_CTX_PTR, get_phy_addr(ei_local, txd_idx));
- sys_reg_write(QTX_DTX_PTR, get_phy_addr(ei_local, txd_idx));
-
- /* get free txd from txd pool */
- txd_idx = get_free_txd(ei_local, 0);
- ei_local->rls_cpu_idx = txd_idx;
- /* add null TXD for release */
- sys_reg_write(QTX_CRX_PTR, get_phy_addr(ei_local, txd_idx));
- sys_reg_write(QTX_DRX_PTR, get_phy_addr(ei_local, txd_idx));
-
- /*Reserve 4 TXD for each physical queue */
- if (ei_local->chip_name == MT7623_FE || ei_local->chip_name == MT7621_FE ||
- ei_local->chip_name == LEOPARD_FE) {
- //for (i = 0; i < NUM_PQ; i++)
- for (i = 0; i < 16; i++)
- sys_reg_write(QTX_CFG_0 + QUEUE_OFFSET * i,
- (NUM_PQ_RESV | (NUM_PQ_RESV << 8)));
- }
-
- sys_reg_write(QTX_SCH_1, 0x80000000);
-#if 0
- if (ei_local->chip_name == MT7622_FE) {
- for (i = 0; i < NUM_PQ; i++) {
- if (i <= 15) {
- sys_reg_write(QDMA_PAGE, 0);
- sys_reg_write(QTX_CFG_0 + QUEUE_OFFSET * i,
- (NUM_PQ_RESV |
- (NUM_PQ_RESV << 8)));
- } else if (i > 15 && i <= 31) {
- sys_reg_write(QDMA_PAGE, 1);
- sys_reg_write(QTX_CFG_0 +
- QUEUE_OFFSET * (i - 16),
- (NUM_PQ_RESV |
- (NUM_PQ_RESV << 8)));
- } else if (i > 31 && i <= 47) {
- sys_reg_write(QDMA_PAGE, 2);
- sys_reg_write(QTX_CFG_0 +
- QUEUE_OFFSET * (i - 32),
- (NUM_PQ_RESV |
- (NUM_PQ_RESV << 8)));
- } else if (i > 47 && i <= 63) {
- sys_reg_write(QDMA_PAGE, 3);
- sys_reg_write(QTX_CFG_0 +
- QUEUE_OFFSET * (i - 48),
- (NUM_PQ_RESV |
- (NUM_PQ_RESV << 8)));
- }
- }
- sys_reg_write(QDMA_PAGE, 0);
- }
-#endif
-
- return 1;
-}
-
-bool sfq_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
- unsigned int reg_val;
- dma_addr_t sfq_phy0;
- dma_addr_t sfq_phy1;
- dma_addr_t sfq_phy2;
- dma_addr_t sfq_phy3;
- struct SFQ_table *sfq0 = NULL;
- struct SFQ_table *sfq1 = NULL;
- struct SFQ_table *sfq2 = NULL;
- struct SFQ_table *sfq3 = NULL;
-
- dma_addr_t sfq_phy4;
- dma_addr_t sfq_phy5;
- dma_addr_t sfq_phy6;
- dma_addr_t sfq_phy7;
- struct SFQ_table *sfq4 = NULL;
- struct SFQ_table *sfq5 = NULL;
- struct SFQ_table *sfq6 = NULL;
- struct SFQ_table *sfq7 = NULL;
-
- int i = 0;
-
- reg_val = sys_reg_read(VQTX_GLO);
- reg_val = reg_val | VQTX_MIB_EN;
- /* Virtual table extends to 32bytes */
- sys_reg_write(VQTX_GLO, reg_val);
- reg_val = sys_reg_read(VQTX_GLO);
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- sys_reg_write(VQTX_NUM,
- (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) |
- (VQTX_NUM_3) | (VQTX_NUM_4) | (VQTX_NUM_5) |
- (VQTX_NUM_6) | (VQTX_NUM_7));
- } else {
- sys_reg_write(VQTX_NUM,
- (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) |
- (VQTX_NUM_3));
- }
-
- /* 10 s change hash algorithm */
- sys_reg_write(VQTX_HASH_CFG, 0xF002710);
-
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE)
- sys_reg_write(VQTX_VLD_CFG, 0xeca86420);
- else
- sys_reg_write(VQTX_VLD_CFG, 0xc840);
- sys_reg_write(VQTX_HASH_SD, 0x0D);
- sys_reg_write(QDMA_FC_THRES, 0x9b9b4444);
- sys_reg_write(QDMA_HRED1, 0);
- sys_reg_write(QDMA_HRED2, 0);
- sys_reg_write(QDMA_SRED1, 0);
- sys_reg_write(QDMA_SRED2, 0);
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- sys_reg_write(VQTX_0_3_BIND_QID,
- (VQTX_0_BIND_QID) | (VQTX_1_BIND_QID) |
- (VQTX_2_BIND_QID) | (VQTX_3_BIND_QID));
- sys_reg_write(VQTX_4_7_BIND_QID,
- (VQTX_4_BIND_QID) | (VQTX_5_BIND_QID) |
- (VQTX_6_BIND_QID) | (VQTX_7_BIND_QID));
- pr_err("VQTX_0_3_BIND_QID =%x\n",
- sys_reg_read(VQTX_0_3_BIND_QID));
- pr_err("VQTX_4_7_BIND_QID =%x\n",
- sys_reg_read(VQTX_4_7_BIND_QID));
- }
-
- sfq0 = dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM0 * sizeof(struct SFQ_table), &sfq_phy0,
- GFP_KERNEL);
-
- memset(sfq0, 0x0, VQ_NUM0 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM0; i++) {
- sfq0[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq0[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- sfq1 = dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM1 * sizeof(struct SFQ_table), &sfq_phy1,
- GFP_KERNEL);
- memset(sfq1, 0x0, VQ_NUM1 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM1; i++) {
- sfq1[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq1[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
-
- sfq2 = dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM2 * sizeof(struct SFQ_table), &sfq_phy2,
- GFP_KERNEL);
- memset(sfq2, 0x0, VQ_NUM2 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM2; i++) {
- sfq2[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq2[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
-
- sfq3 = dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM3 * sizeof(struct SFQ_table), &sfq_phy3,
- GFP_KERNEL);
- memset(sfq3, 0x0, VQ_NUM3 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM3; i++) {
- sfq3[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq3[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- if (unlikely((!sfq0)) || unlikely((!sfq1)) ||
- unlikely((!sfq2)) || unlikely((!sfq3))) {
- pr_err("QDMA SFQ0~3 VQ not available...\n");
- return 1;
- }
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- sfq4 =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM4 * sizeof(struct SFQ_table),
- &sfq_phy4, GFP_KERNEL);
- memset(sfq4, 0x0, VQ_NUM4 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM4; i++) {
- sfq4[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq4[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- sfq5 =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM5 * sizeof(struct SFQ_table),
- &sfq_phy5, GFP_KERNEL);
- memset(sfq5, 0x0, VQ_NUM5 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM5; i++) {
- sfq5[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq5[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- sfq6 =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM6 * sizeof(struct SFQ_table),
- &sfq_phy6, GFP_KERNEL);
- memset(sfq6, 0x0, VQ_NUM6 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM6; i++) {
- sfq6[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq6[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- sfq7 =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- VQ_NUM7 * sizeof(struct SFQ_table),
- &sfq_phy7, GFP_KERNEL);
- memset(sfq7, 0x0, VQ_NUM7 * sizeof(struct SFQ_table));
- for (i = 0; i < VQ_NUM7; i++) {
- sfq7[i].sfq_info1.VQHPTR = 0xdeadbeef;
- sfq7[i].sfq_info2.VQTPTR = 0xdeadbeef;
- }
- if (unlikely((!sfq4)) || unlikely((!sfq5)) ||
- unlikely((!sfq6)) || unlikely((!sfq7))) {
- pr_err("QDMA SFQ4~7 VQ not available...\n");
- return 1;
- }
- }
-
- pr_err("*****sfq_phy0 is 0x%p!!!*******\n", (void *)sfq_phy0);
- pr_err("*****sfq_phy1 is 0x%p!!!*******\n", (void *)sfq_phy1);
- pr_err("*****sfq_phy2 is 0x%p!!!*******\n", (void *)sfq_phy2);
- pr_err("*****sfq_phy3 is 0x%p!!!*******\n", (void *)sfq_phy3);
- pr_err("*****sfq_virt0 is 0x%p!!!*******\n", sfq0);
- pr_err("*****sfq_virt1 is 0x%p!!!*******\n", sfq1);
- pr_err("*****sfq_virt2 is 0x%p!!!*******\n", sfq2);
- pr_err("*****sfq_virt3 is 0x%p!!!*******\n", sfq3);
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- pr_err("*****sfq_phy4 is 0x%p!!!*******\n", (void *)sfq_phy4);
- pr_err("*****sfq_phy5 is 0x%p!!!*******\n", (void *)sfq_phy5);
- pr_err("*****sfq_phy6 is 0x%p!!!*******\n", (void *)sfq_phy6);
- pr_err("*****sfq_phy7 is 0x%p!!!*******\n", (void *)sfq_phy7);
- pr_err("*****sfq_virt4 is 0x%p!!!*******\n", sfq4);
- pr_err("*****sfq_virt5 is 0x%p!!!*******\n", sfq5);
- pr_err("*****sfq_virt6 is 0x%p!!!*******\n", sfq6);
- pr_err("*****sfq_virt7 is 0x%p!!!*******\n", sfq7);
- }
-
- sys_reg_write(VQTX_TB_BASE0, (u32)sfq_phy0);
- sys_reg_write(VQTX_TB_BASE1, (u32)sfq_phy1);
- sys_reg_write(VQTX_TB_BASE2, (u32)sfq_phy2);
- sys_reg_write(VQTX_TB_BASE3, (u32)sfq_phy3);
- if (ei_local->chip_name == MT7622_FE || ei_local->chip_name == LEOPARD_FE) {
- sys_reg_write(VQTX_TB_BASE4, (u32)sfq_phy4);
- sys_reg_write(VQTX_TB_BASE5, (u32)sfq_phy5);
- sys_reg_write(VQTX_TB_BASE6, (u32)sfq_phy6);
- sys_reg_write(VQTX_TB_BASE7, (u32)sfq_phy7);
- }
-
- return 0;
-}
-
-bool fq_qdma_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- /* struct QDMA_txdesc *free_head = NULL; */
- dma_addr_t phy_free_head;
- dma_addr_t phy_free_tail;
- unsigned int *free_page_head = NULL;
- dma_addr_t phy_free_page_head;
- int i;
-
- free_head = dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- NUM_QDMA_PAGE *
- QTXD_LEN, &phy_free_head, GFP_KERNEL);
-
- if (unlikely(!free_head)) {
- pr_err("QDMA FQ decriptor not available...\n");
- return 0;
- }
- memset(free_head, 0x0, QTXD_LEN * NUM_QDMA_PAGE);
-
- free_page_head =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- NUM_QDMA_PAGE * QDMA_PAGE_SIZE,
- &phy_free_page_head, GFP_KERNEL);
-
- if (unlikely(!free_page_head)) {
- pr_err("QDMA FQ page not available...\n");
- return 0;
- }
- for (i = 0; i < NUM_QDMA_PAGE; i++) {
- free_head[i].txd_info1.SDP =
- (phy_free_page_head + (i * QDMA_PAGE_SIZE));
- if (i < (NUM_QDMA_PAGE - 1)) {
- free_head[i].txd_info2.NDP =
- (phy_free_head + ((i + 1) * QTXD_LEN));
- }
- free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
- }
- phy_free_tail =
- (phy_free_head + (u32)((NUM_QDMA_PAGE - 1) * QTXD_LEN));
-
- pr_err("phy_free_head is 0x%p!!!\n", (void *)phy_free_head);
- pr_err("phy_free_tail_phy is 0x%p!!!\n", (void *)phy_free_tail);
- sys_reg_write(QDMA_FQ_HEAD, (u32)phy_free_head);
- sys_reg_write(QDMA_FQ_TAIL, (u32)phy_free_tail);
- sys_reg_write(QDMA_FQ_CNT, ((num_tx_desc << 16) | NUM_QDMA_PAGE));
- sys_reg_write(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
- pr_info("gmac1_txd_num:%d; gmac2_txd_num:%d; num_tx_desc:%d\n",
- gmac1_txd_num, gmac2_txd_num, num_tx_desc);
- ei_local->free_head = free_head;
- ei_local->phy_free_head = phy_free_head;
- ei_local->free_page_head = free_page_head;
- ei_local->phy_free_page_head = phy_free_page_head;
- ei_local->tx_ring_full = 0;
- return 1;
-}
-
-int sfq_prot;
-
-#if (sfq_debug)
-int udp_source_port;
-int tcp_source_port;
-int ack_packt;
-#endif
-int sfq_parse_layer_info(struct sk_buff *skb)
-{
- struct vlan_hdr *vh_sfq = NULL;
- struct ethhdr *eth_sfq = NULL;
- struct iphdr *iph_sfq = NULL;
- struct ipv6hdr *ip6h_sfq = NULL;
- struct tcphdr *th_sfq = NULL;
- struct udphdr *uh_sfq = NULL;
-
- memset(&sfq_parse_result, 0, sizeof(sfq_parse_result));
- eth_sfq = (struct ethhdr *)skb->data;
- ether_addr_copy(sfq_parse_result.dmac, eth_sfq->h_dest);
- ether_addr_copy(sfq_parse_result.smac, eth_sfq->h_source);
- /* memcpy(sfq_parse_result.dmac, eth_sfq->h_dest, ETH_ALEN); */
- /* memcpy(sfq_parse_result.smac, eth_sfq->h_source, ETH_ALEN); */
- sfq_parse_result.eth_type = eth_sfq->h_proto;
-
- if (sfq_parse_result.eth_type == htons(ETH_P_8021Q)) {
- sfq_parse_result.vlan1_gap = VLAN_HLEN;
- vh_sfq = (struct vlan_hdr *)(skb->data + ETH_HLEN);
- sfq_parse_result.eth_type = vh_sfq->h_vlan_encapsulated_proto;
- } else {
- sfq_parse_result.vlan1_gap = 0;
- }
-
- /* set layer4 start addr */
- if ((sfq_parse_result.eth_type == htons(ETH_P_IP)) ||
- (sfq_parse_result.eth_type == htons(ETH_P_PPP_SES) &&
- sfq_parse_result.ppp_tag == htons(PPP_IP))) {
- iph_sfq =
- (struct iphdr *)(skb->data + ETH_HLEN +
- (sfq_parse_result.vlan1_gap));
-
- /* prepare layer3/layer4 info */
- memcpy(&sfq_parse_result.iph, iph_sfq, sizeof(struct iphdr));
- if (iph_sfq->protocol == IPPROTO_TCP) {
- th_sfq =
- (struct tcphdr *)(skb->data + ETH_HLEN +
- (sfq_parse_result.vlan1_gap) +
- (iph_sfq->ihl * 4));
- memcpy(&sfq_parse_result.th, th_sfq,
- sizeof(struct tcphdr));
-#if (sfq_debug)
- tcp_source_port = ntohs(sfq_parse_result.th.source);
- udp_source_port = 0;
- /* tcp ack packet */
- if (ntohl(sfq_parse_result.iph.saddr) == 0xa0a0a04)
- ack_packt = 1;
- else
- ack_packt = 0;
-#endif
- sfq_prot = 2; /* IPV4_HNAPT */
- if (iph_sfq->frag_off & htons(IP_MF | IP_OFFSET))
- return 1;
- } else if (iph_sfq->protocol == IPPROTO_UDP) {
- uh_sfq =
- (struct udphdr *)(skb->data + ETH_HLEN +
- (sfq_parse_result.vlan1_gap) +
- iph_sfq->ihl * 4);
- memcpy(&sfq_parse_result.uh, uh_sfq,
- sizeof(struct udphdr));
-#if (sfq_debug)
- udp_source_port = ntohs(sfq_parse_result.uh.source);
- tcp_source_port = 0;
- ack_packt = 0;
-#endif
- sfq_prot = 2; /* IPV4_HNAPT */
- if (iph_sfq->frag_off & htons(IP_MF | IP_OFFSET))
- return 1;
- } else {
- sfq_prot = 1;
- }
- } else if (sfq_parse_result.eth_type == htons(ETH_P_IPV6) ||
- (sfq_parse_result.eth_type == htons(ETH_P_PPP_SES) &&
- sfq_parse_result.ppp_tag == htons(PPP_IPV6))) {
- ip6h_sfq =
- (struct ipv6hdr *)(skb->data + ETH_HLEN +
- (sfq_parse_result.vlan1_gap));
- if (ip6h_sfq->nexthdr == NEXTHDR_TCP) {
- sfq_prot = 4; /* IPV6_5T */
-#if (sfq_debug)
- if (ntohl(sfq_parse_result.ip6h.saddr.s6_addr32[3]) ==
- 8)
- ack_packt = 1;
- else
- ack_packt = 0;
-#endif
- } else if (ip6h_sfq->nexthdr == NEXTHDR_UDP) {
-#if (sfq_debug)
- ack_packt = 0;
-#endif
- sfq_prot = 4; /* IPV6_5T */
-
- } else {
- sfq_prot = 3; /* IPV6_3T */
- }
- }
- return 0;
-}
-
-int rt2880_qdma_eth_send(struct END_DEVICE *ei_local, struct net_device *dev,
- struct sk_buff *skb, int gmac_no, int ring_no)
-{
- unsigned int length = skb->len;
- struct QDMA_txdesc *cpu_ptr, *prev_cpu_ptr;
- struct QDMA_txdesc dummy_desc;
- struct PSEUDO_ADAPTER *p_ad;
- unsigned long flags;
- unsigned int next_txd_idx, qidx;
-
- cpu_ptr = &dummy_desc;
- /* 2. prepare data */
- dma_sync_single_for_device(&ei_local->qdma_pdev->dev,
- virt_to_phys(skb->data),
- skb->len, DMA_TO_DEVICE);
- /* cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data); */
- cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data);
- cpu_ptr->txd_info3.SDL = skb->len;
- if (ei_local->features & FE_HW_SFQ) {
- sfq_parse_layer_info(skb);
- cpu_ptr->txd_info5.VQID0 = 1; /* 1:HW hash 0:CPU */
- cpu_ptr->txd_info5.PROT = sfq_prot;
- /* no vlan */
- cpu_ptr->txd_info5.IPOFST = 14 + (sfq_parse_result.vlan1_gap);
- }
- cpu_ptr->txd_info4.FPORT = gmac_no;
-
- if (ei_local->features & FE_CSUM_OFFLOAD) {
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- cpu_ptr->txd_info5.TUI_CO = 7;
- else
- cpu_ptr->txd_info5.TUI_CO = 0;
- }
-
- if (ei_local->features & FE_HW_VLAN_TX) {
- if (skb_vlan_tag_present(skb)) {
- cpu_ptr->txd_info6.INSV_1 = 1;
- cpu_ptr->txd_info6.VLAN_TAG_1 = skb_vlan_tag_get(skb);
- cpu_ptr->txd_info4.QID = skb_vlan_tag_get(skb);
- } else {
- cpu_ptr->txd_info4.QID = ring_no;
- cpu_ptr->txd_info6.INSV_1 = 0;
- cpu_ptr->txd_info6.VLAN_TAG_1 = 0;
- }
- } else {
- cpu_ptr->txd_info6.INSV_1 = 0;
- cpu_ptr->txd_info6.VLAN_TAG_1 = 0;
- }
- cpu_ptr->txd_info4.QID = 0;
- /* cpu_ptr->txd_info4.QID = ring_no; */
-
- if ((ei_local->features & QDMA_QOS_MARK) && (skb->mark != 0)) {
- if (skb->mark < 64) {
- qidx = M2Q_table[skb->mark];
- cpu_ptr->txd_info4.QID = ((qidx & 0x30) >> 4);
- cpu_ptr->txd_info4.QID = (qidx & 0x0f);
- } else {
- pr_debug("skb->mark out of range\n");
- cpu_ptr->txd_info4.QID = 0;
- cpu_ptr->txd_info4.QID = 0;
- }
- }
- /* QoS Web UI used */
- if ((ei_local->features & QDMA_QOS_WEB) && (lan_wan_separate == 1)) {
- if (web_sfq_enable == 1 && (skb->mark == 2)) {
- if (gmac_no == 1)
- cpu_ptr->txd_info4.QID = HW_SFQ_DL;
- else
- cpu_ptr->txd_info4.QID = HW_SFQ_UP;
- } else if (gmac_no == 2) {
- cpu_ptr->txd_info4.QID += 8;
- }
- }
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) {
- if (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- cpu_ptr->txd_info4.FPORT = 3; /* PPE */
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- } else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) {
- if (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- cpu_ptr->txd_info4.FPORT = 3; /* PPE */
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- }
-#endif
-
- /* dma_sync_single_for_device(NULL, virt_to_phys(skb->data), */
- /* skb->len, DMA_TO_DEVICE); */
- cpu_ptr->txd_info4.SWC = 1;
-
- /* 5. move CPU_PTR to new TXD */
- cpu_ptr->txd_info5.TSO = 0;
- cpu_ptr->txd_info3.LS = 1;
- cpu_ptr->txd_info3.DDONE = 0;
- next_txd_idx = get_free_txd(ei_local, ring_no);
- cpu_ptr->txd_info2.NDP = get_phy_addr(ei_local, next_txd_idx);
- spin_lock_irqsave(&ei_local->page_lock, flags);
- prev_cpu_ptr = ei_local->txd_pool + ei_local->tx_cpu_idx;
- /* update skb_free */
- ei_local->skb_free[ei_local->tx_cpu_idx] = skb;
- /* update tx cpu idx */
- ei_local->tx_cpu_idx = next_txd_idx;
- /* update txd info */
- prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1;
- prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2;
- prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4;
- prev_cpu_ptr->txd_info5 = dummy_desc.txd_info5;
- prev_cpu_ptr->txd_info6 = dummy_desc.txd_info6;
- prev_cpu_ptr->txd_info7 = dummy_desc.txd_info7;
- prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3;
- /* NOTE: add memory barrier to avoid
- * DMA access memory earlier than memory written
- */
- wmb();
- /* update CPU pointer */
- sys_reg_write(QTX_CTX_PTR,
- get_phy_addr(ei_local, ei_local->tx_cpu_idx));
- spin_unlock_irqrestore(&ei_local->page_lock, flags);
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- if (gmac_no == 2) {
- if (ei_local->pseudo_dev) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_packets++;
-
- p_ad->stat.tx_bytes += length;
- }
- } else {
- ei_local->stat.tx_packets++;
- ei_local->stat.tx_bytes += skb->len;
- }
- } else {
- ei_local->stat.tx_packets++;
- ei_local->stat.tx_bytes += skb->len;
- }
- if (ei_local->features & FE_INT_NAPI) {
- if (ei_local->tx_full == 1) {
- ei_local->tx_full = 0;
- netif_wake_queue(dev);
- }
- }
-
- return length;
-}
-
-int rt2880_qdma_eth_send_tso(struct END_DEVICE *ei_local,
- struct net_device *dev, struct sk_buff *skb,
- int gmac_no, int ring_no)
-{
- unsigned int length = skb->len;
- struct QDMA_txdesc *cpu_ptr, *prev_cpu_ptr;
- struct QDMA_txdesc dummy_desc;
- struct QDMA_txdesc init_dummy_desc;
- int ctx_idx;
- struct iphdr *iph = NULL;
- struct QDMA_txdesc *init_cpu_ptr;
- struct tcphdr *th = NULL;
- skb_frag_t * frag;
- unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
- unsigned int len, size, frag_txd_num, qidx;
- dma_addr_t offset;
- unsigned long flags;
- int i;
- int init_qid, init_qid1;
- struct ipv6hdr *ip6h = NULL;
- struct PSEUDO_ADAPTER *p_ad;
-
- init_cpu_ptr = &init_dummy_desc;
- cpu_ptr = &init_dummy_desc;
-
- len = length - skb->data_len;
- dma_sync_single_for_device(&ei_local->qdma_pdev->dev,
- virt_to_phys(skb->data),
- len,
- DMA_TO_DEVICE);
- offset = virt_to_phys(skb->data);
- cpu_ptr->txd_info1.SDP = offset;
- if (len > MAX_QTXD_LEN) {
- cpu_ptr->txd_info3.SDL = MAX_QTXD_LEN;
- cpu_ptr->txd_info3.LS = 0;
- len -= MAX_QTXD_LEN;
- offset += MAX_QTXD_LEN;
- } else {
- cpu_ptr->txd_info3.SDL = len;
- cpu_ptr->txd_info3.LS = nr_frags ? 0 : 1;
- len = 0;
- }
- if (ei_local->features & FE_HW_SFQ) {
- sfq_parse_layer_info(skb);
-
- cpu_ptr->txd_info5.VQID0 = 1;
- cpu_ptr->txd_info5.PROT = sfq_prot;
- /* no vlan */
- cpu_ptr->txd_info5.IPOFST = 14 + (sfq_parse_result.vlan1_gap);
- }
- if (gmac_no == 1)
- cpu_ptr->txd_info4.FPORT = 1;
- else
- cpu_ptr->txd_info4.FPORT = 2;
-
- cpu_ptr->txd_info5.TSO = 0;
- cpu_ptr->txd_info4.QID = 0;
- /* cpu_ptr->txd_info4.QID = ring_no; */
- if ((ei_local->features & QDMA_QOS_MARK) && (skb->mark != 0)) {
- if (skb->mark < 64) {
- qidx = M2Q_table[skb->mark];
- cpu_ptr->txd_info4.QID = qidx;
-
- } else {
- pr_debug("skb->mark out of range\n");
- cpu_ptr->txd_info4.QID = 0;
-
- }
- }
- if (ei_local->features & FE_CSUM_OFFLOAD) {
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- cpu_ptr->txd_info5.TUI_CO = 7;
- else
- cpu_ptr->txd_info5.TUI_CO = 0;
- }
-
- if (ei_local->features & FE_HW_VLAN_TX) {
- if (skb_vlan_tag_present(skb)) {
- cpu_ptr->txd_info6.INSV_1 = 1;
- cpu_ptr->txd_info6.VLAN_TAG_1 = skb_vlan_tag_get(skb);
- cpu_ptr->txd_info4.QID = skb_vlan_tag_get(skb);
- } else {
- cpu_ptr->txd_info4.QID = ring_no;
- cpu_ptr->txd_info6.INSV_1 = 0;
- cpu_ptr->txd_info6.VLAN_TAG_1 = 0;
- }
- } else {
- cpu_ptr->txd_info6.INSV_1 = 0;
- cpu_ptr->txd_info6.VLAN_TAG_1 = 0;
- }
-
- if ((ei_local->features & FE_GE2_SUPPORT) && (lan_wan_separate == 1)) {
- if (web_sfq_enable == 1 && (skb->mark == 2)) {
- if (gmac_no == 1)
- cpu_ptr->txd_info4.QID = HW_SFQ_DL;
- else
- cpu_ptr->txd_info4.QID = HW_SFQ_UP;
- } else if (gmac_no == 2) {
- cpu_ptr->txd_info4.QID += 8;
- }
- }
- /*debug multi tx queue */
- init_qid = cpu_ptr->txd_info4.QID;
- init_qid1 = cpu_ptr->txd_info4.QID;
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (IS_MAGIC_TAG_PROTECT_VALID_HEAD(skb)) {
- if (FOE_MAGIC_TAG_HEAD(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- cpu_ptr->txd_info4.FPORT = 3; /* PPE */
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- } else if (IS_MAGIC_TAG_PROTECT_VALID_TAIL(skb)) {
- if (FOE_MAGIC_TAG_TAIL(skb) == FOE_MAGIC_PPE) {
- if (ppe_hook_rx_eth) {
- cpu_ptr->txd_info4.FPORT = 3; /* PPE */
- FOE_MAGIC_TAG(skb) = 0;
- }
- }
- }
-#endif
-
- cpu_ptr->txd_info4.SWC = 1;
-
- ctx_idx = get_free_txd(ei_local, ring_no);
- cpu_ptr->txd_info2.NDP = get_phy_addr(ei_local, ctx_idx);
- /*prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1;
- *prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2;
- *prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3;
- *prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4;
- */
- if (len > 0) {
- frag_txd_num = cal_frag_txd_num(len);
- for (frag_txd_num = frag_txd_num; frag_txd_num > 0;
- frag_txd_num--) {
- if (len < MAX_QTXD_LEN)
- size = len;
- else
- size = MAX_QTXD_LEN;
-
- cpu_ptr = (ei_local->txd_pool + (ctx_idx));
- dummy_desc.txd_info1 = cpu_ptr->txd_info1;
- dummy_desc.txd_info2 = cpu_ptr->txd_info2;
- dummy_desc.txd_info3 = cpu_ptr->txd_info3;
- dummy_desc.txd_info4 = cpu_ptr->txd_info4;
- dummy_desc.txd_info5 = cpu_ptr->txd_info5;
- dummy_desc.txd_info6 = cpu_ptr->txd_info6;
- dummy_desc.txd_info7 = cpu_ptr->txd_info7;
- prev_cpu_ptr = cpu_ptr;
- cpu_ptr = &dummy_desc;
- cpu_ptr->txd_info4.QID = init_qid;
- cpu_ptr->txd_info4.QID = init_qid1;
- cpu_ptr->txd_info1.SDP = offset;
- cpu_ptr->txd_info3.SDL = size;
- if ((nr_frags == 0) && (frag_txd_num == 1))
- cpu_ptr->txd_info3.LS = 1;
- else
- cpu_ptr->txd_info3.LS = 0;
- cpu_ptr->txd_info3.DDONE = 0;
- cpu_ptr->txd_info4.SWC = 1;
- if (cpu_ptr->txd_info3.LS == 1)
- ei_local->skb_free[ctx_idx] = skb;
- else
- ei_local->skb_free[ctx_idx] = magic_id;
- ctx_idx = get_free_txd(ei_local, ring_no);
- cpu_ptr->txd_info2.NDP =
- get_phy_addr(ei_local, ctx_idx);
- prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1;
- prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2;
- prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3;
- prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4;
- prev_cpu_ptr->txd_info5 = dummy_desc.txd_info5;
- prev_cpu_ptr->txd_info6 = dummy_desc.txd_info6;
- prev_cpu_ptr->txd_info7 = dummy_desc.txd_info7;
- offset += size;
- len -= size;
- }
- }
-
- for (i = 0; i < nr_frags; i++) {
- /* 1. set or get init value for current fragment */
- offset = 0;
- frag = &skb_shinfo(skb)->frags[i];
- len = skb_frag_size(frag);
- frag_txd_num = cal_frag_txd_num(len);
- for (frag_txd_num = frag_txd_num;
- frag_txd_num > 0; frag_txd_num--) {
- /* 2. size will be assigned to SDL
- * and can't be larger than MAX_TXD_LEN
- */
- if (len < MAX_QTXD_LEN)
- size = len;
- else
- size = MAX_QTXD_LEN;
-
- /* 3. Update TXD info */
- cpu_ptr = (ei_local->txd_pool + (ctx_idx));
- dummy_desc.txd_info1 = cpu_ptr->txd_info1;
- dummy_desc.txd_info2 = cpu_ptr->txd_info2;
- dummy_desc.txd_info3 = cpu_ptr->txd_info3;
- dummy_desc.txd_info4 = cpu_ptr->txd_info4;
- dummy_desc.txd_info5 = cpu_ptr->txd_info5;
- dummy_desc.txd_info6 = cpu_ptr->txd_info6;
- dummy_desc.txd_info7 = cpu_ptr->txd_info7;
- prev_cpu_ptr = cpu_ptr;
- cpu_ptr = &dummy_desc;
- cpu_ptr->txd_info4.QID = init_qid;
- cpu_ptr->txd_info4.QID = init_qid1;
- cpu_ptr->txd_info1.SDP = skb_frag_dma_map(&ei_local->qdma_pdev->dev, frag, offset, size, DMA_TO_DEVICE);
- if (unlikely(dma_mapping_error
- (&ei_local->qdma_pdev->dev,
- cpu_ptr->txd_info1.SDP)))
- pr_err("[%s]dma_map_page() failed...\n",
- __func__);
-
- cpu_ptr->txd_info3.SDL = size;
-
- if ((i == (nr_frags - 1)) && (frag_txd_num == 1))
- cpu_ptr->txd_info3.LS = 1;
- else
- cpu_ptr->txd_info3.LS = 0;
- cpu_ptr->txd_info3.DDONE = 0;
- cpu_ptr->txd_info4.SWC = 1;
- /* 4. Update skb_free for housekeeping */
- if (cpu_ptr->txd_info3.LS == 1)
- ei_local->skb_free[ctx_idx] = skb;
- else
- ei_local->skb_free[ctx_idx] = magic_id;
-
- /* 5. Get next TXD */
- ctx_idx = get_free_txd(ei_local, ring_no);
- cpu_ptr->txd_info2.NDP =
- get_phy_addr(ei_local, ctx_idx);
- prev_cpu_ptr->txd_info1 = dummy_desc.txd_info1;
- prev_cpu_ptr->txd_info2 = dummy_desc.txd_info2;
- prev_cpu_ptr->txd_info3 = dummy_desc.txd_info3;
- prev_cpu_ptr->txd_info4 = dummy_desc.txd_info4;
- prev_cpu_ptr->txd_info5 = dummy_desc.txd_info5;
- prev_cpu_ptr->txd_info6 = dummy_desc.txd_info6;
- prev_cpu_ptr->txd_info7 = dummy_desc.txd_info7;
- /* 6. Update offset and len. */
- offset += size;
- len -= size;
- }
- }
-
- if (skb_shinfo(skb)->gso_segs > 1) {
- /* TsoLenUpdate(skb->len); */
-
- /* TCP over IPv4 */
- iph = (struct iphdr *)skb_network_header(skb);
- if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
- th = (struct tcphdr *)skb_transport_header(skb);
-
- init_cpu_ptr->txd_info5.TSO = 1;
-
- th->check = htons(skb_shinfo(skb)->gso_size);
-
- dma_sync_single_for_device(&ei_local->qdma_pdev->dev,
- virt_to_phys(th),
- sizeof(struct
- tcphdr),
- DMA_TO_DEVICE);
- }
- if (ei_local->features & FE_TSO_V6) {
- ip6h = (struct ipv6hdr *)skb_network_header(skb);
- if ((ip6h->nexthdr == NEXTHDR_TCP) &&
- (ip6h->version == 6)) {
- th = (struct tcphdr *)skb_transport_header(skb);
- init_cpu_ptr->txd_info5.TSO = 1;
- th->check = htons(skb_shinfo(skb)->gso_size);
- dma_sync_single_for_device(&ei_local->qdma_pdev->dev,
- virt_to_phys(th),
- sizeof(struct
- tcphdr),
- DMA_TO_DEVICE);
- }
- }
-
- if (ei_local->features & FE_HW_SFQ) {
- init_cpu_ptr->txd_info5.VQID0 = 1;
- init_cpu_ptr->txd_info5.PROT = sfq_prot;
- /* no vlan */
- init_cpu_ptr->txd_info5.IPOFST =
- 14 + (sfq_parse_result.vlan1_gap);
- }
- }
- /* dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); */
-
- init_cpu_ptr->txd_info3.DDONE = 0;
- spin_lock_irqsave(&ei_local->page_lock, flags);
- prev_cpu_ptr = ei_local->txd_pool + ei_local->tx_cpu_idx;
- ei_local->skb_free[ei_local->tx_cpu_idx] = magic_id;
- ei_local->tx_cpu_idx = ctx_idx;
- prev_cpu_ptr->txd_info1 = init_dummy_desc.txd_info1;
- prev_cpu_ptr->txd_info2 = init_dummy_desc.txd_info2;
- prev_cpu_ptr->txd_info4 = init_dummy_desc.txd_info4;
- prev_cpu_ptr->txd_info3 = init_dummy_desc.txd_info3;
- prev_cpu_ptr->txd_info5 = init_dummy_desc.txd_info5;
- prev_cpu_ptr->txd_info6 = init_dummy_desc.txd_info6;
- prev_cpu_ptr->txd_info7 = init_dummy_desc.txd_info7;
-
- /* NOTE: add memory barrier to avoid
- * DMA access memory earlier than memory written
- */
- wmb();
- sys_reg_write(QTX_CTX_PTR,
- get_phy_addr(ei_local, ei_local->tx_cpu_idx));
- spin_unlock_irqrestore(&ei_local->page_lock, flags);
-
- if (ei_local->features & FE_GE2_SUPPORT) {
- if (gmac_no == 2) {
- if (ei_local->pseudo_dev) {
- p_ad = netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_packets++;
- p_ad->stat.tx_bytes += length;
- }
- } else {
- ei_local->stat.tx_packets++;
- ei_local->stat.tx_bytes += skb->len;
- }
- } else {
- ei_local->stat.tx_packets++;
- ei_local->stat.tx_bytes += skb->len;
- }
- if (ei_local->features & FE_INT_NAPI) {
- if (ei_local->tx_full == 1) {
- ei_local->tx_full = 0;
- netif_wake_queue(dev);
- }
- }
-
- return length;
-}
-
-/* QDMA functions */
-int fe_qdma_wait_dma_idle(void)
-{
- unsigned int reg_val;
-
- while (1) {
- reg_val = sys_reg_read(QDMA_GLO_CFG);
- if ((reg_val & RX_DMA_BUSY)) {
- pr_err("\n RX_DMA_BUSY !!! ");
- continue;
- }
- if ((reg_val & TX_DMA_BUSY)) {
- pr_err("\n TX_DMA_BUSY !!! ");
- continue;
- }
- return 0;
- }
-
- return -1;
-}
-
-int fe_qdma_rx_dma_init(struct net_device *dev)
-{
- int i;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int skb_size;
- /* Initial QDMA RX Ring */
-
- skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN + NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- ei_local->qrx_ring =
- dma_alloc_coherent(&ei_local->qdma_pdev->dev,
- NUM_QRX_DESC * sizeof(struct PDMA_rxdesc),
- &ei_local->phy_qrx_ring,
- GFP_ATOMIC | __GFP_ZERO);
- for (i = 0; i < NUM_QRX_DESC; i++) {
- ei_local->netrx0_skb_data[i] =
- raeth_alloc_skb_data(skb_size, GFP_KERNEL);
- if (!ei_local->netrx0_skb_data[i]) {
- pr_err("rx skbuff buffer allocation failed!");
- goto no_rx_mem;
- }
-
- memset(&ei_local->qrx_ring[i], 0, sizeof(struct PDMA_rxdesc));
- ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0;
- ei_local->qrx_ring[i].rxd_info2.LS0 = 0;
- ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
- ei_local->qrx_ring[i].rxd_info1.PDP0 =
- dma_map_single(&ei_local->qdma_pdev->dev,
- ei_local->netrx0_skb_data[i] +
- NET_SKB_PAD,
- MAX_RX_LENGTH,
- DMA_FROM_DEVICE);
- if (unlikely
- (dma_mapping_error
- (&ei_local->qdma_pdev->dev,
- ei_local->qrx_ring[i].rxd_info1.PDP0))) {
- pr_err("[%s]dma_map_single() failed...\n", __func__);
- goto no_rx_mem;
- }
- }
- pr_err("\nphy_qrx_ring = 0x%p, qrx_ring = 0x%p\n",
- (void *)ei_local->phy_qrx_ring, ei_local->qrx_ring);
-
- /* Tell the adapter where the RX rings are located. */
- sys_reg_write(QRX_BASE_PTR_0,
- phys_to_bus((u32)ei_local->phy_qrx_ring));
- sys_reg_write(QRX_MAX_CNT_0, cpu_to_le32((u32)NUM_QRX_DESC));
- sys_reg_write(QRX_CRX_IDX_0, cpu_to_le32((u32)(NUM_QRX_DESC - 1)));
-
- sys_reg_write(QDMA_RST_CFG, PST_DRX_IDX0);
- ei_local->rx_ring[0] = ei_local->qrx_ring;
-
- return 0;
-
-no_rx_mem:
- return -ENOMEM;
-}
-
-int fe_qdma_tx_dma_init(struct net_device *dev)
-{
- bool pass;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- if (ei_local->features & FE_HW_SFQ)
- sfq_init(dev);
- /*tx desc alloc, add a NULL TXD to HW */
- pass = qdma_tx_desc_alloc();
- if (!pass)
- return -1;
-
- pass = fq_qdma_init(dev);
- if (!pass)
- return -1;
-
- return 0;
-}
-
-void fe_qdma_rx_dma_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i;
-
- /* free RX Ring */
- dma_free_coherent(&ei_local->qdma_pdev->dev,
- NUM_QRX_DESC * sizeof(struct PDMA_rxdesc),
- ei_local->qrx_ring, ei_local->phy_qrx_ring);
-
- /* free RX skb */
- for (i = 0; i < NUM_QRX_DESC; i++) {
- raeth_free_skb_data(ei_local->netrx0_skb_data[i]);
- ei_local->netrx0_skb_data[i] = NULL;
- }
-}
-
-void fe_qdma_tx_dma_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i;
-
- /* free TX Ring */
- if (ei_local->txd_pool)
- dma_free_coherent(&ei_local->qdma_pdev->dev,
- num_tx_desc * QTXD_LEN,
- ei_local->txd_pool, ei_local->phy_txd_pool);
- if (ei_local->free_head)
- dma_free_coherent(&ei_local->qdma_pdev->dev,
- NUM_QDMA_PAGE * QTXD_LEN,
- ei_local->free_head, ei_local->phy_free_head);
- if (ei_local->free_page_head)
- dma_free_coherent(&ei_local->qdma_pdev->dev,
- NUM_QDMA_PAGE * QDMA_PAGE_SIZE,
- ei_local->free_page_head,
- ei_local->phy_free_page_head);
-
- /* free TX data */
- for (i = 0; i < num_tx_desc; i++) {
- if ((ei_local->skb_free[i] != (struct sk_buff *)0xFFFFFFFF) &&
- (ei_local->skb_free[i] != 0))
- dev_kfree_skb_any(ei_local->skb_free[i]);
- }
-}
-
-void set_fe_qdma_glo_cfg(void)
-{
- unsigned int reg_val;
- unsigned int dma_glo_cfg = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- reg_val = sys_reg_read(QDMA_GLO_CFG);
- reg_val &= 0x000000FF;
-
- sys_reg_write(QDMA_GLO_CFG, reg_val);
- reg_val = sys_reg_read(QDMA_GLO_CFG);
-
- /* Enable randon early drop and set drop threshold automatically */
- if (!(ei_local->features & FE_HW_SFQ))
- sys_reg_write(QDMA_FC_THRES, 0x4444);
- sys_reg_write(QDMA_HRED2, 0x0);
-
- dma_glo_cfg =
- (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS | PDMA_DESC_32B_E);
- dma_glo_cfg |= (RX_2B_OFFSET);
- sys_reg_write(QDMA_GLO_CFG, dma_glo_cfg);
-
- pr_err("Enable QDMA TX NDP coherence check and re-read mechanism\n");
- reg_val = sys_reg_read(QDMA_GLO_CFG);
- reg_val = reg_val | 0x400 | 0x100000;
- sys_reg_write(QDMA_GLO_CFG, reg_val);
- //sys_reg_write(QDMA_GLO_CFG, 0x95404575);
- sys_reg_write(QDMA_GLO_CFG, 0x95404475);
- pr_err("***********QDMA_GLO_CFG=%x\n", sys_reg_read(QDMA_GLO_CFG));
-}
-
-int ei_qdma_start_xmit(struct sk_buff *skb, struct net_device *dev, int gmac_no)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int num_of_txd = 0;
- unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i;
- skb_frag_t * frag;
- struct PSEUDO_ADAPTER *p_ad;
- int ring_no;
-
- ring_no = skb->queue_mapping + (gmac_no - 1) * gmac1_txq_num;
-
-#if defined(CONFIG_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_tx_eth) {
- if (ppe_hook_tx_eth(skb, gmac_no) != 1) {
- dev_kfree_skb_any(skb);
- return 0;
- }
- }
-#endif
-
-// dev->trans_start = jiffies; /* save the timestamp */
- netif_trans_update(dev);
- /*spin_lock_irqsave(&ei_local->page_lock, flags); */
-
- /* check free_txd_num before calling rt288_eth_send() */
-
- if (ei_local->features & FE_TSO) {
- num_of_txd += cal_frag_txd_num(skb->len - skb->data_len);
- if (nr_frags != 0) {
- for (i = 0; i < nr_frags; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- num_of_txd += cal_frag_txd_num(skb_frag_size(frag));
- }
- }
- } else {
- num_of_txd = 1;
- }
-
-/* if ((ei_local->free_txd_num > num_of_txd + 1)) { */
- if (likely(atomic_read(&ei_local->free_txd_num[ring_no]) >
- (num_of_txd + 1))) {
- if (num_of_txd == 1)
- rt2880_qdma_eth_send(ei_local, dev, skb,
- gmac_no, ring_no);
- else
- rt2880_qdma_eth_send_tso(ei_local, dev, skb,
- gmac_no, ring_no);
- } else {
- if (ei_local->features & FE_GE2_SUPPORT) {
- if (gmac_no == 2) {
- if (ei_local->pseudo_dev) {
- p_ad =
- netdev_priv(ei_local->pseudo_dev);
- p_ad->stat.tx_dropped++;
- }
- } else {
- ei_local->stat.tx_dropped++;
- }
- } else {
- ei_local->stat.tx_dropped++;
- }
- /* kfree_skb(skb); */
- dev_kfree_skb_any(skb);
- /* spin_unlock_irqrestore(&ei_local->page_lock, flags); */
- return 0;
- }
- /* spin_unlock_irqrestore(&ei_local->page_lock, flags); */
- return 0;
-}
-
-int ei_qdma_xmit_housekeeping(struct net_device *netdev, int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(netdev);
-
- dma_addr_t dma_ptr;
- struct QDMA_txdesc *cpu_ptr = NULL;
- dma_addr_t tmp_ptr;
- unsigned int ctx_offset = 0;
- unsigned int dtx_offset = 0;
- unsigned int rls_cnt[TOTAL_TXQ_NUM] = { 0 };
- int ring_no;
- int i;
-
- dma_ptr = (dma_addr_t)sys_reg_read(QTX_DRX_PTR);
- ctx_offset = ei_local->rls_cpu_idx;
- dtx_offset = (dma_ptr - ei_local->phy_txd_pool) / QTXD_LEN;
- cpu_ptr = (ei_local->txd_pool + (ctx_offset));
- while (ctx_offset != dtx_offset) {
- /* 1. keep cpu next TXD */
- tmp_ptr = (dma_addr_t)cpu_ptr->txd_info2.NDP;
- ring_no = ring_no_mapping(ctx_offset);
- rls_cnt[ring_no]++;
- /* 2. release TXD */
- ei_local->txd_pool_info[ei_local->free_txd_tail[ring_no]] =
- ctx_offset;
- ei_local->free_txd_tail[ring_no] = ctx_offset;
- /* atomic_add(1, &ei_local->free_txd_num[ring_no]); */
- /* 3. update ctx_offset and free skb memory */
- ctx_offset = (tmp_ptr - ei_local->phy_txd_pool) / QTXD_LEN;
- if (ei_local->features & FE_TSO) {
- if (ei_local->skb_free[ctx_offset] != magic_id) {
- dev_kfree_skb_any(ei_local->skb_free
- [ctx_offset]);
- }
- } else {
- dev_kfree_skb_any(ei_local->skb_free[ctx_offset]);
- }
- ei_local->skb_free[ctx_offset] = 0;
- /* 4. update cpu_ptr */
- cpu_ptr = (ei_local->txd_pool + ctx_offset);
- }
- for (i = 0; i < TOTAL_TXQ_NUM; i++) {
- if (rls_cnt[i] > 0)
- atomic_add(rls_cnt[i], &ei_local->free_txd_num[i]);
- }
- /* atomic_add(rls_cnt, &ei_local->free_txd_num[0]); */
- ei_local->rls_cpu_idx = ctx_offset;
- netif_wake_queue(netdev);
- if (ei_local->features & FE_GE2_SUPPORT)
- netif_wake_queue(ei_local->pseudo_dev);
- ei_local->tx_ring_full = 0;
- sys_reg_write(QTX_CRX_PTR,
- (ei_local->phy_txd_pool + (ctx_offset * QTXD_LEN)));
-
- return 0;
-}
-
-int ei_qdma_ioctl(struct net_device *dev, struct ifreq *ifr,
- struct qdma_ioctl_data *data)
-{
- int ret = 0;
- struct END_DEVICE *ei_local = netdev_priv(dev);
- unsigned int cmd;
-
- cmd = data->cmd;
-
- switch (cmd) {
- case RAETH_QDMA_REG_READ:
-
- if (data->off > REG_HQOS_MAX) {
- ret = -EINVAL;
- break;
- }
-
- if (ei_local->chip_name == MT7622_FE) { /* harry */
- unsigned int page = 0;
-
- /* q16~q31: 0x100 <= data->off < 0x200
- * q32~q47: 0x200 <= data->off < 0x300
- * q48~q63: 0x300 <= data->off < 0x400
- */
- if (data->off >= 0x100 && data->off < 0x200) {
- page = 1;
- data->off = data->off - 0x100;
- } else if (data->off >= 0x200 && data->off < 0x300) {
- page = 2;
- data->off = data->off - 0x200;
- } else if (data->off >= 0x300 && data->off < 0x400) {
- page = 3;
- data->off = data->off - 0x300;
- } else {
- page = 0;
- }
- /*magic number for ioctl identify CR 0x1b101a14*/
- if (data->off == 0x777) {
- page = 0;
- data->off = 0x214;
- }
-
- sys_reg_write(QDMA_PAGE, page);
- /* pr_debug("page=%d, data->off =%x\n", page, data->off); */
- }
-
- data->val = sys_reg_read(QTX_CFG_0 + data->off);
- pr_info("read reg off:%x val:%x\n", data->off, data->val);
- ret = copy_to_user(ifr->ifr_data, data, sizeof(*data));
- sys_reg_write(QDMA_PAGE, 0);
- if (ret) {
- pr_info("ret=%d\n", ret);
- ret = -EFAULT;
- }
- break;
- case RAETH_QDMA_REG_WRITE:
-
- if (data->off > REG_HQOS_MAX) {
- ret = -EINVAL;
- break;
- }
-
- if (ei_local->chip_name == MT7622_FE) { /* harry */
- unsigned int page = 0;
- /*QoS must enable QDMA drop packet policy*/
- sys_reg_write(QDMA_FC_THRES, 0x83834444);
- /* q16~q31: 0x100 <= data->off < 0x200
- * q32~q47: 0x200 <= data->off < 0x300
- * q48~q63: 0x300 <= data->off < 0x400
- */
- if (data->off >= 0x100 && data->off < 0x200) {
- page = 1;
- data->off = data->off - 0x100;
- } else if (data->off >= 0x200 && data->off < 0x300) {
- page = 2;
- data->off = data->off - 0x200;
- } else if (data->off >= 0x300 && data->off < 0x400) {
- page = 3;
- data->off = data->off - 0x300;
- } else {
- page = 0;
- }
- /*magic number for ioctl identify CR 0x1b101a14*/
- if (data->off == 0x777) {
- page = 0;
- data->off = 0x214;
- }
- sys_reg_write(QDMA_PAGE, page);
- /*pr_info("data->val =%x\n", data->val);*/
- sys_reg_write(QTX_CFG_0 + data->off, data->val);
- sys_reg_write(QDMA_PAGE, 0);
- } else {
- sys_reg_write(QTX_CFG_0 + data->off, data->val);
- }
- /* pr_ino("write reg off:%x val:%x\n", data->off, data->val); */
- break;
- case RAETH_QDMA_QUEUE_MAPPING:
- if ((data->off & 0x100) == 0x100) {
- lan_wan_separate = 1;
- data->off &= 0xff;
- } else {
- lan_wan_separate = 0;
- data->off &= 0xff;
- }
- M2Q_table[data->off] = data->val;
- break;
- case RAETH_QDMA_SFQ_WEB_ENABLE:
- if (ei_local->features & FE_HW_SFQ) {
- if ((data->val) == 0x1)
- web_sfq_enable = 1;
- else
- web_sfq_enable = 0;
- } else {
- ret = -EINVAL;
- }
- break;
- default:
- ret = 1;
- break;
- }
-
- return ret;
-}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.h
deleted file mode 100644
index ce1af4d..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_qdma.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Carlos Huang <carlos.huang@mediatek.com>
- * Author: Harry Huang <harry.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RAETHER_QDMA_H
-#define RAETHER_QDMA_H
-
-extern struct net_device *dev_raether;
-void set_fe_dma_glo_cfg(void);
-
-#endif
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.c
deleted file mode 100644
index 972c4e0..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.c
+++ /dev/null
@@ -1,1222 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "raether.h"
-#include "raether_rss.h"
-#include "raether_hwlro.h"
-#include "ra_mac.h"
-
-static struct proc_dir_entry *proc_rss_ring1, *proc_rss_ring2, *proc_rss_ring3;
-
-int fe_rss_4ring_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int skb_size;
- int i, j;
-
- skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- /* Initial RX Ring 1 ~ 3 */
- for (i = 1; i < MAX_RX_RING_NUM; i++) {
- ei_local->rx_ring[i] =
- dma_alloc_coherent(dev->dev.parent,
- NUM_RSS_RX_DESC *
- sizeof(struct PDMA_rxdesc),
- &ei_local->phy_rx_ring[i],
- GFP_ATOMIC | __GFP_ZERO);
- for (j = 0; j < NUM_RSS_RX_DESC; j++) {
- ei_local->netrx_skb_data[i][j] =
- raeth_alloc_skb_data(skb_size, GFP_KERNEL);
-
- if (!ei_local->netrx_skb_data[i][j]) {
- pr_info("rx skbuff buffer allocation failed!\n");
- goto no_rx_mem;
- }
-
- memset(&ei_local->rx_ring[i][j], 0,
- sizeof(struct PDMA_rxdesc));
- ei_local->rx_ring[i][j].rxd_info2.DDONE_bit = 0;
- ei_local->rx_ring[i][j].rxd_info2.LS0 = 0;
- ei_local->rx_ring[i][j].rxd_info2.PLEN0 =
- SET_ADMA_RX_LEN0(MAX_RX_LENGTH);
- ei_local->rx_ring[i][j].rxd_info1.PDP0 =
- dma_map_single(dev->dev.parent,
- ei_local->netrx_skb_data[i][j] +
- NET_SKB_PAD,
- MAX_RX_LENGTH, DMA_FROM_DEVICE);
- if (unlikely
- (dma_mapping_error
- (dev->dev.parent,
- ei_local->rx_ring[i][j].rxd_info1.PDP0))) {
- pr_info("[%s]dma_map_single() failed...\n",
- __func__);
- goto no_rx_mem;
- }
- }
- pr_info("\nphy_rx_ring[%d] = 0x%08x, rx_ring[%d] = 0x%p\n",
- i, (unsigned int)ei_local->phy_rx_ring[i],
- i, (void __iomem *)ei_local->rx_ring[i]);
- }
-
- sys_reg_write(RX_BASE_PTR3, phys_to_bus((u32)ei_local->phy_rx_ring[3]));
- sys_reg_write(RX_MAX_CNT3, cpu_to_le32((u32)NUM_RSS_RX_DESC));
- sys_reg_write(RX_CALC_IDX3, cpu_to_le32((u32)(NUM_RSS_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX3);
- sys_reg_write(RX_BASE_PTR2, phys_to_bus((u32)ei_local->phy_rx_ring[2]));
- sys_reg_write(RX_MAX_CNT2, cpu_to_le32((u32)NUM_RSS_RX_DESC));
- sys_reg_write(RX_CALC_IDX2, cpu_to_le32((u32)(NUM_RSS_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX2);
- sys_reg_write(RX_BASE_PTR1, phys_to_bus((u32)ei_local->phy_rx_ring[1]));
- sys_reg_write(RX_MAX_CNT1, cpu_to_le32((u32)NUM_RSS_RX_DESC));
- sys_reg_write(RX_CALC_IDX1, cpu_to_le32((u32)(NUM_RSS_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX1);
-
- /* 1. Set RX ring1~3 to pse modes */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE);
- SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_PSE_MODE);
- SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_PSE_MODE);
-
- /* 2. Enable non-lro multiple rx */
- SET_PDMA_NON_LRO_MULTI_EN(1); /* MRX EN */
-
- /*Hash Type*/
- SET_PDMA_RSS_IPV4_TYPE(7);
- SET_PDMA_RSS_IPV6_TYPE(7);
- /* 3. Select the size of indirection table */
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW0, 0x39393939);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW1, 0x93939393);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW2, 0x39399393);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW3, 0x93933939);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW4, 0x39393939);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW5, 0x93939393);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW6, 0x39399393);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW7, 0x93933939);
- /* 4. Pause */
- SET_PDMA_RSS_CFG_REQ(1);
-
- /* 5. Enable RSS */
- SET_PDMA_RSS_EN(1);
-
- /* 6. Release pause */
- SET_PDMA_RSS_CFG_REQ(0);
-
- return 0;
-
-no_rx_mem:
- return -ENOMEM;
-}
-
-void fe_rss_4ring_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i, j;
-
- for (i = 1; i < MAX_RX_RING_NUM; i++) {
- /* free RX Ring */
- dma_free_coherent(dev->dev.parent,
- NUM_RSS_RX_DESC * sizeof(struct PDMA_rxdesc),
- ei_local->rx_ring[i],
- ei_local->phy_rx_ring[i]);
- /* free RX data */
- for (j = 0; j < NUM_RSS_RX_DESC; j++) {
- raeth_free_skb_data(ei_local->netrx_skb_data[i][j]);
- ei_local->netrx_skb_data[i][j] = NULL;
- }
- }
-}
-
-int fe_rss_2ring_init(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int skb_size;
- int i, j;
-
- skb_size = SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
- for (i = 1; i < MAX_RX_RING_NUM_2RING; i++) {
- ei_local->rx_ring[i] =
- dma_alloc_coherent(dev->dev.parent,
- NUM_RSS_RX_DESC *
- sizeof(struct PDMA_rxdesc),
- &ei_local->phy_rx_ring[i],
- GFP_ATOMIC | __GFP_ZERO);
- for (j = 0; j < NUM_RSS_RX_DESC; j++) {
- ei_local->netrx_skb_data[i][j] =
- raeth_alloc_skb_data(skb_size, GFP_KERNEL);
-
- if (!ei_local->netrx_skb_data[i][j]) {
- pr_info("rx skbuff buffer allocation failed!\n");
- goto no_rx_mem;
- }
-
- memset(&ei_local->rx_ring[i][j], 0,
- sizeof(struct PDMA_rxdesc));
- ei_local->rx_ring[i][j].rxd_info2.DDONE_bit = 0;
- ei_local->rx_ring[i][j].rxd_info2.LS0 = 0;
- ei_local->rx_ring[i][j].rxd_info2.PLEN0 =
- SET_ADMA_RX_LEN0(MAX_RX_LENGTH);
- ei_local->rx_ring[i][j].rxd_info1.PDP0 =
- dma_map_single(dev->dev.parent,
- ei_local->netrx_skb_data[i][j] +
- NET_SKB_PAD,
- MAX_RX_LENGTH, DMA_FROM_DEVICE);
- if (unlikely
- (dma_mapping_error
- (dev->dev.parent,
- ei_local->rx_ring[i][j].rxd_info1.PDP0))) {
- pr_info("[%s]dma_map_single() failed...\n",
- __func__);
- goto no_rx_mem;
- }
- }
- pr_info("\nphy_rx_ring[%d] = 0x%08x, rx_ring[%d] = 0x%p\n",
- i, (unsigned int)ei_local->phy_rx_ring[i],
- i, (void __iomem *)ei_local->rx_ring[i]);
- }
-
- sys_reg_write(RX_BASE_PTR1, phys_to_bus((u32)ei_local->phy_rx_ring[1]));
- sys_reg_write(RX_MAX_CNT1, cpu_to_le32((u32)NUM_RSS_RX_DESC));
- sys_reg_write(RX_CALC_IDX1, cpu_to_le32((u32)(NUM_RSS_RX_DESC - 1)));
- sys_reg_write(PDMA_RST_CFG, PST_DRX_IDX1);
-
- /* 1. Set RX ring1~3 to pse modes */
- SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE);
-
- /* 2. Enable non-lro multiple rx */
- SET_PDMA_NON_LRO_MULTI_EN(1); /* MRX EN */
-
- /*Hash Type*/
- SET_PDMA_RSS_IPV4_TYPE(7);
- SET_PDMA_RSS_IPV6_TYPE(7);
- /* 3. Select the size of indirection table */
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW0, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW1, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW2, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW3, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW4, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW5, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW6, 0x44444444);
- SET_PDMA_RSS_CR_VALUE(ADMA_RSS_INDR_TABLE_DW7, 0x44444444);
- /* 4. Pause */
- SET_PDMA_RSS_CFG_REQ(1);
-
- /* 5. Enable RSS */
- SET_PDMA_RSS_EN(1);
-
- /* 6. Release pause */
- SET_PDMA_RSS_CFG_REQ(0);
-
- return 0;
-
-no_rx_mem:
- return -ENOMEM;
-}
-
-void fe_rss_2ring_deinit(struct net_device *dev)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- int i, j;
-
- for (i = 1; i < MAX_RX_RING_NUM_2RING; i++) {
- /* free RX Ring */
- dma_free_coherent(dev->dev.parent,
- NUM_RSS_RX_DESC * sizeof(struct PDMA_rxdesc),
- ei_local->rx_ring[i],
- ei_local->phy_rx_ring[i]);
- /* free RX data */
- for (j = 0; j < NUM_RSS_RX_DESC; j++) {
- raeth_free_skb_data(ei_local->netrx_skb_data[i][j]);
- ei_local->netrx_skb_data[i][j] = NULL;
- }
- }
-}
-
-static inline void hw_rss_rx_desc_init(struct END_DEVICE *ei_local,
- struct PDMA_rxdesc *rx_ring,
- unsigned int rx_ring_no,
- dma_addr_t dma_addr)
-{
- rx_ring->rxd_info2.PLEN0 = MAX_RX_LENGTH;
- rx_ring->rxd_info1.PDP0 = dma_addr;
- rx_ring->rxd_info2.LS0 = 0;
- rx_ring->rxd_info2.DDONE_bit = 0;
-}
-
-static inline void __iomem *get_rx_cal_idx_reg(unsigned int rx_ring_no)
-{
- return (void __iomem *)(RAETH_RX_CALC_IDX0 + (rx_ring_no << 4));
-}
-
-int fe_rss0_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int length = 0;
- unsigned int rx_ring_no = 0, rx_ring_no_next = 0;
- unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next;
- unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM];
- unsigned int skb_size, map_size;
- /* void __iomem *rx_calc_idx_reg; */
- int rx_processed = 0;
-
- /* get cpu owner indexes of rx rings */
- rx_dma_owner_lro[0] = (ei_local->rx_calc_idx[0] + 1) % num_rx_desc;
-
- rx_ring_no = 0;
- rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no];
- rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx];
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- /* prefetch the next handling RXD */
-
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % num_rx_desc;
- skb_size =
- SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_RX_LENGTH;
-
- /* rx_ring_no_next = get_rss_rx_ring(ei_local, rx_dma_owner_lro, group); */
- rx_ring_no_next = rx_ring_no;
- rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next];
-
- rx_ring_next =
- &ei_local->rx_ring
- [rx_ring_no_next][rx_dma_owner_idx_next];
- rx_data_next =
- ei_local->netrx_skb_data
- [rx_ring_no_next][rx_dma_owner_idx_next];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_info("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- map_size,
- DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_info("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_info("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (ei_local->pseudo_dev) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_info
- ("pseudo_dev is still not initialize ");
- pr_info
- ("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (likely(rx_ring->rxd_info4.L4VLD))
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- if (IS_SPACE_AVAILABLE_HEAD(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- }
- if (IS_SPACE_AVAILABLE_TAIL(rx_skb)) {
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
- }
-#endif
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI) {
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- } else {
- netif_rx(rx_skb);
- }
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* Init RX desc. */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- dma_addr);
- ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] =
- new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
- sys_reg_write(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- /* use prefetched variable */
- rx_dma_owner_idx = rx_dma_owner_idx_next;
- rx_ring_no = rx_ring_no_next;
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- rx_ring->rxd_info1.PDP0);
- sys_reg_write(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- return (budget + 1);
-}
-
-int fe_rss1_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int length = 0;
- unsigned int rx_ring_no = 0, rx_ring_no_next = 0;
- unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next;
- unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM];
- unsigned int skb_size, map_size;
- /* void __iomem *rx_calc_idx_reg; */
- int rx_processed = 0;
-
- /* get cpu owner indexes of rx rings */
- rx_dma_owner_lro[1] = (ei_local->rx_calc_idx[1] + 1) % NUM_RSS_RX_DESC;
-
- rx_ring_no = 1;
- rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no];
- rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx];
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- /* prefetch the next handling RXD */
-
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % NUM_RSS_RX_DESC;
- skb_size =
- SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_RX_LENGTH;
-
- /* rx_ring_no_next = get_rss_rx_ring(ei_local, rx_dma_owner_lro, group); */
- rx_ring_no_next = rx_ring_no;
- rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next];
-
- rx_ring_next =
- &ei_local->rx_ring
- [rx_ring_no_next][rx_dma_owner_idx_next];
- rx_data_next =
- ei_local->netrx_skb_data
- [rx_ring_no_next][rx_dma_owner_idx_next];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_info("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- map_size,
- DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_info("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_info("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (ei_local->pseudo_dev) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_info
- ("pseudo_dev is still not initialize ");
- pr_info
- ("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (likely(rx_ring->rxd_info4.L4VLD))
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
-#endif
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI) {
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- } else {
- netif_rx(rx_skb);
- }
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* Init RX desc. */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- dma_addr);
- ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] =
- new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
- sys_reg_write(RAETH_RX_CALC_IDX1, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- /* use prefetched variable */
- rx_dma_owner_idx = rx_dma_owner_idx_next;
- rx_ring_no = rx_ring_no_next;
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- rx_ring->rxd_info1.PDP0);
- sys_reg_write(RAETH_RX_CALC_IDX1, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- return (budget + 1);
-}
-
-int fe_rss2_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int length = 0;
- unsigned int rx_ring_no = 0, rx_ring_no_next = 0;
- unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next;
- unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM];
- unsigned int skb_size, map_size;
- /* void __iomem *rx_calc_idx_reg; */
- int rx_processed = 0;
-
- /* get cpu owner indexes of rx rings */
- rx_dma_owner_lro[2] = (ei_local->rx_calc_idx[2] + 1) % NUM_RSS_RX_DESC;
-
- rx_ring_no = 2;
- rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no];
- rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx];
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- /* prefetch the next handling RXD */
-
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % NUM_RSS_RX_DESC;
- skb_size =
- SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_RX_LENGTH;
-
- /* rx_ring_no_next = get_rss_rx_ring(ei_local, rx_dma_owner_lro, group); */
- rx_ring_no_next = rx_ring_no;
- rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next];
-
- rx_ring_next =
- &ei_local->rx_ring
- [rx_ring_no_next][rx_dma_owner_idx_next];
- rx_data_next =
- ei_local->netrx_skb_data
- [rx_ring_no_next][rx_dma_owner_idx_next];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_info("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- map_size,
- DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_info("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_info("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (ei_local->pseudo_dev) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_info
- ("pseudo_dev is still not initialize ");
- pr_info
- ("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (likely(rx_ring->rxd_info4.L4VLD))
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
-#endif
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI) {
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- } else {
- netif_rx(rx_skb);
- }
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* Init RX desc. */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- dma_addr);
- ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] =
- new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
-
- sys_reg_write(RAETH_RX_CALC_IDX2, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- /* use prefetched variable */
- rx_dma_owner_idx = rx_dma_owner_idx_next;
- rx_ring_no = rx_ring_no_next;
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- rx_ring->rxd_info1.PDP0);
- sys_reg_write(RAETH_RX_CALC_IDX2, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- return (budget + 1);
-}
-
-int fe_rss3_recv(struct net_device *dev,
- struct napi_struct *napi,
- int budget)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev);
- struct PSEUDO_ADAPTER *p_ad = netdev_priv(ei_local->pseudo_dev);
- struct sk_buff *rx_skb;
- struct PDMA_rxdesc *rx_ring, *rx_ring_next;
- void *rx_data, *rx_data_next, *new_data;
- unsigned int length = 0;
- unsigned int rx_ring_no = 0, rx_ring_no_next = 0;
- unsigned int rx_dma_owner_idx, rx_dma_owner_idx_next;
- unsigned int rx_dma_owner_lro[MAX_RX_RING_NUM];
- unsigned int skb_size, map_size;
- /* void __iomem *rx_calc_idx_reg; */
- int rx_processed = 0;
-
- /* get cpu owner indexes of rx rings */
- rx_dma_owner_lro[3] = (ei_local->rx_calc_idx[3] + 1) % NUM_RSS_RX_DESC;
- rx_ring_no = 3;
- rx_dma_owner_idx = rx_dma_owner_lro[rx_ring_no];
- rx_ring = &ei_local->rx_ring[rx_ring_no][rx_dma_owner_idx];
- rx_data = ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx];
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
-
- for (;;) {
- dma_addr_t dma_addr;
-
- if ((rx_processed++ > budget) ||
- (rx_ring->rxd_info2.DDONE_bit == 0))
- break;
-
- /* prefetch the next handling RXD */
-
- rx_dma_owner_lro[rx_ring_no] =
- (rx_dma_owner_idx + 1) % NUM_RSS_RX_DESC;
- skb_size =
- SKB_DATA_ALIGN(MAX_RX_LENGTH + NET_IP_ALIGN +
- NET_SKB_PAD) +
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- map_size = MAX_RX_LENGTH;
-
- /* rx_ring_no_next = get_rss_rx_ring(ei_local, rx_dma_owner_lro, group); */
- rx_ring_no_next = rx_ring_no;
- rx_dma_owner_idx_next = rx_dma_owner_lro[rx_ring_no_next];
-
- rx_ring_next =
- &ei_local->rx_ring
- [rx_ring_no_next][rx_dma_owner_idx_next];
- rx_data_next =
- ei_local->netrx_skb_data
- [rx_ring_no_next][rx_dma_owner_idx_next];
- prefetch(rx_ring_next);
-
- /* We have to check the free memory size is big enough
- * before pass the packet to cpu
- */
- new_data = raeth_alloc_skb_data(skb_size, GFP_ATOMIC);
-
- if (unlikely(!new_data)) {
- pr_info("skb not available...\n");
- goto skb_err;
- }
-
- dma_addr = dma_map_single(dev->dev.parent,
- new_data + NET_SKB_PAD,
- map_size,
- DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(dev->dev.parent, dma_addr))) {
- pr_info("[%s]dma_map_single() failed...\n", __func__);
- raeth_free_skb_data(new_data);
- goto skb_err;
- }
-
- rx_skb = raeth_build_skb(rx_data, skb_size);
-
- if (unlikely(!rx_skb)) {
- put_page(virt_to_head_page(rx_data));
- pr_info("build_skb failed\n");
- goto skb_err;
- }
- skb_reserve(rx_skb, NET_SKB_PAD + NET_IP_ALIGN);
-
- length = rx_ring->rxd_info2.PLEN0;
- dma_unmap_single(dev->dev.parent,
- rx_ring->rxd_info1.PDP0,
- length, DMA_FROM_DEVICE);
-
- prefetch(rx_skb->data);
-
- /* skb processing */
- skb_put(rx_skb, length);
-
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2) {
- if (ei_local->pseudo_dev) {
- rx_skb->dev = ei_local->pseudo_dev;
- rx_skb->protocol =
- eth_type_trans(rx_skb,
- ei_local->pseudo_dev);
- } else {
- pr_info
- ("pseudo_dev is still not initialize ");
- pr_info
- ("but receive packet from GMAC2\n");
- }
- } else {
- rx_skb->dev = dev;
- rx_skb->protocol = eth_type_trans(rx_skb, dev);
- }
-
- /* rx checksum offload */
- if (likely(rx_ring->rxd_info4.L4VLD))
- rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- rx_skb->ip_summed = CHECKSUM_NONE;
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if (ppe_hook_rx_eth) {
- *(uint32_t *)(FOE_INFO_START_ADDR_HEAD(rx_skb)) =
- *(uint32_t *)&rx_ring->rxd_info4;
- *(uint32_t *)(FOE_INFO_START_ADDR_TAIL(rx_skb) + 2) =
- *(uint32_t *)&rx_ring->rxd_info4;
- FOE_ALG_HEAD(rx_skb) = 0;
- FOE_ALG_TAIL(rx_skb) = 0;
- FOE_MAGIC_TAG_HEAD(rx_skb) = FOE_MAGIC_GE;
- FOE_MAGIC_TAG_TAIL(rx_skb) = FOE_MAGIC_GE;
- FOE_TAG_PROTECT_HEAD(rx_skb) = TAG_PROTECT;
- FOE_TAG_PROTECT_TAIL(rx_skb) = TAG_PROTECT;
- }
-#endif
- if (ei_local->features & FE_HW_VLAN_RX) {
- if (rx_ring->rxd_info2.TAG)
- __vlan_hwaccel_put_tag(rx_skb,
- htons(ETH_P_8021Q),
- rx_ring->rxd_info3.VID);
- }
-/* ra_sw_nat_hook_rx return 1 --> continue
- * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
- */
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- if ((!ppe_hook_rx_eth) ||
- (ppe_hook_rx_eth && ppe_hook_rx_eth(rx_skb))) {
-#endif
- if (ei_local->features & FE_INT_NAPI) {
- /* napi_gro_receive(napi, rx_skb); */
- netif_receive_skb(rx_skb);
- } else {
- netif_rx(rx_skb);
- }
-
-#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
- }
-#endif
-
- if (rx_ring->rxd_info4.SP == 2) {
- p_ad->stat.rx_packets++;
- p_ad->stat.rx_bytes += length;
- } else {
- ei_local->stat.rx_packets++;
- ei_local->stat.rx_bytes += length;
- }
-
- /* Init RX desc. */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- dma_addr);
- ei_local->netrx_skb_data[rx_ring_no][rx_dma_owner_idx] =
- new_data;
-
- /* make sure that all changes to the dma ring are flushed before
- * we continue
- */
- wmb();
-
- sys_reg_write(RAETH_RX_CALC_IDX3, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- /* use prefetched variable */
- rx_dma_owner_idx = rx_dma_owner_idx_next;
- rx_ring_no = rx_ring_no_next;
- rx_ring = rx_ring_next;
- rx_data = rx_data_next;
- /* rx_calc_idx_reg = get_rx_cal_idx_reg(rx_ring_no); */
- } /* for */
-
- return rx_processed;
-
-skb_err:
- /* rx packet from GE2 */
- if (rx_ring->rxd_info4.SP == 2)
- p_ad->stat.rx_dropped++;
- else
- ei_local->stat.rx_dropped++;
-
- /* Discard the rx packet */
- hw_rss_rx_desc_init(ei_local,
- rx_ring,
- rx_ring_no,
- rx_ring->rxd_info1.PDP0);
- sys_reg_write(RAETH_RX_CALC_IDX3, rx_dma_owner_idx);
- ei_local->rx_calc_idx[rx_ring_no] = rx_dma_owner_idx;
-
- return (budget + 1);
-}
-
-int rx_rss_ring_read(struct seq_file *seq, void *v,
- struct PDMA_rxdesc *rx_ring_p)
-{
- struct PDMA_rxdesc *rx_ring;
- int i = 0;
-
- rx_ring =
- kmalloc(sizeof(struct PDMA_rxdesc) * NUM_RSS_RX_DESC, GFP_KERNEL);
- if (!rx_ring) {
- seq_puts(seq, " allocate temp rx_ring fail.\n");
- return 0;
- }
-
- for (i = 0; i < NUM_RSS_RX_DESC; i++)
- memcpy(&rx_ring[i], &rx_ring_p[i], sizeof(struct PDMA_rxdesc));
-
- for (i = 0; i < NUM_RSS_RX_DESC; i++) {
- seq_printf(seq, "%d: %08x %08x %08x %08x\n", i,
- *(int *)&rx_ring[i].rxd_info1,
- *(int *)&rx_ring[i].rxd_info2,
- *(int *)&rx_ring[i].rxd_info3,
- *(int *)&rx_ring[i].rxd_info4);
- }
-
- kfree(rx_ring);
- return 0;
-}
-
-int rss_ring1_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_rss_ring_read(seq, v, ei_local->rx_ring[1]);
-
- return 0;
-}
-
-int rss_ring2_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_rss_ring_read(seq, v, ei_local->rx_ring[2]);
-
- return 0;
-}
-
-int rss_ring3_read(struct seq_file *seq, void *v)
-{
- struct END_DEVICE *ei_local = netdev_priv(dev_raether);
-
- rx_rss_ring_read(seq, v, ei_local->rx_ring[3]);
-
- return 0;
-}
-
-static int rx_ring1_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rss_ring1_read, NULL);
-}
-
-static int rx_ring2_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rss_ring2_read, NULL);
-}
-
-static int rx_ring3_open(struct inode *inode, struct file *file)
-{
- return single_open(file, rss_ring3_read, NULL);
-}
-
-static const struct file_operations rss_ring1_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring1_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static const struct file_operations rss_ring2_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring2_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-static const struct file_operations rss_ring3_fops = {
- .owner = THIS_MODULE,
- .open = rx_ring3_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release
-};
-
-int rss_debug_proc_init(struct proc_dir_entry *proc_reg_dir)
-{
- proc_rss_ring1 =
- proc_create(PROCREG_RXRING1, 0, proc_reg_dir, &rss_ring1_fops);
- if (!proc_rss_ring1)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING1);
-
- proc_rss_ring2 =
- proc_create(PROCREG_RXRING2, 0, proc_reg_dir, &rss_ring2_fops);
- if (!proc_rss_ring2)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING2);
-
- proc_rss_ring3 =
- proc_create(PROCREG_RXRING3, 0, proc_reg_dir, &rss_ring3_fops);
- if (!proc_rss_ring3)
- pr_info("!! FAIL to create %s PROC !!\n", PROCREG_RXRING3);
-
- return 0;
-}
-EXPORT_SYMBOL(rss_debug_proc_init);
-
-void rss_debug_proc_exit(struct proc_dir_entry *proc_reg_dir)
-{
- if (proc_rss_ring1)
- remove_proc_entry(PROCREG_RXRING1, proc_reg_dir);
- if (proc_rss_ring2)
- remove_proc_entry(PROCREG_RXRING2, proc_reg_dir);
- if (proc_rss_ring3)
- remove_proc_entry(PROCREG_RXRING3, proc_reg_dir);
-}
-EXPORT_SYMBOL(rss_debug_proc_exit);
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.h
deleted file mode 100644
index 07c073f..0000000
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/raeth/raether_rss.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2016 MediaTek Inc.
- * Author: Nelson Chang <nelson.chang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef RA_RSS_H
-#define RA_RSS_H
-
-#include "raeth_reg.h"
-
-#define NUM_RSS_RX_DESC 1024
-#define MAX_RX_RING_NUM_2RING 2
-
-/******RSS define*******/
-#define PDMA_RSS_EN BIT(0)
-#define PDMA_RSS_BUSY BIT(1)
-#define PDMA_RSS_CFG_REQ BIT(2)
-#define PDMA_RSS_CFG_RDY BIT(3)
-#define PDMA_RSS_INDR_TBL_SIZE BITS(4, 6)
-#define PDMA_RSS_IPV6_TYPE BITS(8, 10)
-#define PDMA_RSS_IPV4_TYPE BITS(12, 14)
-#define PDMA_RSS_IPV6_TUPLE_EN BITS(16, 20)
-#define PDMA_RSS_IPV4_TUPLE_EN BITS(24, 28)
-
-#define PDMA_RSS_EN_OFFSET (0)
-#define PDMA_RSS_BUSY_OFFSET (1)
-#define PDMA_RSS_CFG_REQ_OFFSET (2)
-#define PDMA_RSS_CFG_RDY_OFFSET (3)
-#define PDMA_RSS_INDR_TBL_SIZE_OFFSET (4)
-#define PDMA_RSS_IPV6_TYPE_OFFSET (8)
-#define PDMA_RSS_IPV4_TYPE_OFFSET (12)
-#define PDMA_RSS_IPV6_TUPLE_EN_OFFSET (16)
-#define PDMA_RSS_IPV4_TUPLE_EN_OFFSET (24)
-
-#define SET_PDMA_RSS_EN(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_EN); \
-reg_val |= ((x) & 0x1) << PDMA_RSS_EN_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_CFG_REQ(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_CFG_REQ); \
-reg_val |= ((x) & 0x1) << PDMA_RSS_CFG_REQ_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_IPV4_TYPE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_IPV4_TYPE); \
-reg_val |= ((x) & 0x7) << PDMA_RSS_IPV4_TYPE_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_IPV6_TYPE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_IPV6_TYPE); \
-reg_val |= ((x) & 0x7) << PDMA_RSS_IPV6_TYPE_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_IPV4_TUPLE_TYPE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_IPV4_TYPE); \
-reg_val |= ((x) & 0x7) << PDMA_RSS_IPV4_TUPLE_EN_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_IPV6_TUPLE_TYPE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_IPV6_TYPE); \
-reg_val |= ((x) & 0x7) << PDMA_RSS_IPV6_TUPLE_EN_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_INDR_TBL_SIZE(x) \
-{ \
-unsigned int reg_val = sys_reg_read(ADMA_RSS_GLO_CFG); \
-reg_val &= ~(PDMA_RSS_INDR_TBL_SIZE); \
-reg_val |= ((x) & 0x7) << PDMA_RSS_INDR_TBL_SIZE_OFFSET; \
-sys_reg_write(ADMA_RSS_GLO_CFG, reg_val); \
-}
-
-#define SET_PDMA_RSS_CR_VALUE(x, y) \
-{ \
-unsigned int reg_val = y; \
-sys_reg_write(x, reg_val); \
-}
-
-#endif