blob: ef6e990f4ff6aacdee41a78723e0d83e0c0462d0 [file] [log] [blame]
From 50d41085e1f54e1cb308bd615052aaf5e317c8c5 Mon Sep 17 00:00:00 2001
From: Peter Chiu <chui-hao.chiu@mediatek.com>
Date: Wed, 28 Sep 2022 18:52:54 +0800
Subject: [PATCH 3010/3011] mt76: mt7915: drop scatter and gather frame
The scatter and gather frame may be incorrect because WED and WO may
send frames to host driver interleaved.
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
---
dma.c | 9 +++++++++
dma.h | 1 +
mt76.h | 1 +
3 files changed, 11 insertions(+)
diff --git a/dma.c b/dma.c
index a7a4538..c106ae4 100644
--- a/dma.c
+++ b/dma.c
@@ -419,6 +419,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
if (desc->ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP))
*drop = true;
+
+ if (*more || (q->flags & MT_QFLAG_WED_FRAG)) {
+ *drop = true;
+
+ if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1))
+ q->flags &= ~MT_QFLAG_WED_FRAG;
+ else
+ q->flags |= MT_QFLAG_WED_FRAG;
+ }
} else {
buf_addr = e->dma_addr[0];
e->buf = NULL;
diff --git a/dma.h b/dma.h
index 083cbca..221fcc8 100644
--- a/dma.h
+++ b/dma.h
@@ -21,6 +21,7 @@
#define MT_DMA_CTL_DROP BIT(14)
#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
+#define MT_DMA_CTL_WO BIT(8)
#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
diff --git a/mt76.h b/mt76.h
index 8011d4c..9b22551 100644
--- a/mt76.h
+++ b/mt76.h
@@ -32,6 +32,7 @@
#define MT_QFLAG_WED_RING GENMASK(1, 0)
#define MT_QFLAG_WED_TYPE GENMASK(3, 2)
#define MT_QFLAG_WED BIT(4)
+#define MT_QFLAG_WED_FRAG BIT(5)
#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
--
2.18.0