[][update pcie clk]
[Description]
Add pcie pipe clk and point it parent to xtal
[Release-log]
N/A
Change-Id: I87defd2d5764b3c616aed21cecd28b4dbad3e82e
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4691294
diff --git a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c
index 06ecdb9..66abf8f 100644
--- a/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c
+++ b/target/linux/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7986.c
@@ -535,6 +535,7 @@
GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "infra_usb_sys", 2),
GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", "infra_usb", 3),
GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_mux", 12),
+ GATE_INFRA2(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", 13),
GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", "infra_f26m_ck0", 14),
GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", "infra_133m_phck", 15),
};
@@ -666,6 +667,10 @@
return;
clk_prepare_enable(mt7986_pll_clk_data->clks[CK_APMIXED_ARMPLL]);
+ clk_prepare_enable(mt7986_top_clk_data->clks[CK_TOP_SYSAXI_SEL]);
+ clk_prepare_enable(mt7986_top_clk_data->clks[CK_TOP_SYSAPB_SEL]);
+ clk_prepare_enable(mt7986_top_clk_data->clks[CK_TOP_DRAMC_SEL]);
+ clk_prepare_enable(mt7986_top_clk_data->clks[CK_TOP_DRAMC_MD32_SEL]);
}
static void __init mtk_infracfg_init(struct device_node *node)