diff --git a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
index 494350a..277d10c 100644
--- a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
+++ b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
@@ -25,6 +25,7 @@
 enum {
 	MT79XX_IRQ_0,
 	MT79XX_IRQ_1,
+	MT79XX_IRQ_2,
 	MT79XX_IRQ_NUM,
 };
 
diff --git a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c
index 62bf593..63162c7 100644
--- a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c
+++ b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c
@@ -239,7 +239,7 @@
 		.irq_en_reg = AFE_IRQ0_MCU_CFG0,
 		.irq_en_shift = IRQ_MCU_ON_SFT,
 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ_MCU_CLR_SFT,
+		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
 	},
 	[MT79XX_IRQ_1] = {
 		.id = MT79XX_IRQ_1,
@@ -252,7 +252,20 @@
 		.irq_en_reg = AFE_IRQ1_MCU_CFG0,
 		.irq_en_shift = IRQ_MCU_ON_SFT,
 		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-		.irq_clr_shift = IRQ_MCU_CLR_SFT,
+		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
+	},
+	[MT79XX_IRQ_2] = {
+		.id = MT79XX_IRQ_2,
+		.irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
+		.irq_fs_reg = AFE_IRQ2_MCU_CFG0,
+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
+		.irq_en_reg = AFE_IRQ2_MCU_CFG0,
+		.irq_en_shift = IRQ_MCU_ON_SFT,
+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
+		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
 	},
 };
 
diff --git a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
index d55bd28..b8d2d56 100644
--- a/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
+++ b/target/linux/mediatek/files-5.4/sound/soc/mediatek/mt79xx/mt79xx-reg.h
@@ -19,6 +19,8 @@
 #define AFE_IRQ0_MCU_CFG1               0x0144
 #define AFE_IRQ1_MCU_CFG0               0x0148
 #define AFE_IRQ1_MCU_CFG1               0x014c
+#define AFE_IRQ2_MCU_CFG0               0x0150
+#define AFE_IRQ2_MCU_CFG1               0x0154
 #define ETDM_IN5_CON0                   0x13f0
 #define ETDM_IN5_CON1                   0x13f4
 #define ETDM_IN5_CON2                   0x13f8
@@ -64,7 +66,7 @@
 #define AFE_VUL0_CON0                   0x4238
 
 #define AFE_MAX_REGISTER AFE_VUL0_CON0
-#define AFE_IRQ_STATUS_BITS             0x1
+#define AFE_IRQ_STATUS_BITS             0x7
 #define AFE_IRQ_CNT_SHIFT               0
 #define AFE_IRQ_CNT_MASK	        0xffffff
 
@@ -131,9 +133,15 @@
 #define IRQ_MCU_ON_SFT                  0
 #define IRQ_MCU_ON_MASK                 0x1
 #define IRQ_MCU_ON_MASK_SFT             BIT(0)
-#define IRQ_MCU_CLR_SFT                 0
-#define IRQ_MCU_CLR_MASK                0x1
-#define IRQ_MCU_CLR_MASK_SFT            BIT(0)
+#define IRQ0_MCU_CLR_SFT                0
+#define IRQ0_MCU_CLR_MASK               0x1
+#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
+#define IRQ1_MCU_CLR_SFT                1
+#define IRQ1_MCU_CLR_MASK               0x1
+#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
+#define IRQ2_MCU_CLR_SFT                2
+#define IRQ2_MCU_CLR_MASK               0x1
+#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
 
 /* ETDM_IN5_CON2 */
 #define IN_CLK_SRC(x)                   ((x) << 10)