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filogic
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uboot
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fc809eb2faf3160842ec0db06a3ba2348ec7e3cf
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arch
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arm
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mach-versal
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include
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mach
a7acb53
xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
by Michal Simek
· Fri Jun 23 14:51:57 2023 +0200
f68ab7b
arm64: versal: Add missing prototype for initialize_tcm
by Algapally Santosh Sagar
· Fri Jun 09 03:05:30 2023 -0600
58f731a
xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
by Algapally Santosh Sagar
· Wed Mar 01 03:33:33 2023 -0700
141cbfd
arm64: versal: Define zynqmp_mmio_write() for versal
by Michal Simek
· Thu Aug 25 06:59:02 2022 -0600
3b49fbf
spi: cadence_qspi: Enable apb linear mode for apb read & write operations
by T Karthik Reddy
· Thu May 12 04:05:34 2022 -0600
3d71b2d
spi: cadence-qspi: reset qspi flash for versal platform
by T Karthik Reddy
· Thu May 12 04:05:33 2022 -0600
7f9116f
xilinx: Remove GPIO_EXTRA_HEADER selection
by Michal Simek
· Fri Feb 04 08:40:48 2022 +0100
cb8485b
soc: xilinx: versal: Add soc_xilinx_versal driver
by T Karthik Reddy
· Tue Aug 10 06:50:19 2021 -0600
0768aeb
xilinx: zynqmp: synchronize firmware call return payload
by Ibai Erkiaga
· Tue Aug 04 23:17:26 2020 +0100
7fbe9be
versal: fix versal PM ret payload size
by Ibai Erkiaga
· Thu Jul 02 00:10:58 2020 +0100
4dcacfc
common: Drop linux/bitops.h from common header
by Simon Glass
· Sun May 10 11:40:13 2020 -0600
81efd2a
arm64: xilinx: Move firmware functions from platform to driver
by Michal Simek
· Fri Oct 04 15:45:29 2019 +0200
e50c104
arm64: versal: Clean pm_api_id usage
by Michal Simek
· Fri Oct 04 15:25:18 2019 +0200
f7a7120
clk: versal: Add clock driver support
by Siva Durga Prasad Paladugu
· Sun Jun 23 12:24:57 2019 +0530
21eb5cc
arm64: versal: Enable memory mapping via DT
by Michal Simek
· Mon Apr 29 09:39:09 2019 -0700
37c2ff8
arm64: versal: Define board_late_init for versal
by Siva Durga Prasad Paladugu
· Thu Jan 31 17:28:14 2019 +0530
775aa95
arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU
by Siva Durga Prasad Paladugu
· Tue Jan 08 21:47:26 2019 +0530
4b066a1
arm64: versal: Add support for new Xilinx Versal ACAPs
by Michal Simek
· Wed Aug 22 14:55:27 2018 +0200