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git01.mediatek.com / filogic / uboot / f94b26109b51f02fcd5930cfbbc24a865e6e4e81 / arch / riscv / cpu / u-boot-spl.lds
  1. 4478727 riscv: Update alignment for some sections in linker scripts by Bin Meng · Thu Apr 13 14:20:08 2023 +0800
  2. 604a0c5 riscv: spl: Remove relocation sections by Bin Meng · Thu Apr 13 14:20:07 2023 +0800
  3. 5a9095c linker_lists: Rename sections to remove . prefix by Andrew Scull · Mon May 30 10:00:04 2022 +0000
  4. 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · Fri May 29 11:33:23 2020 +0530
  5. 55bc1bd riscv: Fix clear bss loop in the start-up code by Rick Chen · Thu Nov 14 13:52:27 2019 +0800
  6. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200