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git01.mediatek.com / filogic / uboot / f904a86c0c34d2049b7c0840b931414e3db3074f / drivers / ddr / altera
  1. f904a86 ddr: altera: sdram: Clean up set_sdr_fifo_cfg() by Marek Vasut · Sat Aug 01 20:04:33 2015 +0200
  2. 9d64f19 ddr: altera: sdram: Clean up set_sdr_static_cfg() by Marek Vasut · Sat Aug 01 20:04:19 2015 +0200
  3. 820b0d9 ddr: altera: sdram: Clean up set_sdr_addr_rw() by Marek Vasut · Sat Aug 01 19:50:56 2015 +0200
  4. 6e9af9b ddr: altera: sdram: Clean up set_sdr_dram_timing*() by Marek Vasut · Sat Aug 01 19:45:24 2015 +0200
  5. 82a2764 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() by Marek Vasut · Sat Aug 01 19:33:40 2015 +0200
  6. 724c50f ddr: altera: sdram: Clean up compute_errata_rows() part 2 by Marek Vasut · Sat Aug 01 19:20:19 2015 +0200
  7. 186880e ddr: altera: sdram: Clean up compute_errata_rows() part 1 by Marek Vasut · Sat Aug 01 18:54:34 2015 +0200
  8. 2fda506 ddr: altera: sdram: Switch to generic_hweight32() by Marek Vasut · Sat Aug 01 18:46:55 2015 +0200
  9. 98d279a ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 by Marek Vasut · Sun Jul 26 11:46:04 2015 +0200
  10. 7574c87 ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 by Marek Vasut · Sun Jul 26 11:44:54 2015 +0200
  11. 13ee438 ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 by Marek Vasut · Sun Jul 26 11:42:53 2015 +0200
  12. 4b203df ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 by Marek Vasut · Sun Jul 26 11:34:09 2015 +0200
  13. 50d7199 ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 by Marek Vasut · Sun Jul 26 11:11:28 2015 +0200
  14. c140275 ddr: altera: Minor clean up of rw_mgr_mem_handoff() by Marek Vasut · Sun Jul 26 10:59:19 2015 +0200
  15. a358127 ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() by Marek Vasut · Tue Jul 21 06:18:57 2015 +0200
  16. 2da0257 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() by Marek Vasut · Sat Jul 18 05:58:44 2015 +0200
  17. adbaa2d ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() by Marek Vasut · Tue Jul 21 06:00:36 2015 +0200
  18. c67d962 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 by Marek Vasut · Tue Jul 21 05:57:11 2015 +0200
  19. bc773a1 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 by Marek Vasut · Tue Jul 21 05:54:39 2015 +0200
  20. 0b97c42 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 by Marek Vasut · Tue Jul 21 05:43:37 2015 +0200
  21. 2595b24 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 by Marek Vasut · Tue Jul 21 05:33:49 2015 +0200
  22. fc2ec8f ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 by Marek Vasut · Tue Jul 21 05:32:49 2015 +0200
  23. 1bb221e ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 by Marek Vasut · Tue Jul 21 05:29:05 2015 +0200
  24. 4e79b0a ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 by Marek Vasut · Tue Jul 21 05:26:58 2015 +0200
  25. affbc89 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 by Marek Vasut · Tue Jul 21 05:00:42 2015 +0200
  26. 9cdbb96 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 by Marek Vasut · Tue Jul 21 04:27:32 2015 +0200
  27. d29f804 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 by Marek Vasut · Sat Jul 18 20:44:28 2015 +0200
  28. dfed1e6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 by Marek Vasut · Sat Jul 18 20:42:27 2015 +0200
  29. b69c247 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 by Marek Vasut · Sat Jul 18 20:34:00 2015 +0200
  30. f1b8f71 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 by Marek Vasut · Sat Jul 18 19:57:12 2015 +0200
  31. 89feb50 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 by Marek Vasut · Sat Jul 18 19:46:26 2015 +0200
  32. aa0e6e1 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 by Marek Vasut · Sat Jul 18 19:18:06 2015 +0200
  33. ca8ea37 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 by Marek Vasut · Sat Jul 18 08:01:45 2015 +0200
  34. 85cd4d7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 by Marek Vasut · Mon Jul 13 02:48:34 2015 +0200
  35. e624caf ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 by Marek Vasut · Mon Jul 13 02:38:15 2015 +0200
  36. b20a506 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 by Marek Vasut · Mon Jul 13 02:11:02 2015 +0200
  37. 4a78cc7 ddr: altera: Clean up rw_mgr_mem_calibrate_writes() by Marek Vasut · Sat Jul 18 07:23:25 2015 +0200
  38. 656002e ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 by Marek Vasut · Mon Jul 20 03:26:05 2015 +0200
  39. 50a780f ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 by Marek Vasut · Sun Jul 19 07:57:28 2015 +0200
  40. 28957f3 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 by Marek Vasut · Sun Jul 19 07:51:17 2015 +0200
  41. c6c1fe7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 by Marek Vasut · Sun Jul 19 07:48:58 2015 +0200
  42. a005c77 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 by Marek Vasut · Sun Jul 19 07:44:21 2015 +0200
  43. a50d5d7 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() by Marek Vasut · Sun Jul 19 07:35:36 2015 +0200
  44. ec4bbd3 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 by Marek Vasut · Mon Jul 20 09:11:09 2015 +0200
  45. 28dbf12 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 by Marek Vasut · Mon Jul 20 09:20:42 2015 +0200
  46. 59729a6 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 by Marek Vasut · Mon Jul 20 09:20:20 2015 +0200
  47. 6ff36b7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 by Marek Vasut · Sun Jul 19 07:27:06 2015 +0200
  48. deebda8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 by Marek Vasut · Sun Jul 19 07:03:15 2015 +0200
  49. 970539d ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 by Marek Vasut · Sun Jul 19 07:00:26 2015 +0200
  50. 4896bcc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 by Marek Vasut · Sun Jul 19 02:42:21 2015 +0200
  51. 088eb21 ddr: altera: Clean up find_vfifo_read() by Marek Vasut · Sun Jul 19 06:45:43 2015 +0200
  52. 42e43ab ddr: altera: Clean up rw_mgr_*_vfifo() part 2 by Marek Vasut · Sun Jul 19 06:37:51 2015 +0200
  53. 1c9f25b ddr: altera: Clean up rw_mgr_*_vfifo() part 1 by Marek Vasut · Sun Jul 19 06:25:27 2015 +0200
  54. 6394ef5 ddr: altera: Clean up sdr_*_phase() part 10 by Marek Vasut · Sun Jul 19 06:04:00 2015 +0200
  55. 6eff803 ddr: altera: Clean up sdr_*_phase() part 9 by Marek Vasut · Sun Jul 19 05:48:30 2015 +0200
  56. f260eec ddr: altera: Clean up sdr_*_phase() part 8 by Marek Vasut · Sun Jul 19 05:42:43 2015 +0200
  57. 2700b9c ddr: altera: Clean up sdr_*_phase() part 7 by Marek Vasut · Sun Jul 19 05:40:06 2015 +0200
  58. 6da8ae4 ddr: altera: Clean up sdr_*_phase() part 6 by Marek Vasut · Sun Jul 19 05:35:40 2015 +0200
  59. f2b02d4 ddr: altera: Clean up sdr_*_phase() part 5 by Marek Vasut · Sun Jul 19 05:26:49 2015 +0200
  60. b148ebe ddr: altera: Clean up sdr_*_phase() part 4 by Marek Vasut · Sun Jul 19 05:01:12 2015 +0200
  61. 434f639 ddr: altera: Clean up sdr_*_phase() part 3 by Marek Vasut · Sun Jul 19 04:37:08 2015 +0200
  62. 6ff1c85 ddr: altera: Clean up sdr_*_phase() part 2 by Marek Vasut · Sun Jul 19 04:34:12 2015 +0200
  63. 139ad79 ddr: altera: Clean up sdr_*_phase() part 1 by Marek Vasut · Sun Jul 19 04:29:21 2015 +0200
  64. fea03c3 ddr: altera: Clean up sdr_find_window_centre() part 3 by Marek Vasut · Sun Jul 19 04:14:32 2015 +0200
  65. ea4c4bb ddr: altera: Clean up sdr_find_window_centre() part 2 by Marek Vasut · Sun Jul 19 04:04:33 2015 +0200
  66. d996e80 ddr: altera: Clean up sdr_find_window_centre() part 1 by Marek Vasut · Sun Jul 19 02:56:59 2015 +0200
  67. 3aa19dc ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 by Marek Vasut · Sat Jul 18 04:28:42 2015 +0200
  68. 1beb243 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 by Marek Vasut · Sat Jul 18 04:24:49 2015 +0200
  69. faf820a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 by Marek Vasut · Sat Jul 18 04:20:26 2015 +0200
  70. bb9a5f7 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 by Marek Vasut · Sat Jul 18 04:16:45 2015 +0200
  71. 55c4d69 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() by Marek Vasut · Sat Jul 18 03:55:07 2015 +0200
  72. fcef833 ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() by Marek Vasut · Sat Jul 18 03:36:09 2015 +0200
  73. 6a75278 ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup by Marek Vasut · Sat Jul 18 03:34:22 2015 +0200
  74. 349ea3e ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 03:10:31 2015 +0200
  75. feb5e65 ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:57:32 2015 +0200
  76. 6ca5b96 ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() by Marek Vasut · Sat Jul 18 02:46:56 2015 +0200
  77. 912d43e ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 by Marek Vasut · Sat Jul 18 03:15:34 2015 +0200
  78. e42fcea ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 by Marek Vasut · Fri Jul 17 04:24:18 2015 +0200
  79. 0d9f9d5 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 by Marek Vasut · Fri Jul 17 03:54:34 2015 +0200
  80. f2a4bda ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 by Marek Vasut · Fri Jul 17 03:50:17 2015 +0200
  81. d7f4915 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 by Marek Vasut · Fri Jul 17 03:44:26 2015 +0200
  82. aff1a5f ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 by Marek Vasut · Fri Jul 17 03:22:31 2015 +0200
  83. c27ea62 ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 by Marek Vasut · Fri Jul 17 03:16:45 2015 +0200
  84. 1185e22 ddr: altera: Minor clean up of rw_mgr_mem_initialize() by Marek Vasut · Sun Jul 26 10:57:06 2015 +0200
  85. d9fcf9a ddr: altera: Internal mem_calibrate() cleanup part 6 by Marek Vasut · Mon Jul 20 04:34:51 2015 +0200
  86. 0568f22 ddr: altera: Internal mem_calibrate() cleanup part 5 by Marek Vasut · Fri Jul 17 02:50:56 2015 +0200
  87. fc38d5c ddr: altera: Internal mem_calibrate() cleanup part 4 by Marek Vasut · Fri Jul 17 02:40:21 2015 +0200
  88. 6db5573 ddr: altera: Internal mem_calibrate() cleanup part 3 by Marek Vasut · Fri Jul 17 02:38:51 2015 +0200
  89. f04045f ddr: altera: Internal mem_calibrate() cleanup part 2 by Marek Vasut · Fri Jul 17 02:31:04 2015 +0200
  90. d6f2879 ddr: altera: Internal mem_calibrate() cleanup part 1 by Marek Vasut · Fri Jul 17 02:21:47 2015 +0200
  91. b984ee8 ddr: altera: Trivial mem_calibrate() indent cleanup by Marek Vasut · Fri Jul 17 02:07:12 2015 +0200
  92. 60daef8 ddr: altera: Minor clean up of mem_skip_calibrate() by Marek Vasut · Sun Jul 26 10:54:15 2015 +0200
  93. 575029d ddr: altera: Clean up set_rank_and_odt_mask() part 3 by Marek Vasut · Mon Jul 20 08:15:57 2015 +0200
  94. 9252308 ddr: altera: Clean up set_rank_and_odt_mask() part 2 by Marek Vasut · Mon Jul 20 08:09:05 2015 +0200
  95. 0b5e257 ddr: altera: Clean up set_rank_and_odt_mask() part 1 by Marek Vasut · Mon Jul 20 08:03:11 2015 +0200
  96. be333bc ddr: altera: Clean up mem_precharge_and_activate() by Marek Vasut · Mon Jul 20 07:33:33 2015 +0200
  97. 0f0840d ddr: altera: Clean up mem_config() by Marek Vasut · Fri Jul 17 01:57:41 2015 +0200
  98. fe5aa45 ddr: altera: Clean up phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:36:32 2015 +0200
  99. 092a1ef ddr: altera: Clean up run_mem_calibrate() by Marek Vasut · Fri Jul 17 01:20:21 2015 +0200
  100. acaaff7 ddr: altera: Rename initialize() to phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:12:07 2015 +0200