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git01.mediatek.com
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filogic
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uboot
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f7521dead1f0beb056123f95fa718296482f245a
/
drivers
/
clk
/
sifive
/
fu540-prci.c
e848dba
clk: sifive: fu540-prci: Release ethernet clock reset
by Pragnesh Patel
· Fri May 29 11:33:31 2020 +0530
1790bce
clk: sifive: fu540-prci: Add ddr clock initialization
by Pragnesh Patel
· Fri May 29 11:33:30 2020 +0530
54ce0e0
clk: sifive: fu540-prci: Add clock enable and disable ops
by Pragnesh Patel
· Fri May 29 11:33:29 2020 +0530
dbd7954
common: Drop linux/delay.h from common header
by Simon Glass
· Sun May 10 11:40:11 2020 -0600
d66c5f7
dm: core: Require users of devres to include the header
by Simon Glass
· Mon Feb 03 07:36:15 2020 -0700
9a99add
clk: sifive: Sync-up main driver with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:21 2019 +0000
83d5b50
clk: sifive: Sync-up DT bindings header with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:15 2019 +0000
6f7b5a2
clk: sifive: Sync-up WRPLL library with upstream Linux
by Anup Patel
· Tue Jun 25 06:31:08 2019 +0000
00a156d
clk: sifive: Factor-out PLL library as separate module
by Anup Patel
· Tue Jun 25 06:31:02 2019 +0000
72be986
clk: sifive: fu540-prci: Change include order
by Jagan Teki
· Wed May 08 19:52:18 2019 +0530
42fdf08
clk: Add SiFive FU540 PRCI clock driver
by Anup Patel
· Mon Feb 25 08:14:49 2019 +0000