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git01.mediatek.com / filogic / uboot / f716943069c0ee157a1410c58b7b473f98b62aad / drivers / clk / altera / clk-agilex.c
  1. 9579301 clk: agilex: Additional membus writes for HPS PLL by Chee Hong Ang · Fri Jul 10 20:55:23 2020 +0800
  2. 2d94ee6 clk: agilex: Handle clock configuration differently in SPL and U-Boot proper by Chee Hong Ang · Fri Jul 10 20:55:22 2020 +0800
  3. 7609220 clk: agilex: Add clock enable support by Ley Foon Tan · Fri Jul 10 20:55:21 2020 +0800
  4. f94b0fd clk: agilex: Add NAND clock support by Ley Foon Tan · Fri Jul 10 20:55:20 2020 +0800
  5. a89b4de treewide: convert devfdt_get_addr() to dev_read_addr() by Masahiro Yamada · Fri Jul 17 14:36:48 2020 +0900
  6. 5a9ecb2 Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" by Tom Rini · Fri Jul 24 08:42:06 2020 -0400
  7. a831cef treewide: convert devfdt_get_addr() to dev_read_addr() by Masahiro Yamada · Fri Jul 17 14:36:48 2020 +0900
  8. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  9. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  10. ef5458f clk: agilex: Add clock driver for Agilex by Ley Foon Tan · Wed Nov 27 15:55:22 2019 +0800