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git01.mediatek.com / filogic / uboot / f5ff42940083ecb6c281ac13f72640213813373c / arch / x86 / dts / link.dts
  1. 268eefd x86: ivybridge: Implement SDRAM init by Simon Glass · Wed Nov 12 22:42:28 2014 -0700
  2. 9a44768 x86: chromebook_link: Enable GPIO support by Simon Glass · Wed Nov 12 22:42:25 2014 -0700
  3. 0c84eec x86: dts: Add microcode updates for ivybridge CPU by Simon Glass · Wed Nov 12 22:42:22 2014 -0700
  4. dcfac35 x86: ivybridge: Add early LPC init so that serial works by Simon Glass · Wed Nov 12 22:42:15 2014 -0700
  5. 1fad146 dm: x86: dts: Add additional info to the serial port node by Simon Glass · Fri Oct 10 07:49:19 2014 -0600
  6. e4e5627 x86: Add device tree information for Chrome OS EC by Simon Glass · Fri Oct 10 07:30:13 2014 -0600
  7. 884ef15 dts: move device tree sources to arch/$(ARCH)/dts/ by Masahiro Yamada · Wed Feb 05 11:28:26 2014 +0900[Renamed from board/chromebook-x86/dts/link.dts]
  8. ec7fbf5 Coding Style cleanup: replace leading SPACEs by TABs by Wolfgang Denk · Fri Oct 04 17:43:24 2013 +0200
  9. 3f972cc dt: don't use ARCH_CPU_DTS by Stephen Warren · Wed Jul 24 10:09:20 2013 -0700
  10. 87323ed x86: Add FDT SPI node for link by Simon Glass · Mon Mar 11 06:08:10 2013 +0000
  11. f88ab16 x86: Adjust link device tree include file by Simon Glass · Thu Feb 28 19:26:17 2013 +0000
  12. 791f61b x86: fdt: Create basic .dtsi file for coreboot by Simon Glass · Mon Dec 03 13:56:51 2012 +0000