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git01.mediatek.com / filogic / uboot / f56b4d4f3f2472d55c9cfda0d1cca112f80feaef / drivers / clk / sunxi / clk_h6_r.c
  1. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  2. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  3. 8443650 clk: sunxi: Store the array sizes in the CCU descriptor by Samuel Holland · Mon May 09 00:29:31 2022 -0500
  4. 2d1864f clk: sunxi: add and use dummy gate clocks by Andre Przywara · Thu May 05 01:25:43 2022 +0100
  5. fdad831 clk: sunxi: h6_r: Correct the driver name by Samuel Holland · Sat Apr 23 16:07:16 2022 -0500
  6. f7d4954 clk: sunxi: Add drivers for A31 and H6 PRCM CCUs by Samuel Holland · Sun Sep 12 09:47:25 2021 -0500