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git01.mediatek.com / filogic / uboot / f23e481cf7ad43d88582d80f5147ff33fd97d0ad / board / stxssa / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  3. 0abad32 FSL DDR: Convert STXSSA to new DDR code. by Kumar Gala · Wed Aug 27 01:04:07 2008 -0500