Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f17d43db21ef77888e98c4f660b02d53b57535f4 / drivers / rng / meson-rng.c
  1. e1c56f3 clk: Add clk_get_by_name_optional by Sean Anderson · Sat Jan 15 15:52:47 2022 -0500
  2. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  3. aad29ae dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · Thu Dec 03 16:55:21 2020 -0700
  4. fa20e93 dm: treewide: Rename dev_get_platdata() to dev_get_plat() by Simon Glass · Thu Dec 03 16:55:20 2020 -0700
  5. 71fa5b4 dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · Thu Dec 03 16:55:18 2020 -0700
  6. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  7. e733052 rng: meson: make core clock optional by Neil Armstrong · Fri Sep 25 09:19:20 2020 +0200
  8. 009d4a7 drivers/rng: add Amlogic hardware RNG driver by Heinrich Schuchardt · Sun Feb 02 19:52:04 2020 +0100