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git01.mediatek.com / filogic / uboot / f013a3aea1e5462517dbc175ff80ff0a39df7e16 / board / altera / socfpga / pll_config.h
  1. b1194c2 arm: socfpga: spl: update peripheral pll for dev kit by Dinh Nguyen · Wed Apr 15 16:44:33 2015 -0500
  2. 3debe33 arm: socfpga: Sync Cyclone V DK PLL configuration by Marek Vasut · Tue Dec 30 19:41:17 2014 +0100
  3. 43dca1e arm: socfpga: clock: Add missing stubs into board file by Marek Vasut · Sat Sep 13 08:16:49 2014 +0200
  4. cb35060 socfpga: Adding Clock Manager driver by Chin Liang See · Tue Mar 04 22:13:53 2014 -0600