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git01.mediatek.com / filogic / uboot / ed9342890af6ea52c98bde0a7f5c6313e7232b80 / drivers / mmc / zynq_sdhci.c
  1. 8bc7817 zynq: sdhci: Define max clock by macro by Michal Simek · Tue Sep 29 01:27:13 2015 +0200
  2. 366b24f of: clean up OF_CONTROL ifdef conditionals by Masahiro Yamada · Wed Aug 12 07:31:55 2015 +0900
  3. 5fd3edd mmc: remove the MMC_MODE_HC flag by Rob Herring · Mon Mar 23 17:56:59 2015 -0500
  4. 049e003 zynqmp: sdhci: Remove the quirk SDHCI_QUIRK_NO_CD by Siva Durga Prasad Paladugu · Tue Jul 08 15:31:04 2014 +0530
  5. 384081a mmc: zynq: Use phys_addr_t for addresses by Michal Simek · Wed Jan 14 16:11:47 2015 +0100
  6. c57ba04 mmc: zynq: Add OF initialization support by Michal Simek · Mon Feb 24 11:16:31 2014 +0100
  7. 0d6891b mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1B by Siva Durga Prasad Paladugu · Wed Jan 22 09:17:09 2014 +0100
  8. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  9. 0dd222b mmc: Add support for Xilinx Zynq sdhci controller by Michal Simek · Mon Apr 22 14:56:49 2013 +0200