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git01.mediatek.com / filogic / uboot / ec4fe263db1fead5806556d30d3237ea56f8ce87 / arch / arm / cpu / armv7 / mx6 / ddr.c
  1. ec4fe26 mx6: ddr: add routine to return DDR calibration data by Eric Nelson · 8 years ago
  2. a09d68a mx6: ddr: pass mx6_ddr_sysinfo to calibration routines by Eric Nelson · 8 years ago
  3. 4285a53 mx6: ddr: allow 32 cycles for DQS gating calibration by Eric Nelson · 8 years ago
  4. cb3c121 mx6: ddr: Allow changing REFSEL and REFR fields by Fabio Estevam · 8 years ago
  5. 9dba13b imx: mx6: ddr: support i.MX6D/QPlus by Peng Fan · 9 years ago
  6. 6861c5a imx: mx6: use simpler runtime cpu dection macros by Peng Fan · 9 years ago
  7. 2302357 arm: imx6: Switch DDR3 calibration to wait_for_bit() by Marek Vasut · 9 years ago
  8. ab257ed arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL by Marek Vasut · 9 years ago
  9. 4648332 imx: ddr: drop duplicated debug info by Peng Fan · 9 years ago
  10. b96b74c Revert "imx: mx6: ddr correct tRFC and tXS" by Peng Fan · 9 years ago
  11. da7ada0 imx: mx6: ddr: add LPDDR2 support by Peng Fan · 9 years ago
  12. 77e8695 imx: mx6: ddr init MMDC according to ddr_type by Peng Fan · 9 years ago
  13. d226fac imx: mx6: ddr add dram io configuration and header file for i.MX6SL by Peng Fan · 9 years ago
  14. 6b43bbd imx: mx6: ddr correct tRFC and tXS by Peng Fan · 9 years ago
  15. 1b81b06 imx: mx6: ddr no support MMDC1 for i.MX6SL by Peng Fan · 9 years ago
  16. 98f11a1 imx:mx6ul add dram spl configuration and header file by Peng Fan · 9 years ago
  17. 591fe97 arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified by Tim Harvey · 10 years ago
  18. a2534ba arm: mx6: ddr3: Remove dead code by Nikolay Dimitrov · 10 years ago
  19. 99c25ff arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations by Nikolay Dimitrov · 10 years ago
  20. fe1723f arm: mx6: ddr: add pd_fast_exit flag to system information by Tim Harvey · 10 years ago
  21. 2ecdd02 imx:mx6sx add dram io configure for mx6sx by Peng Fan · 10 years ago
  22. b62b39b cosmetic: replace MIN, MAX with min, max by Masahiro Yamada · 10 years ago
  23. 4a50ec2 arm: mx6: ddr: fix cs0_end calculation by Nikita Kiryanov · 10 years ago
  24. a810c95 arm: mx6: ddr: configure MMDC for slow_pd by Nikita Kiryanov · 10 years ago
  25. 6816f71 arm: mx6: ddr: do not write into reserved bit by Nikita Kiryanov · 10 years ago
  26. c475346 arm: mx6: ddr: cleanup by Nikita Kiryanov · 10 years ago
  27. 4a46360 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices by Marek Vasut · 10 years ago
  28. 8ab871b mx6: add mmdc configuration for MX6Q/MX6DL by Tim Harvey · 11 years ago