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git01.mediatek.com / filogic / uboot / e8a72791b4f8d7f215c8d61b1cca5387ed917749 / board / freescale / imx8ulp_evk / lpddr4_timing_266.c
  1. 4d23115 imx8ulp_evk: disable overflow of port0 for LPAV by Peng Fan · Tue Jan 31 16:42:33 2023 +0800
  2. 144e2b3 imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun by Ye Li · Tue Jan 31 16:42:32 2023 +0800
  3. 4cdb3a3 imx: imx8ulp: add ND/LD clock by Peng Fan · Wed Apr 06 14:30:12 2022 +0800