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git01.mediatek.com / filogic / uboot / e565bd41b6cfce7698f225d38407841a06baad5d / drivers / clk / sifive
  1. e1ff6eb sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · Wed Jul 29 02:36:13 2020 -0700
  2. 9158b39 fu540: prci: use common reset indexes defined in binding header by Sagar Shrikant Kadam · Wed Jul 29 02:36:11 2020 -0700
  3. e848dba clk: sifive: fu540-prci: Release ethernet clock reset by Pragnesh Patel · Fri May 29 11:33:31 2020 +0530
  4. 1790bce clk: sifive: fu540-prci: Add ddr clock initialization by Pragnesh Patel · Fri May 29 11:33:30 2020 +0530
  5. 54ce0e0 clk: sifive: fu540-prci: Add clock enable and disable ops by Pragnesh Patel · Fri May 29 11:33:29 2020 +0530
  6. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  7. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  8. 6e9ff1a clk: sifive: Drop GEMGXL clock driver by Anup Patel · Tue Jun 25 06:31:30 2019 +0000
  9. 9a99add clk: sifive: Sync-up main driver with upstream Linux by Anup Patel · Tue Jun 25 06:31:21 2019 +0000
  10. 83d5b50 clk: sifive: Sync-up DT bindings header with upstream Linux by Anup Patel · Tue Jun 25 06:31:15 2019 +0000
  11. 6f7b5a2 clk: sifive: Sync-up WRPLL library with upstream Linux by Anup Patel · Tue Jun 25 06:31:08 2019 +0000
  12. 00a156d clk: sifive: Factor-out PLL library as separate module by Anup Patel · Tue Jun 25 06:31:02 2019 +0000
  13. eb195bd clk: sifive: Add clock driver for GEMGXL MGMT by Bin Meng · Wed May 22 00:09:44 2019 -0700
  14. 72be986 clk: sifive: fu540-prci: Change include order by Jagan Teki · Wed May 08 19:52:18 2019 +0530
  15. 42fdf08 clk: Add SiFive FU540 PRCI clock driver by Anup Patel · Mon Feb 25 08:14:49 2019 +0000