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git01.mediatek.com / filogic / uboot / e55fb906f1194bc5f8f764f67d16cc1590f97ea7 / drivers / clk / sunxi / clk_sunxi.c
  1. 934d0f5 clk: sunxi: Add support for the D1 CCU by Samuel Holland · Sat Apr 30 22:38:37 2022 -0500
  2. 86b561c reset: sunxi: Reuse the platform data from the clock driver by Samuel Holland · Mon May 09 00:29:37 2022 -0500
  3. 9031532 clk: sunxi: Convert driver private data to platform data by Samuel Holland · Mon May 09 00:29:35 2022 -0500
  4. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  5. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  6. a496907 clk: sunxi: Prevent out-of-bounds gate array access by Samuel Holland · Mon May 09 00:29:32 2022 -0500
  7. 2d1864f clk: sunxi: add and use dummy gate clocks by Andre Przywara · Thu May 05 01:25:43 2022 +0100
  8. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  9. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  10. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  11. 030bab8 sunxi: clk: enable clk and reset for CCU devices by Andre Przywara · Tue Jan 29 15:54:08 2019 +0000
  12. 1d150b4 clk: Add Allwinner A64 CLK driver by Jagan Teki · Sat Dec 22 21:32:49 2018 +0530