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git01.mediatek.com / filogic / uboot / e3e812182b0abf7a167ce2dbb0c562a96863ecaa / drivers / clk / clk_versal.c
  1. aa12d51 clk: versal: Fix watchdog clock issue by T Karthik Reddy · Wed Apr 08 21:34:54 2020 -0600
  2. 5986efc versal: drivers: clk: Fix invalid clock name queries by Rajan Vaja · Thu Jan 16 03:55:05 2020 -0800
  3. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  4. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  5. 142fb5b arm64: versal: Rename versal_pm_request to xilinx_pm_request by Michal Simek · Fri Oct 04 15:52:43 2019 +0200
  6. e50c104 arm64: versal: Clean pm_api_id usage by Michal Simek · Fri Oct 04 15:25:18 2019 +0200
  7. f7a7120 clk: versal: Add clock driver support by Siva Durga Prasad Paladugu · Sun Jun 23 12:24:57 2019 +0530