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git01.mediatek.com / filogic / uboot / e32b06659e3588ff3eec7578b86bb1f0ac4e18c0 / drivers / ddr / marvell / a38x / ddr3_training_db.c
  1. e042270 ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit by Moti Buskila · Fri Feb 19 17:11:20 2021 +0100
  2. ac8bfb1 mv_ddr: ddr3: fix tRAS timimg parameter by Chris Packham · Fri Mar 01 10:11:13 2019 +1300
  3. 4bf81db ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02 by Chris Packham · Mon Dec 03 14:26:49 2018 +1300
  4. 1a07d21 ARM: mvebu: a38x: sync ddr training code with upstream by Chris Packham · Thu May 10 13:28:29 2018 +1200
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. 5450f0c ddr: marvell: update ddr controller init and freq by Chris Packham · Thu Jan 18 17:16:10 2018 +1300
  7. 5ffceb8 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr by Stefan Roese · Thu Mar 26 15:36:56 2015 +0100