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git01.mediatek.com / filogic / uboot / debdf8abb1e3df4246221543dd79469a82121c1e / arch / arm / mach-exynos / dmc_init_ddr3.c
  1. bb4dd96 global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* by Tom Rini · Wed Nov 16 13:10:37 2022 -0500
  2. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  3. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  4. 259b1fb Fix spelling of "resetting". by Vagrant Cascadian · Sun Oct 23 20:45:19 2016 -0700
  5. 401aec0 arm: exynos: clean up checkpatch issues by Minkyu Kang · Thu Oct 22 14:51:58 2015 +0900
  6. 74f8486 ARM: exynos: move SoC sources to mach-exynos by Thomas Abraham · Mon Aug 03 17:58:00 2015 +0530[Renamed from arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c]
  7. 8949456 Exynos5: ddr3: Choose between single or double channel config by Akshay Saraswat · Thu Nov 13 22:38:20 2014 +0530
  8. 0f4798c DMC: Exynos5: Enable update mode for DREX controller by Alim Akhtar · Thu Nov 13 22:38:18 2014 +0530
  9. 8a806e3 Exynos5420: DMC: Add software read leveling by Akshay Saraswat · Mon May 26 19:20:08 2014 +0530
  10. 70fa804 DMC: exynos5420: Gate CLKM to when reading PHY_CON13 by Doug Anderson · Mon May 26 19:19:05 2014 +0530
  11. 8e37c8a Exynos5420: Remove code for enabling read leveling by Akshay Saraswat · Mon May 26 19:18:06 2014 +0530
  12. 24c3e95 Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init by Akshay Saraswat · Mon May 26 19:17:03 2014 +0530
  13. 2d7f08c Exynos5420: Add DDR3 initialization for 5420 by Rajeshwari Birje · Thu Dec 26 09:44:22 2013 +0530
  14. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  15. bed2442 EXYNOS: Move files from board/samsung to arch/arm by Rajeshwari Shinde · Thu Jul 04 12:29:17 2013 +0530[Renamed (92%) from board/samsung/smdk5250/dmc_init_ddr3.c]
  16. 6558d27 Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0 by Rajeshwari Shinde · Tue Jul 03 20:02:56 2012 +0000