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git01.mediatek.com / filogic / uboot / dd1cd7080fd502441844ed375dffefff55352a98 / arch / riscv / cpu / fu540
  1. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  2. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · Tue Aug 18 01:09:20 2020 -0700
  3. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · Mon Aug 03 23:09:49 2020 +0200
  4. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · Sun Aug 02 23:09:04 2020 -0700
  5. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  6. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · Wed Jul 15 15:39:00 2020 +0530
  7. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  8. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  9. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530