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git01.mediatek.com / filogic / uboot / d8158f918b83d204b1966abe40cc41f47a23d5bc / arch / arm / cpu / armv7 / socfpga / clock_manager.c
  1. 5c46446 arm: socfpga: Add DW master SPI clock to clock_manager.c by Stefan Roese · Fri Nov 07 13:50:29 2014 +0100
  2. 43e9c40 arm: socfpga: clock: Sync with reference code by Marek Vasut · Tue Sep 16 19:54:32 2014 +0200
  3. e0098b37 arm: socfpga: clock: Clean up bit definitions by Marek Vasut · Tue Sep 16 17:21:00 2014 +0200
  4. 42780af arm: socfpga: clock: Trim down code duplication by Marek Vasut · Sat Sep 13 08:27:16 2014 +0200
  5. 7c8d5a6 arm: socfpga: clock: Add code to read clock configuration by Pavel Machek · Mon Sep 08 14:08:45 2014 +0200
  6. e5353fd arm: socfpga: clock: Drop nonsense inlining from clock manager code by Marek Vasut · Mon Sep 08 14:08:45 2014 +0200
  7. 112cb0d socfpga: Fix SOCFPGA build error for Altera dev kit by Chin Liang See · Tue Jul 22 04:28:35 2014 -0500
  8. 91c2f8f socfpga: fix clock manager register definition by Pavel Machek · Sat Jul 19 23:57:59 2014 +0200
  9. cb35060 socfpga: Adding Clock Manager driver by Chin Liang See · Tue Mar 04 22:13:53 2014 -0600