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git01.mediatek.com / filogic / uboot / d8158f918b83d204b1966abe40cc41f47a23d5bc / arch / arm / cpu / armv7 / mx6 / ddr.c
  1. b62b39b cosmetic: replace MIN, MAX with min, max by Masahiro Yamada · Thu Sep 18 13:28:06 2014 +0900
  2. 4a50ec2 arm: mx6: ddr: fix cs0_end calculation by Nikita Kiryanov · Wed Aug 20 15:08:58 2014 +0300
  3. a810c95 arm: mx6: ddr: configure MMDC for slow_pd by Nikita Kiryanov · Wed Aug 20 15:08:57 2014 +0300
  4. 6816f71 arm: mx6: ddr: do not write into reserved bit by Nikita Kiryanov · Wed Aug 20 15:08:56 2014 +0300
  5. c475346 arm: mx6: ddr: cleanup by Nikita Kiryanov · Sun Sep 07 18:58:11 2014 +0300
  6. 4a46360 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices by Marek Vasut · Mon Aug 04 01:47:10 2014 +0200
  7. 8ab871b mx6: add mmdc configuration for MX6Q/MX6DL by Tim Harvey · Mon Jun 02 16:13:23 2014 -0700