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git01.mediatek.com / filogic / uboot / d6a8288829a4edb6465e85fb76a5e03efd01cb4b / board / stx / stxssa / ddr.c
  1. c68e86c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board by Kumar Gala · Mon Jan 31 22:18:47 2011 -0600
  2. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  3. dd67ddc stx: create common vendor/board hierarchy for STx boards by Alex Dubov · Fri Aug 07 15:28:32 2009 +1000[Renamed from board/stxssa/ddr.c]
  4. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  5. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  6. 0abad32 FSL DDR: Convert STXSSA to new DDR code. by Kumar Gala · Wed Aug 27 01:04:07 2008 -0500