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git01.mediatek.com / filogic / uboot / d66c5f7177cb5c8f218f59bdfe5ef39c1214ba67 / drivers / clk / sifive
  1. d66c5f7 dm: core: Require users of devres to include the header by Simon Glass · Mon Feb 03 07:36:15 2020 -0700
  2. 6e9ff1a clk: sifive: Drop GEMGXL clock driver by Anup Patel · Tue Jun 25 06:31:30 2019 +0000
  3. 9a99add clk: sifive: Sync-up main driver with upstream Linux by Anup Patel · Tue Jun 25 06:31:21 2019 +0000
  4. 83d5b50 clk: sifive: Sync-up DT bindings header with upstream Linux by Anup Patel · Tue Jun 25 06:31:15 2019 +0000
  5. 6f7b5a2 clk: sifive: Sync-up WRPLL library with upstream Linux by Anup Patel · Tue Jun 25 06:31:08 2019 +0000
  6. 00a156d clk: sifive: Factor-out PLL library as separate module by Anup Patel · Tue Jun 25 06:31:02 2019 +0000
  7. eb195bd clk: sifive: Add clock driver for GEMGXL MGMT by Bin Meng · Wed May 22 00:09:44 2019 -0700
  8. 72be986 clk: sifive: fu540-prci: Change include order by Jagan Teki · Wed May 08 19:52:18 2019 +0530
  9. 42fdf08 clk: Add SiFive FU540 PRCI clock driver by Anup Patel · Mon Feb 25 08:14:49 2019 +0000