Log - d136654ba299c033985bdfaa35d57e04089cd8b0 - filogic/uboot

42e942f zynq: nand: Runtime detection of nand buswidth through slcr by Michal Simek · Wed Oct 26 10:49:37 2016 +0200
43246cc ARM: zynq: move SoC sources to mach-zynq by Masahiro Yamada · Mon Mar 16 16:43:22 2015 +0900[Renamed from arch/arm/cpu/armv7/zynq/slcr.c]
be0bf69 zynq: slcr: Disable all level shifters by Siva Durga Prasad Paladugu · Mon Mar 02 16:03:46 2015 +0530
250e605 ARM: zynq: slcr: Dont modify the reserved bits by Siva Durga Prasad Paladugu · Tue Oct 28 11:22:19 2014 +0530
ec02820 ARM: zynq: ehci: Added USB host driver support by Michal Simek · Fri Apr 25 12:21:04 2014 +0200
8d19162 ARM: zynq: Add MIO detection code by Michal Simek · Fri Apr 25 12:21:04 2014 +0200
bc73304 ARM: zynq: Setup correct slcr_lock value by Michal Simek · Fri Aug 30 07:26:08 2013 +0200
7cffeb0 ARM: zynq: slcr: Fix incorrect commentary by Michal Simek · Thu Mar 27 10:06:43 2014 +0100
90b8064 ARM: zynq: Fix sparse warnings in slcr.c by Michal Simek · Fri Apr 25 13:48:08 2014 +0200
4dded98 net: zynq_gem: Calculate clock dividers dynamically by Soren Brinkmann · Thu Nov 21 13:39:01 2013 -0800
3b5b992 net: zynq_gem: Move RCLK details out of driver by Soren Brinkmann · Thu Nov 21 13:39:00 2013 -0800
11704c2 zynq: Add support to find bootmode by Jagannadha Sutradharudu Teki · Thu Jan 09 01:48:21 2014 +0530
661ccfc zynq: slcr: Wait 100ms till clk is properly setup by Michal Simek · Wed May 08 15:37:28 2013 +0200
d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
15d654c fpga: zynq: Add support for loading bitstream by Michal Simek · Mon Apr 22 15:43:02 2013 +0200
d9f2c11 net: gem: Fix gem driver on 1Gbps LAN by Michal Simek · Mon Oct 15 14:01:23 2012 +0200
eb1dfa7 arm: zynq: Add SLCR support with system reset by Michal Simek · Mon Feb 04 12:38:59 2013 +0100