Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d0de5dc0fcb2e83d893a424cc1b5ba8a498d7b91 / drivers / clk / sunxi / clk_a80.c
  1. a0f27ba clk: sunxi: Add NAND clocks and resets by Samuel Holland · Sun Jan 22 16:06:31 2023 -0600
  2. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  3. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  4. 8443650 clk: sunxi: Store the array sizes in the CCU descriptor by Samuel Holland · Mon May 09 00:29:31 2022 -0500
  5. 3e9aa0b clk: sunxi: add PIO bus gate clocks by Andre Przywara · Wed May 04 22:10:28 2022 +0100
  6. fa7a7fa clk: sunxi: Add support for I2C gates/resets by Samuel Holland · Sun Sep 12 09:47:24 2021 -0500
  7. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  8. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  9. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  10. bc12313 clk: sunxi: Implement SPI clocks, resets by Jagan Teki · Wed Feb 27 20:02:06 2019 +0530
  11. 8c8c8a4 sunxi: clk: A80: add MMC clock support by Andre Przywara · Tue Jan 29 15:54:10 2019 +0000
  12. ddf33c1 sunxi: clk: add MMC gates/resets by Andre Przywara · Tue Jan 29 15:54:09 2019 +0000
  13. e366a0c clk: sunxi: Add Allwinner A80 CLK driver by Jagan Teki · Fri Jan 11 15:41:46 2019 +0530