Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d014e35e99b0430e2801394ae2b1c83867515081 / board / stxssa / ddr.c
  1. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  2. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  3. 0abad32 FSL DDR: Convert STXSSA to new DDR code. by Kumar Gala · 16 years ago