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git01.mediatek.com / filogic / uboot / cf1f4bb343ca1d19e09c89432367274786dfa873 / drivers / phy / marvell / comphy_a3700.h
  1. 81b1d62 phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization by Pali Rohár · Fri Sep 24 16:11:55 2021 +0200
  2. 2d72d04 phy: marvell: cp110: clean up driver after it was moved to atf by Grzegorz Jaszczyk · Wed Apr 04 16:42:43 2018 +0200
  3. 19ce44c phy: marvell: Support changing SERDES map in board file by Marek Behún · Fri Aug 17 12:58:51 2018 +0200
  4. 3c340ed phy: marvell: a3700: Save/restore selector reg in SGMII init by Marek Behún · Tue Apr 24 17:21:24 2018 +0200
  5. 79c115a phy: marvell: a3700: Fix SGMII cfg and stat register addresses by Marek Behún · Tue Apr 24 17:21:22 2018 +0200
  6. 2684a39 phy: marvell: a3700: revise the USB3 comphy setting during power on by zachary · Tue Apr 24 17:21:20 2018 +0200
  7. ef6f36e phy: marvell: a3700: Access USB3 register indirectly on lane 2 by Marek Behún · Tue Apr 24 17:21:18 2018 +0200
  8. a89ae13 phy: marvell: a3700: Don't create functional macro for each register by Marek Behún · Tue Apr 24 17:21:14 2018 +0200
  9. ee3e2f6 phy: marvell: a3700: Use reg_set16 instead of phy_write16 by Marek Behún · Tue Apr 24 17:21:13 2018 +0200
  10. 4c02f73 phy: marvell: a3700: Change return type of macro MVEBU_REG by Marek Behún · Tue Apr 24 17:21:12 2018 +0200
  11. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  12. 8dfa4ee marvell: comphy_a3700: fix bitmask by Andre Przywara · Wed Nov 16 00:50:10 2016 +0000
  13. 8f64e26 drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k by Stefan Roese · Mon May 23 11:12:05 2016 +0200