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git01.mediatek.com / filogic / uboot / cf1f4bb343ca1d19e09c89432367274786dfa873 / drivers / clk / sunxi / clk_h616.c
  1. a0f27ba clk: sunxi: Add NAND clocks and resets by Samuel Holland · Sun Jan 22 16:06:31 2023 -0600
  2. 1467d44 clk: sunxi: Add DE2 display-related clocks/resets by Samuel Holland · Mon Nov 28 01:02:24 2022 -0600
  3. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  4. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  5. 8443650 clk: sunxi: Store the array sizes in the CCU descriptor by Samuel Holland · Mon May 09 00:29:31 2022 -0500
  6. 2d1864f clk: sunxi: add and use dummy gate clocks by Andre Przywara · Thu May 05 01:25:43 2022 +0100
  7. 3e9aa0b clk: sunxi: add PIO bus gate clocks by Andre Przywara · Wed May 04 22:10:28 2022 +0100
  8. fa7a7fa clk: sunxi: Add support for I2C gates/resets by Samuel Holland · Sun Sep 12 09:47:24 2021 -0500
  9. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  10. e52dc3e clk: sunxi: Add support for H616 clocks by Jernej Skrabec · Mon Jan 11 21:11:52 2021 +0100