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git01.mediatek.com / filogic / uboot / ce64bd3ff0c8add9db0acef2370b6a03122f5b50 / drivers / clk / kendryte
  1. 8aa82e1 clk: Add support for the k210 clock driver pre-relocation by Sean Anderson · Thu Apr 08 22:13:08 2021 -0400
  2. 95d2724 clk: k210: Move the clint clock to under aclk by Sean Anderson · Thu Apr 08 22:13:07 2021 -0400
  3. afab998 clk: k210: Remove k210_register_pll by Sean Anderson · Thu Apr 08 22:13:06 2021 -0400
  4. 16e5c17 clk: k210: Fix PLL enable always getting taken by Sean Anderson · Thu Apr 08 22:13:05 2021 -0400
  5. e649ff3 clk: k210: Fix PLLs not being enabled by Sean Anderson · Thu Apr 08 22:13:04 2021 -0400
  6. 29ff16a clk: Update drivers to use -EINVAL by Simon Glass · Thu Mar 25 10:26:08 2021 +1300
  7. b213ffc clk: kendryte: no need to check argument of free() by Heinrich Schuchardt · Tue Sep 29 21:52:12 2020 +0200
  8. 510bca3 riscv: clk: Add CLINT clock to kendryte clock driver by Sean Anderson · Mon Sep 28 10:52:27 2020 -0400
  9. 4303396 clk: Drop dm.h header file in clk-provider.h by Simon Glass · Sun Jul 19 10:15:56 2020 -0600
  10. 4d88d96 clk: Add K210 clock support by Sean Anderson · Wed Jun 24 06:41:11 2020 -0400
  11. 65cd44e clk: Add a bypass clock for K210 by Sean Anderson · Wed Jun 24 06:41:10 2020 -0400
  12. 6e887ee clk: Add K210 pll support by Sean Anderson · Wed Jun 24 06:41:09 2020 -0400