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git01.mediatek.com / filogic / uboot / cb9c5d07ed2e510606c7e596645a3e091b24e197 / drivers / net / zynq_gem.c
  1. d9cfa97 net: gem: Enable CTRL+C in wait_for_bit by Michal Simek · Thu Sep 24 20:13:45 2015 +0200
  2. 3c4ce3c net: gem: Read information about interface from DT by Michal Simek · Mon Nov 30 14:17:50 2015 +0100
  3. 250e05e net: gem: Move driver to DM by Michal Simek · Mon Nov 30 14:14:56 2015 +0100
  4. 3f8c635 net: gem: Fix miiphy_read name by Michal Simek · Mon Nov 30 14:14:37 2015 +0100
  5. df3b414 net: gem: Remove zynq_gem_of_init() by Michal Simek · Mon Nov 30 14:00:20 2015 +0100
  6. e9ecc1c net: gem: Enable MDIO bus earlier by Michal Simek · Mon Nov 30 13:58:36 2015 +0100
  7. 2c68e08 net: gem: Check if priv->phydev is valid by Michal Simek · Mon Nov 30 14:03:37 2015 +0100
  8. 7cd7ea6 net: gem: Extract phy init code by Michal Simek · Mon Nov 30 13:54:43 2015 +0100
  9. 43b3832 net: gem: Remove phydev variable by Michal Simek · Mon Nov 30 13:44:49 2015 +0100
  10. 1a63ee2 net: gem: Change mii function not to use eth_device structure by Michal Simek · Mon Nov 30 10:24:15 2015 +0100
  11. 3ce1615 net: gem: Change mdio_wait prototype to pass regs by Michal Simek · Mon Nov 30 10:09:43 2015 +0100
  12. 75fbb69 net: gem: Do not continue if phy is not found by Michal Simek · Mon Nov 30 13:38:32 2015 +0100
  13. 728d32e net: zynq: Fix MDC setting for zynq by Michal Simek · Tue Sep 08 17:07:01 2015 +0200
  14. d5abec6 net: zynq: Remove unused MDCCLKDIV2 macro by Michal Simek · Tue Sep 08 16:54:39 2015 +0200
  15. 6429595 net: zynq: Fix mdc clock division setting for 100Mbit/s by Michal Simek · Tue Sep 08 16:55:42 2015 +0200
  16. 975ae35 net: zynq: Wait till packet is sent by Michal Simek · Mon Aug 17 09:57:46 2015 +0200
  17. 2304511 net: zynq: Disable secondary queues by Edgar E. Iglesias · Fri Sep 25 23:50:07 2015 -0700
  18. 1dc446e net: zynq: Add dummy packet to fix packet duplication issue by Michal Simek · Mon Aug 17 09:58:54 2015 +0200
  19. f91f7e5 net: zynq: Do not report TX underrun by Michal Simek · Mon Aug 17 09:51:34 2015 +0200
  20. b6fe7ad net: zynq: Setup BD when structures are filled by Michal Simek · Mon Aug 17 09:50:09 2015 +0200
  21. c6eb0bc net: zynq: Allocate BD_SPACE in connection to RX_BUF by Michal Simek · Mon Aug 17 09:45:53 2015 +0200
  22. ff5dbef net: zynq: Fix clearing statistic by Michal Simek · Mon Oct 05 12:49:48 2015 +0200
  23. 74a86e8 net: zynq: Extend register description with offsets by Michal Simek · Mon Oct 05 11:49:43 2015 +0200
  24. 492de0f net: zynq: Add support for different PHY interface types by Michal Simek · Wed Oct 07 16:42:56 2015 +0200
  25. c919c2c net: zynq: Add debug message to phyread/phywrite by Michal Simek · Wed Oct 07 16:34:51 2015 +0200
  26. 1e9e619 driver: net: Fix pointer conversion warnings for xilinx_zynqmp_ep by Prabhakar Kushwaha · Sun Oct 25 13:18:54 2015 +0530
  27. 366b24f of: clean up OF_CONTROL ifdef conditionals by Masahiro Yamada · Wed Aug 12 07:31:55 2015 +0900
  28. 3b4b5db net: gem: Extend timeout value by Michal Simek · Tue Oct 16 17:37:11 2012 +0200
  29. aaf9cc1 zynq: gem: Setting up WRAP bit for one TX bd by Michal Simek · Tue May 26 12:01:12 2015 +0200
  30. 55931cf zynq: gem: Increase the Rx buffer descriptors to 32 by Siva Durga Prasad Paladugu · Wed Apr 15 12:15:01 2015 +0530
  31. 2b0690e zynqmp: gem: Flush the rx buffers while transmitting by Siva Durga Prasad Paladugu · Sat Dec 06 12:57:53 2014 +0530
  32. 71245a4 zynqmp: gem: Set data bus width to 64bit for arm64 by Siva Durga Prasad Paladugu · Tue Jul 08 15:31:03 2014 +0530
  33. 0afb6b2 net: gem: Use correct type for casting by Michal Simek · Wed Apr 15 13:31:28 2015 +0200
  34. 9f09a36 net: cosmetic: Fix var naming net <-> eth drivers by Joe Hershberger · Wed Apr 08 01:41:06 2015 -0500
  35. 13b4d3c net: gem: Use phys_addr_t instead of int for addresses by Michal Simek · Wed Jan 14 15:44:21 2015 +0100
  36. b055f67 net: zynq: Fix sparse warnings in gem by Michal Simek · Fri Apr 25 14:17:38 2014 +0200
  37. 5031623 net: zynq: Use predefined macros instead of hardcoded value by Michal Simek · Tue Feb 25 10:25:38 2014 +0100
  38. 12dbc40 net: gem: Add OF initialization support by Michal Simek · Mon Feb 24 11:16:30 2014 +0100
  39. 4dded98 net: zynq_gem: Calculate clock dividers dynamically by Soren Brinkmann · Thu Nov 21 13:39:01 2013 -0800
  40. 3b5b992 net: zynq_gem: Move RCLK details out of driver by Soren Brinkmann · Thu Nov 21 13:39:00 2013 -0800
  41. 216b96d net: gem: Check if phy was correctly detected by Michal Simek · Tue Nov 12 14:25:29 2013 +0100
  42. cbf20b2 net: zynq_gem: Add d-cache support by Srikanth Thokala · Fri Nov 08 22:55:48 2013 +0530
  43. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  44. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  45. ab72cb4 net: gem: Add support for phy autodetection by Michal Simek · Mon Apr 22 14:41:09 2013 +0200
  46. 73875dc net: gem: Preserve clk on emio interface by David Andrey · Fri Apr 05 17:24:24 2013 +0200
  47. 1b0dd5e net: gem: Pass phy address to init by David Andrey · Thu Apr 04 19:13:07 2013 +0200
  48. d9f2c11 net: gem: Fix gem driver on 1Gbps LAN by Michal Simek · Mon Oct 15 14:01:23 2012 +0200
  49. a94f84d net: gem: Do not initialize BDs again by Michal Simek · Thu Jan 24 13:04:12 2013 +0100
  50. 3b9f30e net: gem: Simplify return path in zynq_gem_recv by Michal Simek · Fri Jan 25 08:24:18 2013 +0100
  51. bb2ad88 net: gem: Remove WRAP bit from TX buffer description by Michal Simek · Wed Oct 17 11:03:40 2012 +0200
  52. 19dfc47 net: Add driver for Zynq Gem IP by Michal Simek · Thu Sep 13 20:23:34 2012 +0000